KR19990006214A - Burn-in test board - Google Patents

Abstract

A burn-in socket for burn-in test of the plurality of semiconductor memory devices; A signal synthesizing means connected to all input / output terminals of the sockets and combining all output signals from the terminals to output a single fail test synthesized signal; A semiconductor memory device including a discrimination unit configured to discriminate a fail state of the semiconductor memory device, and output a discrimination result signal to the slot, and a slot for applying an output signal of the discrimination unit to the burn-in system Configure the burn-in test board.

Therefore, there is one discrimination unit corresponding to one semiconductor memory element, and the one discrimination unit is also constituted by one discrimination means for generating one output per semiconductor memory element.

Description

Burn-in test board

The present invention relates to a burn-in test, and more particularly, to a burn-in board for a burn-in test that can increase the number of testable semiconductor memory devices at a time.

In general, after the semiconductor device is manufactured, various tests are performed to ensure the reliability of the product. The burn-in test is one of the tests. The input and output terminals of the semiconductor device are connected to the test signal generation circuit to apply stress at a higher temperature, voltage, and current than the normal operating conditions, and to determine whether the semiconductor device has a long life or defect. This is a test to check.

As a result, the burn-in test must have a fault that can cause some disturbance when used under normal conditions. The burn-in test therefore ensures product reliability by detecting and removing defective semiconductor devices during the test.

In a conventional burn-in test, when a burn-in stress is applied to a semiconductor device or a test during burn-in (TDBI) is performed, data is controlled separately for the input and output of the semiconductor device, and the input / output terminals set in the burn-in system and the burn-in board are used. The burn-in test was carried out limited to the number of. As a result, the number of memory devices tested simultaneously in one burn-in test was small.

1 shows a conventional burn-in test board compatible with a TDBI system. Burn-in test board 100 is provided with eight blocks having 32 burn-in sockets 110 for mounting the test semiconductor device.

Referring to FIG. 1, it is assumed that the maximum number of input / output terminals supported by the burn-in test board is 72. Using 16M (2M × 8) DRAM as an example, when 256 DRAMs are mounted on a burn-in board and performing TDBI, eight DRAMs corresponding to a total of 64 input / output terminals can be simultaneously tested in one burn-in test.

In addition, the determination unit 120 as shown in FIG. 2 is provided between the slot 130 of the board and the socket 110. The determination unit 120 includes first to eighth comparison means COMP1 to COMP8 connected to the data input / output terminals of the socket 110 in which the test DRAM is mounted.

The output signal of the determination unit 20 is applied to the slot 120, and is externally read to determine a pass / fail for the test DRAM.

First, the data output value expected for the data value input to the DRAM is set as follows. The minimum value of the high level data expected as the output is set to V _OH , and the maximum value of the low level data expected as the output is set to V _OL and the V _OH and V _OL are input to the comparison means COMP1 to COMP8, respectively. . After the burn-in stress is applied, the output signal output from the DRAM input / output terminal is input to each of the comparison means COMP1 to COMP8 corresponding to the input / output terminal. The comparison means COMP1 to COMP8 compare the input data V _OH and V _OL with output values from the DRAM and apply them to the slot 120.

At this time, the comparison means in the determination unit 130 outputs the high-potential output signal when the output data does not fail, and outputs a low-potential output signal when the failure occurs (not shown). ) Determines the pass / fail of the DRAM from the output signal of the determination unit 130 applied through the slot 120.

At this time, 32 test scans should be performed to test all 256 DRAMs mounted on the burn-in board. If the time required for one test scan is 100 seconds, it is 32 times 100 seconds, which takes a total of 3200 seconds.

An object of the present invention is to provide a burn-in test burn-in board that can reduce the test scan time required to test all the semiconductor memory devices mounted on the burn-in board by increasing the number of testable semiconductor memory devices at a time. It is done.

An object of the present invention as described above is to determine whether an input terminal of a socket is mounted between a socket and a slot in which a semiconductor memory device is mounted, and all input / output terminals of the socket are connected to an input terminal of a single NAND gate. This is achieved by providing only one discriminating unit, i.e., by having one output for determining one pass / fail per memory element.

1 is a typical burn-in test board.

Fig. 2 is a conventional discriminating part connected to the burn-in socket on the burn-in test board shown in Fig. 1;

3 is a discriminating unit according to the present invention connected to a burn-in socket on the burn-in test board shown in FIG.

Explanation of symbols for main parts of the drawings

100: burn-in test board 110: burn-in socket

120: slot 130: determination unit

MEM: semiconductor memory device

A burn-in socket for burn-in test of the plurality of semiconductor memory devices; A signal synthesizing means connected to all input / output terminals of the sockets and combining all output signals from the terminals to output a single fail test synthesized signal; A semiconductor memory device including a discrimination unit configured to discriminate a fail state of the semiconductor memory device, and output a discrimination result signal to the slot, and a slot for applying an output signal of the discrimination unit to the burn-in system Configure the burn-in test board.

Therefore, there is one discrimination unit corresponding to one semiconductor memory element, and the one discrimination unit is also constituted by one discrimination means for generating one output per semiconductor memory element. In addition, only the output signal of the determination unit is used as a burn-in test target signal. Therefore, in one burn-in test, the number of controllable semiconductor memory devices in the burn-in test board for semiconductor memory devices can be increased.

EXAMPLE

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Fig. 1 shows a burn-in test board of a general semiconductor memory element, and Fig. 3 shows a circuit diagram of a discriminating unit connected to the burn-in socket on the burn-in test board shown in Fig. 1 according to the present invention.

1 and 3, a burn-in socket 110 for burn-in test of a plurality of 2M × 8 semiconductor memory devices MEM; An eight-input NAND gate 131 connected to all input / output terminals of the sockets 110 and combining eight output signals from the eight terminals to output one fail test composite signal; and the NAND gate 131 A discriminating unit 130 comprising a determining unit 132 for inputting a synthesized signal of?) And comparing the reference signals VOH and VOL to a fail state of the semiconductor memory device MEM; And a slot 120 for applying the output signal of 130 in the burn-in system.

In the discriminating means 132, the first comparator COMP1321 uses the high potential reference signal VOH as the first input and the output signal of the NAND gate 131 as the second input. The input signals are compared only when the data input to MEM) is at high potential. The second comparator COMP1322 uses the low potential reference signal VOL as the first input, the output signal of the NAND gate 131 as the second input, and the data input to the semiconductor memory device has a low potential. Only compare the input signal. In addition, when the Storobe signal STRB is applied, one of the output signal of the first comparator COMP1321 and the output signal of the second comparator COMP1322 with respect to the output of the NAND gate 131 may be compared to the slot (SB). 120).

At this time, the high potential reference signal is the lowest voltage of the high potential level at which the output is expected from the semiconductor memory element, and the low potential reference signal is set to the highest voltage at the low potential level at which the output is expected from the semiconductor memory element. .

First, a low potential signal is applied to all the semiconductor memory devices MEM for burn-in test. Subsequently, all eight output signals output from the semiconductor memory device MEM are combined through the NAND gate 131. In this case, an output signal of one NAND gate 131 is applied to the determination unit 132.

That is, one output signal of the NAND gate 131 is applied as a second input signal of the first comparator COMP1321 and the second comparator COMP1322, respectively. In this case, the first comparator COMP1322 outputs a high potential output signal when the high potential reference signal VOH is smaller than the output signal of the NAND gate 131, and the second comparator COMP1322 outputs a low potential reference signal VOL. Outputs a high potential output signal when the high potential reference signal VOH is smaller than the output signal of the NAND gate 131.

In the normal operation, since all eight output signals output from the semiconductor memory device MEM are low potential, the output signal of the NAND gate 131 becomes high potential. In addition, since all input signals input to the semiconductor memory device MEM are low potential, only the second comparator COMP1322 of the discriminating means 132 compares and outputs the input signals.

Since the output of the NAND gate 131 has a low potential value, the output of the second comparator COMP1322 becomes a high potential.

On the other hand, when a failure occurs, one or more high-potential output signals are generated from the semiconductor memory MEM. Therefore, the output of the NAND gate 131 becomes high potential. Further, since all input signals input to the semiconductor memory device MEM are low potential, only the second comparator COMP1322 of the discriminating means 132 compares and outputs the input signals. Therefore, since a signal with a high potential larger than the low potential reference signal is input, a low potential signal is output.

One determination unit 130 is provided per one semiconductor memory element MEM, and one determination unit 130 includes two comparators COMP1321 and COMP1322, so that the number of comparators is reduced compared to the conventional determination unit. do. In addition, if the number of I / O terminals provided to be tested on one board is 64, burn-in test of 64 semiconductor memory devices becomes possible. That is, the number of semiconductor memory devices tested at one time is increased by eight times compared to the eight burn-in tests possible in the related art. Therefore, when all the semiconductor memory devices mounted on the burn-in test board are burned-in, the number of test scans is reduced by 1/8 times, and the time required for burn-in is reduced to 1/8.

According to the above configuration, since one burn-in test result value is output for one semiconductor memory device, the number of semiconductor memory devices that can be burned in at one time increases with respect to the number of input / output terminals supported by the burn-in test board. Therefore, it is possible to increase the burn-in speed.

Claims (7)

Burn-in socket for burn-in test of a plurality of semiconductor memory devices, A discriminating unit connected to all input / output terminals of the burn-in sockets and generating a signal for determining a pass / fail of the semiconductor memory device by inputting an output signal of the burn-in socket; In the burn-in test board of the semiconductor memory device comprising a slot for applying the output signal of the discrimination unit to the burn-in system, The determination unit is connected to all the input and output terminals of the sockets, the signal combining means for outputting a combined test signal for the fail test by combining all the output signals from the input and output terminals; And determining means for inputting the synthesized signal of the signal synthesizing means, determining a fail state of the semiconductor memory device by comparing with reference signals, and outputting a determination result signal to the slot. Burn-in test board. The burn-in test board of claim 1, wherein the signal synthesizing means comprises a NAND gate configured to input an output signal of the burn-in socket. The input signal according to claim 1, wherein the discriminating means uses a high potential reference signal as a first input, an output signal of the signal synthesizing means as a second input, and an input signal only when the data input to the semiconductor memory element is high potential. With a first comparator comparing the A second comparator for comparing the input signal only when the low potential reference signal is the first input, the output signal of the signal synthesizing means is the second input, and the data input to the semiconductor memory device is low potential; Burn-in test board, characterized in that configured to apply one of the output signal of the first comparator and the output signal of the second comparator to the slot. 4. The burn-in test board according to claim 3, wherein the first comparator outputs a high potential signal when the first input signal is smaller than the second input signal. 4. The burn-in test board according to claim 3, wherein the second comparator outputs a high potential signal when the first input signal is larger than the second input signal. 4. The burn-in test board according to claim 3, wherein the high potential reference signal is the lowest voltage of the high potential level at which the output from the semiconductor memory device is expected. 4. The burn-in test board according to claim 3, wherein the low potential reference signal is the highest voltage of the low potential level at which the output from the semiconductor memory device is expected.