KR19980085088A - Virtual memory system and its processing method - Google Patents

Abstract

The present invention relates to a virtual memory system for classifying a page number of a virtual address to access a physical address, comprising: page number classification means for classifying a page number of a virtual address into a page directory number, a page table number, and a page offset; A page directory number and a page table number are respectively determined by the comparator for comparing whether the page table numbers transmitted from the page number classification means and the page table tag match, and the signals transmitted from the page directory tag and the comparator, respectively. Page number determining means for determining whether a page table tag exists, and enabling to determine whether to enable the conversion index buffer by signals transmitted from the page directory tag and the comparator, respectively. Determination means, converting a data selector for selecting and outputting the data transferred from the cache memory by a signal transmitted from the physical address tag and the page number determination means for storing the physical address transmitted from the buffer index.

Description

Virtual memory system and processing method thereof.

The present invention relates to a virtual memory system, and more particularly, to a virtual memory system and a processing method thereof for classifying page numbers of virtual addresses to access a physical address.

In general, in order to write or read data in a memory in a virtual memory system, a virtual address is first created, and then the address is converted into a physical address of a memory having desired data.

In addition, as the time required for memory access becomes a major factor that determines the performance of the virtual memory system, the virtual cache memory is used to reduce the time for the data processing CPU to access the data.

In other words, the method of accessing cache memory previously used a virtual address to reduce the time required for address translation while using a physical address.

Referring to FIG. 1, a conventional virtual memory system includes a tag memory 10 storing a virtual address transferred through an internal bus, a cache memory 20 storing data to be accessed, and a tag decoded by a virtual address. A decoder 30 which transmits a decoding signal for selecting and enabling the tag entry 11 and the cache entry 22 of the memory 10 and the cache memory 20, respectively, and a virtual address and tag memory transferred from the inside. The comparator 40 for comparing the virtual addresses delivered from the tag entry 11 of 10 and outputting a comparison result, and the cache entry 21 of the cache memory 20 by a signal transmitted from the comparator 40. And a data selector 50 for outputting data to be accessed from.

Referring to the operation of the conventional virtual memory system having the above structure is as follows.

Predetermined bits of the virtual address passed through the bus to the comparator 40 are passed through the bus to the decoder 30 to decode the decoder 30, which then decodes the tag memory 10 and the cache memory ( Each of the tag entry 11 and the cache entry 22 of 20 is selected and delivered with a decoding signal for enabling.

In this way, the enabled tag memory 10 transmits the page number of the virtual address stored through the tag entry 11 to the comparator 40, and the comparator 40 then transfers the page of the virtual address transferred from the internal bus. If the page number is equal to the page number of the virtual address transmitted from the tag memory 10, and if the comparison result is the same, the signal HIT SIGNAL is transmitted to the data selector 50. (MISS SIGNAL) is passed to the data selector 50.

When the match signal is transmitted from the comparator 40, the data selector 50 selects and outputs data transmitted through the bus from the cache entry 21 of the cache memory 20.

On the other hand, when the inconsistency signal is transmitted from the comparator 40, the data selector 50 requests data from the external memory through a path not shown in FIG. 1 without outputting the data of the cache memory 20.

However, in the conventional virtual memory system as described above, there is a problem in that it takes a relatively long time by comparing the page numbers of the virtual addresses and accessing the physical addresses by the comparison result.

Accordingly, the present invention is to solve the above problems, the page number of the virtual address is classified into the page directory number and the page table number to compare the page numbers of the virtual address and access the physical address by the comparison result to access time The purpose is to provide a virtual memory system that can reduce the number of times.

1 is a block diagram of a conventional virtual memory system.

2 is a block diagram of a virtual memory system in accordance with an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100: page number classification means 110: page table tag

120: page directory tag 130: comparator

140: page number determination means 150: conversion index buffer

160: enable determination means 170: physical address tag

180: cache memory 190: data selector

200: main memory

In order to achieve the above object, the present invention provides a cache memory for accessing and outputting desired data by a decoded enable signal, a data selector for selecting and outputting data transferred from the cache memory by a selection control signal; In a virtual memory system having a translation index buffer that temporarily stores and outputs transmitted data to speed up data processing, a page for classifying a page number of a virtual address into a page directory number, a page table number, and a page offset. Number classification means;

A page directory tag for comparing a page directory number transmitted from the page number classification means with a previously stored page directory number and outputting a comparison result; A page table tag for conveying a page table number already stored by a page offset which is a predetermined bit value decoded to select an entry transferred from the page number sorting means; A comparator for comparing whether the page table numbers transmitted from the page number sorting means and the page table tag respectively match; Page number determination means for determining whether a page directory number and a page table number exist in the page directory tag and the page table tag, respectively, by the signals transmitted from the page directory tag and the comparator; Enable determining means for determining whether to enable the translation index buffer by the signals transmitted from the page directory tag and the page table tag, respectively; A physical address tag for storing the physical address carried from the translation index buffer.

Hereinafter, a preferred embodiment of the present invention will be described with reference to FIG. 2.

Referring to FIG. 2, the virtual memory system of the present invention includes a page number sorting means 100 for classifying a page number of a virtual address into a page directory number, a page table number, and a page offset, and a page number sorting means 100. And a comparator 130 for comparing whether the page table numbers transmitted from the page table tag 110 match, and the page directory tag 120 according to the page directory number and the page table number transmitted from the page number sorting means 100. And page number discrimination means 140 for determining whether the page directory number and the page table number exist in the page directory tag and the page table tag by the signals transmitted from the comparator 130 and the comparator 130, respectively. And the conversion index by the signal transmitted from the comparator 140, respectively Enable determination means 160 for determining whether to enable the fur 150, a physical address tag 170 for storing a physical address transferred from the translation index buffer 150, and a page number determination means ( And a data selector 190 for selecting and outputting data transmitted from the cache memory 180 by the signal transmitted from the 150.

The page number sorting means 100 is built in the CPU.

The page number discrimination unit 140 includes an AND gate AG for logic and outputting the output signal of the page directory tag 120 input to one input terminal and the output signal of the comparator 130 input to the type force stage.

The enable determination unit 160 includes a NAND gate NG for logical NAND output signal of the page directory tag 120 input to one input terminal and output signal of the comparator 130 input to the type force stage.

Referring to the operation of the virtual memory system of the present invention having the above structure is as follows.

The page number classification means 100 classifies the page number of the delivered virtual address into a page directory number, a page table number and a page offset, and then transfers the page directory number to the page directory tag 120 and the translation index buffer 150. The page table number is transmitted to the comparator 130 and the translation index buffer 150, and the page offset is transmitted to the page table tag 110, the cache memory 180, and the physical address tag 170.

The page directory tag 120 transmits a match signal (HIT SIGNAL) to the page number determining unit 140 and the enable determining unit 160, respectively, if the transmitted page directory number matches the page directory number already stored. If not, it transmits a mismatch signal.

The page table tag 110 transmits the page table number stored in the entry 110-1 to the comparator 130 by the delivered page offset.

When the page table number transmitted from the page sorting means 100 and the page table number transmitted from the entry 110-1 of the page table tag 110 coincide with each other, the comparator 130 sets a match signal (HIT SIGNAL) to the page number. The signal is transmitted to the determination means 140 and the enable determination means 160, and if not matched, the mismatch signal MISS SIGNAL is transmitted.

The AND gate AG of the page number determining unit 140 logic-ends the output signal of the page directory tag 120 transmitted to one input terminal and the output signal of the comparator 130 transferred to the type force stage. Is output to the data selector 190. In this case, the page number determining unit 140 determines that the page directory number and the page table number exist in the page directory tag 120 and the page table tag 110 only when the coincidence signal is input to all input terminals. A coincidence signal for enabling 190 is output; otherwise, a mismatch signal for disabling data selector 190 is output.

The enable determination unit 140 logics the NAND gate NG to NAND gate NG by outputting the output signal of the page directory tag 120 transmitted to one input terminal and the output signal of the comparator 130 transferred to the type force stage. Is output to the conversion index buffer 150. At this time, the enable determination unit 140 determines that a discrepancy signal is input to any input terminal, that is, the page directory number and the page table number are not present in the page directory tag 120 or the page table tag 110, respectively. The enable signal for enabling the conversion index buffer 150 is output. Otherwise, the disable signal for disabling the data selector 190 is output.

When the enable signal is input from the enable determining means 160, the translation index buffer 150 enables the page directory number and the page table numbers of the virtual addresses transmitted from the page number classification means 100 to the main memory 200. ) Is converted into a physical address for access and the translated physical address is stored in the entry 170-1 of the physical address tag 170, or the translation index buffer 150 is disabled from the enable determination means 160. Even if a signal is input, it may be operated regardless of the input signal.

By the above process, the physical address is stored in the entry 170-1 of the physical address tag 170, and the external snooping according to the coherency protocol such as the multiprocess system can be processed. .

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes are possible within the scope of the present invention without departing from the technical idea. It will be evident to those who have knowledge of.

As described above, the virtual memory system of the present invention needs to increase the cache size in order to increase the cache hit ratio. However, in order to overcome the disadvantage that the page number tag is proportionally large, a small number of page directory tag entries may be provided. Effective for large-capacity cache designs, reducing the latency and power of these operations by invalidating only the page directory tag portion during cache flush and cache invalidation, and in the case of virtual caches using virtual page numbers, By using the error signal in the fast page directory tag as a cache error signal that controls the operation of the translation index buffer for obtaining an address, it is possible to quickly control the operation of the translation index buffer in error. pay Classified table number to be compared, and the page number of the virtual address and reduce the access time for access to a physical address by the comparison result, and also provides an effect to improve the efficiency of the access when the power of the physical address.

Claims (5)

A cache memory for accessing and outputting desired data by a decoded enable signal, a data selector for selecting and outputting data transferred from the cache memory by a selection control signal, and a data selector for speeding up data processing. In the virtual memory system having a translation index buffer for temporarily storing and outputting, Page number sorting means for classifying a page number of a virtual address into a page directory number, a page table number, and a page offset; A page directory tag for comparing a page directory number transmitted from the page number classification means with a previously stored page directory number and outputting a comparison result; A page table tag for conveying a page table number already stored by a page offset which is a predetermined bit value decoded to select an entry transferred from the page number sorting means; A comparator for comparing whether the page table numbers transmitted from the page number sorting means and the page table tag respectively match; Page number determination means for determining whether a page directory number and a page table number exist in the page directory tag and the page table tag, respectively, by the signals transmitted from the page directory tag and the comparator; Enable determining means for determining whether to enable the translation index buffer by the signals transmitted from the page directory tag and the page table tag, respectively; And And a physical address tag for storing a physical address carried from the translation lookaside buffer. The method of claim 1, The page number classification means Virtual memory system, characterized in that embedded in the central processing unit. The method of claim 1, The page number determining means And an AND gate for logic and outputting the output signal of the page directory tag input to one input terminal and the output signal of the comparator input to a type force stage. The method of claim 1, The enable determination means And a NAND gate configured to logically NAND an output signal of the page directory tag input to one input terminal and an output signal of the comparator input to a type force stage. Classifying the page number of the virtual address into a page directory number, a page table number, and a page offset to deliver a classified result; Outputting a comparison result by comparing the page directory number transmitted from the page number classification means with a previously stored page directory number; Conveying a page table number already stored by a page offset which is a predetermined bit value decoded to select an entry transferred from the page number sorting means; Comparing the page table numbers delivered from the page number classification means and the page table tag with each other and delivering a comparison result; Determining whether a page directory number and a page table number exist in the page directory tag and the page table tag by the signals transmitted from the page directory tag and the comparator, respectively, and output a determination result; Determining whether to enable a conversion index buffer by the signals transmitted from the page directory tag and the page tag, respectively, and outputting a determination result; Storing data transferred from the translation lookaside buffer; Accessing data already stored by the page offset transferred from the page number sorting means; And And selecting and outputting the data transferred from the cache memory by the signal transmitted from the page number determining means.