KR19980068043A - Method of forming pad layer in manufacturing process of semiconductor device - Google Patents

Abstract

The present invention discloses a method of forming a pad layer in a manufacturing process of a semiconductor device.

In the method for forming a pad layer in the semiconductor device manufacturing process according to the present invention, the second spacer is formed on the side of the photoresist pattern defining the pad layer region even though the dual pad layer is formed, and the material formed under the photoresist pattern using the second spacer as an etching mask. The width of the two pad layers formed by patterning the films may be about twice as wide as the width of the second spacer. In addition, since the first insulating film is covered on the gate electrode in the process of patterning the material film under the photosensitive film pattern, sufficient transient etching may be performed to prevent the bridge from being formed between the two pad layers.

As a result, a dual pad layer having a wide width and no cross bridge is formed. This result can bring a wide process margin in the subsequent process of exposing the interface of the two pad layer, it is easy to bring the manufacturing process of the semiconductor device even at high integration speed.

Description

Method of forming pad layer in manufacturing process of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a pad layer in a semiconductor device manufacturing process, and more particularly to a method of forming a dual pad layer.

As the memory capacity required by the memory device is increased, the number of unit cells constituting the memory device must be increased. If the size of the memory device is increased, this operation can be easily performed. However, when the size of the memory device increases, the space occupied by the memory device becomes wider, and thus the workspace cannot be used efficiently. In particular, in a situation where high integration of semiconductor devices is increasing, large memory devices are forced to be removed. As a result, memory cells have been made as small as possible by increasing cell density per unit area of the substrate.As a result, memory devices that have a much wider range of functions than the conventional ones and have sizes that are incomparably smaller than conventional ones have emerged. have.

As the semiconductor devices have been highly integrated, difficulties that have not been encountered in the past have emerged. This difficulty is mainly due to a smaller area for forming unit cells allocated to the substrate.

For example, a bit line in a cell array may be formed in a semiconductor device. The bit line should be configured without contact with a cell transistor or a cell capacitor. Contact opportunities are increasing.

Therefore, in order to manufacture a semiconductor device of about 1 gigabyte DRAM (GDRAM), a cell inevitably needs to be configured in three dimensions. In this case, the cell capacitor contact is formed in a straight line in one direction (for example, in the X-axis direction). Therefore, when the bit line is formed, the Y-axis coordinates should be different while different steps from the cell capacitors in order to be wired in the same direction as the cell capacitor contacts without contacting the contact of the cell capacitors. In this way, a pad poly process is used in the middle to form the bit line. However, when the pad poly process is used, overetching is performed in the pad poly process to prevent the bridges between the pads from being formed. This overetch causes the bit line contacts formed in the previous step to be recessed to reduce the misalignment margin with the gate poly in the next bit line contact forming process.

To improve this, a dual pad process has recently been used. A conventional technique for forming a pad layer of a semiconductor device using the dual pad process will be described in detail with reference to the accompanying drawings.

First, an example of a pad layer forming method in a manufacturing process of a semiconductor device according to the prior art will be described with reference to FIGS. 1 to 5.

Referring to FIG. 1, an isolation layer 24 is formed on a semiconductor substrate 22 to separate a substrate into an active region and an inactive region, and then, for example, polysilicon doped with impurities is deposited on the semiconductor substrate. The gate 26 is then patterned to form an insulating material on the resultant, and then an interlayer insulating layer 28 in the form of a spacer is formed through an etch back.

Referring to FIG. 2, a first conductive layer that completely fills the valleys between the gate and the gate by depositing a conductive material such as polysilicon doped with impurities on the resultant of FIG. 1 and then etching it back 30 is formed.

Subsequently, an oxide layer 32 or a nitride layer is formed as an etch stop layer on the resultant on which the first conductive layer is formed, and polysilicon doped with impurities is deposited thereon to form a second conductive layer 34.

Next, a photoresist pattern 38 defining a region where the pad layer is to be formed is formed in a portion corresponding to the drain region on the second conductive layer 34 through a photolithography process. In this case, the photoresist pattern 38 is preferably formed to a size smaller than the size of the pad layer to be formed.

Referring to FIG. 3, after patterning the second conductive layer 34 using the photoresist pattern (reference numeral 36 of FIG. 2) as an etching mask, the photoresist pattern is removed, and the second conductive layer ( The oxide film 32 is etched using the etching selectivity between 34 and the lower oxide film 32. Subsequently, an oxide film is deposited on the entire surface of the resultant material and then etched back to form spacers 38 on sidewalls of the second conductive layer 34 and the oxide film 32.

Referring to FIG. 4, when anisotropic etching is performed on the resultant of FIG. 3, a pad layer 30a that is limited to each cell unit as shown and connected to a drain region (not shown) may be formed. . In the anisotropic etching process, the spacer 38 is used as an etching mask, and the first conductive layer formed between the spacer and the neighboring spacer is also etched to form the pad layer 30a in a shape defined for each cell unit.

Referring to FIG. 5, after the oxide film (reference numeral 32 of FIG. 4) and the spacer (reference numeral 38 of FIG. 4) are removed, an interlayer insulating layer 40 is formed on the resultant, and a conventional capacitor forming process is performed. By proceeding, a DRAM memory cell as shown is completed. Reference numeral 42 denotes a storage electrode.

According to the embodiment of the present invention described above, it is possible to form the pad layer without forming a fine contact pattern as in the prior art.

Next, another example of the pad layer forming method in the manufacturing process of the semiconductor device according to the prior art will be described.

6 and 7 are diagrams illustrating step-by-step methods of forming a pad layer in a manufacturing process of a semiconductor device according to another example of the prior art.

Referring to FIG. 6, after the process of forming the first conductive layer 30 is performed in the same manner as in the first embodiment of the present invention, an oxide film (reference numeral 32 of FIG. 2) is not formed, and the first conductive layer ( A photoresist pattern 36 is formed directly on 30. In addition, an oxide film that can be deposited at a low temperature is deposited and etched back on the entire surface of the resultant to form a spacer on the sidewall of the photoresist pattern 38.

Referring to FIG. 7, the first conductive layer formed between the spacer and the spacer adjacent to the first conductive layer using the spacer 38 and the photoresist pattern (reference numeral 36 of FIG. 6) as an etching mask. By performing anisotropic etching so that this is completely removed, the pad layer 30a of the shape limited to each cell unit is formed.

Subsequent processes are performed to form the lower electrode of the capacitor, as shown in FIG. 5.

Next, another example of the pad layer forming method in the manufacturing process of the semiconductor device according to the prior art will be described.

8 to 13 are steps illustrating a method of forming a pad layer in a process of manufacturing a semiconductor device according to another prior art.

FIG. 8 illustrates a step of defining a bit line contact and a capacitor contact area. Specifically, the semiconductor substrate 50 is divided into active and inactive regions, and then a field oxide film (not shown) is formed in the non-active region. do. Subsequently, the gate electrode 52 is formed in the active region to be spaced apart by a predetermined interval, and the gate space 54 is formed on the side surface of the gate electrode 52. Subsequently, the gate space 54 is formed, and then the first insulating film 56 is formed on the entire surface of the semiconductor substrate 50, and then the entire surface is planarized within the range where the gate electrode 52 is not exposed. Next, a photosensitive film (not shown) is coated on the entire surface of the first insulating film 56 and then patterned to expose the interface of the first insulating film 56 corresponding to the active region between the gate electrodes 52. ). Next, the entire surface of the first insulating film 56 is anisotropically etched using the photoresist pattern 58 as an etching mask. Anisotropic etching is performed until the active region of the semiconductor substrate 50 is exposed. By anisotropic etching, the first insulating layer 56 is patterned to remain only in the portion masked by the photoresist pattern 58, and the unmasked region by the photoresist pattern 58 is completely removed to expose the active region of the substrate 50. Let's do it. In this way, the bit line contact 59 and the capacitor contact 59a are formed in the first insulating film 56. Thereafter, the photoresist pattern 58 is removed. To form the insulating film spacer (62 of FIG. 10) on the entire surface of the resultant having the photoresist pattern 58 removed thereon, as shown in FIG. 9, to further secure the sidewall of the first insulating film pattern 56a and the gate side. The second insulating film 60 is formed. Subsequently, the entire surface of the second insulating film 60 is anisotropically etched until the interface of the semiconductor substrate 50 is exposed. Due to the anisotropic etching property, the second insulating film 60 is completely removed in the flat region of the second insulating film 60, and the insulating film spacer 62 is formed on the side surface of the first insulating film pattern 56a as shown in FIG. 10. do. In this way, a bit line contact 59 and a capacitor contact 59a are formed between the gate electrodes 52.

FIG. 11 is a view illustrating a step of forming an anti-reflection coating (hereinafter referred to as ARC). Specifically, the bit line contact (or a bit line contact) is formed on the entire surface of the resultant formed with the bit line contact 59 and the capacitor contact 59a. 59 and the first conductive layer 64 filling the capacitor contact 59a are formed. Subsequently, ARC is formed on the entire surface of the first conductive layer 64. The first conductive layer 64 is formed of a doped polysilicon layer.

12 is a view illustrating a step of defining an area to be used as a pad layer. Specifically, a photoresist film (not shown) is coated on the entire surface of the resultant material of FIG. 11 and then patterned to form at least the bit line contact 59 and the capacitor contact ( A photosensitive film pattern 68 covering 59a) is formed. Subsequently, the entire surface of the ARC 66 is anisotropically etched using the photoresist pattern 68 as an etch mask. The anisotropic etch 70 is performed until the interface of the first insulating layer pattern 56a is exposed. Thereafter, the photoresist pattern 68 is removed. As a result of the anisotropic etching 70, the bit line contact 59 and the capacitor contact 59a are in contact with the substrate 50 and partially extended onto the first insulating layer pattern 56a as shown in FIG. 13. The capacitor contact pad layer 64a is formed and a portion of the ARC pattern 66a remains on the pad layer 64a. The subsequent process is not shown in the figure, but the interlayer insulating film is formed on the entire surface of the resultant, the bit line contact pad layer is exposed, the bit line is wired, and then the interlayer insulating layer is formed on the entire surface of the resultant bit line again, and then the capacitor contact. The pad layer is exposed to form the lower electrode of the capacitor.

As such, when the bit line contact pad layer and the capacitor contact pad layer are formed together, the margin of the bit line contact becomes very good, but there is a problem in that the distance between the two contact pad layers becomes very narrow. Therefore, there is a possibility that a bridge is formed between the two pad layers, which increases rapidly as the semiconductor device becomes more integrated. This problem can be solved by slightly reducing the width of the capacitor contact pad layer. In this case, however, the margin is reduced in the process of exposing the capacitor contact pad layer after forming the bit line, thereby exposing a part of the gate electrode. It can cause more serious problems.

Accordingly, an object of the present invention is to provide a semiconductor device capable of greatly reducing the possibility of forming a bridge between two pad layers while simultaneously forming a wide bit line contact pad layer and a capacitor contact pad layer. The present invention provides a method for forming a pad layer in a manufacturing process.

1 to 5 are diagrams showing step-by-step method for forming a pad layer in a semiconductor device manufacturing process according to the prior art.

6 and 7 are diagrams illustrating step-by-step methods of forming a pad layer in a manufacturing process of another conventional semiconductor device.

8 to 13 are steps illustrating a method of forming a pad layer in a process of manufacturing a semiconductor device according to another prior art.

14 to 20 are diagrams illustrating step-by-step methods of forming a pad layer in a manufacturing process of a semiconductor device according to an embodiment of the present invention.

Explanation of Signs of Major Parts of Drawings

80: semiconductor substrate 82: first spacer

86: first insulating film 90: second insulating film

100: third insulating film 102: second spacer

106, 108: bit line and capacitor contact pad layers.

In order to achieve the above object, the method for forming a pad layer in the manufacturing process of a semiconductor device according to the present invention comprises the steps of: (a) dividing the entire surface of the semiconductor substrate into an active region and an inactive region; (b) forming a field oxide film on the inactive region; (c) forming a gate electrode in the active region; (d) forming a gate spacer on the side of the gate electrode; (e) forming a first insulating film pattern having a bit line contact and a capacitor contact between the gate electrode on the resultant product; (f) forming a first spacer on a side of the first insulating film pattern; (g) forming a conductive layer filling the bit line contact and the capacitor contact in front of the resultant; (h) applying an antireflection film to the entire surface of the conductive layer; (i) forming a photoresist pattern on the anti-reflection film that covers at least the bit line contacts and the capacitor contacts; (j) forming a second spacer on a side surface of the photoresist pattern; (k) etching the anti-reflection film by using the photoresist pattern and the second spacer as an etching mask; (l) anisotropically etching the entire surface of the resultant until the interface of the first insulating film pattern is exposed using an emitter having an excellent etching selectivity compared to an oxide film; And (m) removing the second spacer and the anti-reflection film from the resultant.

The step (e) may include (e1) forming a first insulating film on the entire surface of the resultant product in which the gate electrode and the gate spacer are formed; (e2) planarizing the entire surface of the first insulating film; (e3) forming a photoresist pattern on the planarized first insulating layer to cover the gate electrode and a gate spacer on a side thereof; (e4) anisotropically etching the first insulating film until the interface of the substrate is exposed using the photoresist pattern as an etching mask.

Step (f) may include forming a second insulating film on the entire surface of the resultant product on which the first insulating film pattern is formed; And anisotropically etching the entire surface of the second insulating layer until the interface of the substrate is exposed.

In the step (m), the second spacer and the anti-reflection film are removed using a wet etching method.

Step (j) comprises the steps of forming a third insulating film on the entire surface of the resultant photoresist pattern formed; And anisotropically etching the entire surface of the third insulating film.

The third insulating film is formed of an LT-TEOS film.

The conductive layer is formed of a doped polysilicon layer.

The first insulating film is formed of a nitride film.

The present invention broadly forms the bit line contact pad layer and the capacitor contact pad layer without being bridged to each other. Therefore, the margin of the process of exposing the two pad layers can be widened, and the process becomes easy.

Hereinafter, a method of forming a pad layer in a manufacturing process of a semiconductor device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

14 to 20 are diagrams illustrating step-by-step methods of forming a pad layer in a manufacturing process of a semiconductor device according to an embodiment of the present invention.

FIG. 14 is a diagram illustrating a step of defining a bit line contact and a capacitor contact area. Specifically, the semiconductor substrate 80 is divided into active and inactive regions, and then a field oxide film (not shown) is applied to the non-active region. Form. Subsequently, a gate electrode 82 is formed in the active region so as to be spaced a predetermined distance apart, and a gate spacer 84 is formed on the side of the gate electrode 82. Subsequently, the gate space 84 is formed, and then a first insulating film 86 is formed on the entire surface of the semiconductor substrate 80 on which the gate electrode 82 and the gate spacer 84 are formed. The flattening is performed within a range where 82 is not revealed. The first insulating film 86 is formed of a nitride film. Next, a photosensitive film (not shown) is coated on the entire surface of the first insulating film 86 and then patterned to expose an interface of the first insulating film 86 corresponding to the active region between the gate electrodes 82. The pattern 88 is formed. Subsequently, the entire surface of the first insulating layer 86 is anisotropically etched using the photoresist pattern 88 as an etching mask. The anisotropic etching is performed until the active region of the semiconductor substrate 80 is exposed. The first insulating layer 86 is patterned by the anisotropic etching, leaving only the portion masked by the photoresist pattern 88, and the region not masked by the photoresist pattern 88 is completely removed, thereby the semiconductor substrate 80. To expose the active area. In this way, a bit line contact 89 and a capacitor contact 89a are formed in the first insulating layer 86. Thereafter, the photoresist pattern 88 is removed. As shown in FIG. 15, a first spacer (FIG. 16) is further formed on the entire surface of the resultant layer from which the photoresist layer pattern 88 is removed, to further secure the side protection of the gate electrode 82 as well as the side surface of the first insulating film pattern 86a. The second insulating film 90 is formed to form 92). Subsequently, the entire surface of the second insulating film 90 is anisotropically etched until the interface of the semiconductor substrate 80 is exposed. Due to the property of anisotropic etching, the second insulating film 90 is completely removed from the flat region of the second insulating film 90, and the first spacer (as shown in FIG. 16) is formed on the side surface of the first insulating film pattern 86a. 92 is formed. In this way, a bit line contact 89 and a capacitor contact 89a are formed between the gate electrodes 82.

FIG. 17 illustrates a step of applying the ARC 96. Specifically, the bit line contact 89 and the capacitor contact 89a are formed on the entire surface of the resultant product in which the bit line contact 89 and the capacitor contact 89a are formed. Filling conductive layer 94 is formed. Subsequently, ARC 96 is applied to the entire surface of the conductive layer 94. The conductive layer 94 is formed of a doped polysilicon layer.

FIG. 18 is a view illustrating a step of forming a third insulating film 100. Specifically, the photoresist film (not shown) is coated on the entire surface of the resultant material of FIG. 17 and then patterned to form at least the bit line contact 89. A photosensitive film pattern 98 is formed to cover the capacitor contact 89a. The third insulating film 100 is formed of an LT-TEOS film, and the LT-TOES film is formed by a chemical vapor deposition method.

19 is a view illustrating a step of forming the second spacer 102. Specifically, the entire surface of the third insulating layer 100 is anisotropically etched until the interface of the ARC 96 is exposed. As a result, a second spacer 102 is formed on the side surface of the photoresist pattern 98 due to the property of anisotropic etching.

FIG. 20 is a view illustrating a step of forming bit line contact and capacitor contact pad layers 106 and 108. Specifically, the photoresist pattern 98 and the second spacer 102 formed on the side surface thereof are etched. Anisotropically etch the entire surface of the resultant using The anisotropic etching is performed until the interface of the conductive layer 84 is exposed. The exposed portion of the ARC 100 is completely removed by the anisotropic etching. Subsequently, the entire surface of the resultant is anisotropically etched using an emitter having an etching selectivity with respect to the oxide film until the interface of the first insulating film pattern 86a is exposed. The anisotropic etching removes the conductive layer between the second spacers 102 of FIG. 19 formed on the side surface of the photosensitive film pattern 98 of FIG. 19 to expose the interface of the first insulating film pattern 86a. Subsequently, the resultant portion of which the interface of the first insulating layer pattern 85a is partially exposed is wet-etched to remove residual ACR formed between the second spacer 102 and the second spacer 102. In this way, the bit line contact pad layer 106 and the capacitor contact pad layer 108 are formed in the bit line contact 89 and the capacitor contact 89a. Each pad layer is formed to be in contact with the substrate and extend on the adjacent first insulating layer pattern 86a.

As described above, in the method for forming a pad layer in the semiconductor device manufacturing process according to the present invention, the second spacer is formed on the side surface of the photoresist pattern defining the pad layer region even though the dual pad layer is formed, and the second spacer is formed under the photoresist pattern using the etching mask. The width of the two pad layers formed by patterning the formed material layers may be about twice the width of the second spacer. In addition, since the first insulating film is covered on the gate electrode in the process of patterning the material film under the photosensitive film pattern, sufficient transient etching may be performed to prevent the bridge from being formed between the two pad layers. As a result, a dual pad layer having a wide width and no cross bridge is formed. This result can bring a wide process margin in the subsequent process of exposing the interface of the two pad layer, it is easy to bring the manufacturing process of the semiconductor device even at high integration speed.

The present invention is not limited to the above embodiments, and it is apparent that many modifications can be made by those skilled in the art within the technical spirit of the present invention.

Claims (8)

(a) dividing the entire surface of the semiconductor substrate into an active region and an inactive region; (b) forming a field oxide film on the inactive region; (c) forming a gate electrode in the active region; (d) forming a gate spacer on the side of the gate electrode; (e) forming a first insulating film pattern having a bit line contact and a capacitor contact between the gate electrode on the resultant product; (f) forming a first spacer on a side of the first insulating film pattern; (g) forming a conductive layer filling the bit line contact and the capacitor contact in front of the resultant; (h) applying an antireflection film to the entire surface of the conductive layer; (i) forming a photoresist pattern on the anti-reflection film that covers at least the bit line contacts and the capacitor contacts; (j) forming a second spacer on a side surface of the photoresist pattern; (k) etching the anti-reflection film by using the photoresist pattern and the second spacer as an etching mask; (l) anisotropically etching the entire surface of the resultant until the interface of the first insulating film pattern is exposed using an emitter having an excellent etching selectivity compared to an oxide film; And and (m) removing the second spacer and the anti-reflection film from the resultant. The method of claim 1, wherein step (e) (e1) forming a first insulating film on an entire surface of the resultant product in which the gate electrode and the gate spacer are formed; (e2) planarizing the entire surface of the first insulating film; (e3) forming a photoresist pattern on the planarized first insulating layer to cover the gate electrode and a gate spacer on a side thereof; and (e4) anisotropically etching the first insulating film until the interface of the substrate is exposed using the photoresist pattern as an etching mask. The method of claim 1, wherein step (f) Forming a second insulating film on an entire surface of the resultant product on which the first insulating film pattern is formed; And And anisotropically etching the entire surface of the second insulating film until the interface of the substrate is exposed. The method of claim 1, wherein the step (m) removes the second spacer and the anti-reflection film from the resultant using a wet etching method. The method of claim 1, wherein step (j) (j1) forming a third insulating film on the entire surface of the resultant photosensitive film pattern; And (j2) anisotropically etching the entire surface of the third insulating film. 6. The method of claim 5, wherein the third insulating film is formed of an LT-TEOS film. The method of claim 1, wherein the conductive layer is formed of a doped polysilicon layer. The method of claim 1 or 2, wherein the first insulating film is formed of a nitride film.