KR102669030B1 - A packaging method for semiconductor components - Google Patents
A packaging method for semiconductor components Download PDFInfo
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- KR102669030B1 KR102669030B1 KR1020190161688A KR20190161688A KR102669030B1 KR 102669030 B1 KR102669030 B1 KR 102669030B1 KR 1020190161688 A KR1020190161688 A KR 1020190161688A KR 20190161688 A KR20190161688 A KR 20190161688A KR 102669030 B1 KR102669030 B1 KR 102669030B1
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- 238000000034 method Methods 0.000 title claims abstract description 46
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 16
- 229920006336 epoxy molding compound Polymers 0.000 claims abstract description 34
- 239000000463 material Substances 0.000 claims abstract description 34
- 238000000576 coating method Methods 0.000 claims abstract description 17
- 239000011248 coating agent Substances 0.000 claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims abstract description 9
- 239000002184 metal Substances 0.000 claims abstract description 9
- 239000007769 metal material Substances 0.000 claims abstract description 9
- 238000007772 electroless plating Methods 0.000 claims abstract description 4
- 238000009713 electroplating Methods 0.000 claims abstract description 4
- 238000003698 laser cutting Methods 0.000 claims abstract description 4
- 238000000206 photolithography Methods 0.000 claims abstract description 4
- 238000001020 plasma etching Methods 0.000 claims abstract description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000011230 binding agent Substances 0.000 claims description 4
- 239000002952 polymeric resin Substances 0.000 claims description 4
- 229920003002 synthetic resin Polymers 0.000 claims description 4
- 238000007598 dipping method Methods 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims description 2
- 239000010419 fine particle Substances 0.000 claims description 2
- 238000005507 spraying Methods 0.000 claims description 2
- 239000003795 chemical substances by application Substances 0.000 claims 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 239000011800 void material Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 208000032368 Device malfunction Diseases 0.000 description 1
- 229910001111 Fine metal Inorganic materials 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009429 electrical wiring Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000002923 metal particle Substances 0.000 description 1
- 239000013528 metallic particle Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Toxicology (AREA)
- Electromagnetism (AREA)
- Health & Medical Sciences (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
본 발명은 반도체 소자의 페키징 방법에 관한 것으로, 더욱 상세하게는 전자부품이 실장된 인쇄회로기판을 준비하는 단계(S10); 준비된 인쇄회로기판의 상면으로 EMC(epoxy molding compound)를 일정 두께로 도포하는 EMC 도포단계(S20); EMC가 도포된 인쇄회로기판의 각 부품 사이를 레이저컷팅, 포토리소그래피, 반응성 이온식각, 나노 임프린트 중 하나의 방법을 이용하여 도통홀(Via hole)을 형성시키는 도통홀(Via hole) 형성단계(S30); 전자파 차폐기능이 있는 도전성이 높은 금속재로 이루어진 전자파 차폐재를 무전해 도금이나 전해 도금을 이용하여 EMC 상부면과 수평이 되도록 도통홀(Via hole)을 충진시키는 전자파 차폐재 도통홀(Via hole) 충진단계(S40); EMC 표면과 도통홀(Via hole) 표면 위로 전자파 차폐기능이 있는 도전성이 높은 금속재로 이루어진 전자파 차폐재를 이용하여 균일한 두께가 유지되도록 일정 두께로 코팅하는 전자파 차폐재 코팅단계(S50);를 포함하여 이루어진다.The present invention relates to a packaging method for semiconductor devices, and more specifically, to the step of preparing a printed circuit board on which electronic components are mounted (S10); An EMC application step (S20) of applying EMC (epoxy molding compound) to a certain thickness on the upper surface of the prepared printed circuit board; Via hole forming step (S30) of forming a via hole between each component of the EMC-coated printed circuit board using one of the following methods: laser cutting, photolithography, reactive ion etching, or nano imprinting. ); Electromagnetic wave shielding material via hole filling step (via hole filling) made of highly conductive metal with electromagnetic wave shielding function using electroless plating or electrolytic plating to ensure that the via hole is level with the upper surface of the EMC S40); It includes an electromagnetic wave shielding material coating step (S50) of coating the EMC surface and the via hole surface to a certain thickness to maintain a uniform thickness using an electromagnetic wave shielding material made of a highly conductive metal material with an electromagnetic wave shielding function. .
Description
본 발명은 반도체 소자의 페키징 방법에 관한 것으로, 더욱 상세하게는 조립된 반도체 칩 및 기타 소자 등에서 발생되는 유해 전자파를 차단하여 제품의 신뢰성을 향상시키면서 오작동을 방지할 수 있도록 하는 반도체 소자의 패키징 방법에 관한 것이다.The present invention relates to a packaging method for semiconductor devices, and more specifically, to a packaging method for semiconductor devices that improves product reliability and prevents malfunctions by blocking harmful electromagnetic waves generated from assembled semiconductor chips and other devices. It's about.
전자 디바이스는 소형화, 경량화, 초박형화, 고집적화, 고기능화 추세에 따라 각 디바이스 간 거리가 가까워짐에 따라 디바이스 상호간 전자파 간섭에 따른 기기의 오동작과 고장, 신뢰성 저하 및 인체에 대한 유해성 문제가 대두되고 있다.As electronic devices become smaller, lighter, ultra-thinner, more integrated, and more functional, and the distance between each device gets closer, problems such as device malfunction and failure due to electromagnetic interference between devices, reliability decline, and hazards to the human body are emerging.
일례로 스마트폰과 같은 휴대형 통신단말에서 전자부품의 전자파를 차폐하는 방법으로, (ⅰ) 각 부품 개별적으로 반도체 칩 등 주요 부품을 금속 캔의 씌우거나(그림 1참조), (ⅱ) 스퍼터링으로 전도성이 높은 Cu, Ag, Al 등의 금속을 코팅하여 유해 전자파를 반사 또는 흡수하여 차폐하는 방법(그림 2 참조)을 이용하고 있다.For example, a method of shielding electromagnetic waves from electronic components in portable communication terminals such as smartphones is (i) individually covering major components such as semiconductor chips with metal cans (see Figure 1), or (ii) making them conductive by sputtering. This method is used to reflect or absorb harmful electromagnetic waves and shield them by coating them with metals such as Cu, Ag, and Al (see Figure 2).
(그림 1)(Figure 1)
(그림 2)(Figure 2)
상술한 금속 캔을 씌우는 경우, 여분의 공간 점유로 박형화에 한계가 있고, 전도성 금속의 스퍼터링에 의한 코팅의 경우 고가의 진공 설비가 필요하고 공정시간이 매우 길어 생산단가가 높아지며, 스퍼터된 금속 원자의 직진성으로 인하여 부품의 상부면에 비하여 측면의 코팅 두께가 얇아 전자파가 횡방향으로 누설되어 디바이스 간의 전자파 차폐 효과가 불충분하다는 문제점이 있었다.In the case of covering the above-mentioned metal can, there is a limit to thinning due to the occupation of extra space, and in the case of coating by sputtering of conductive metal, expensive vacuum equipment is required, the process time is very long, which increases the production cost, and the sputtered metal atoms are Due to the straight-line nature, the coating thickness on the side of the component was thinner than the upper surface of the component, causing electromagnetic waves to leak laterally, resulting in insufficient electromagnetic wave shielding between devices.
본 발명은 인쇄회로기판(PCB) 등의 기판 위에 반도체 칩 등 각종 전자제품 일체가 탑재된 상태에서 기판 또는 모듈 레벨에서 각 부품 간 전자파 간섭을 차단할 수 있는 수단을 제공함으로써 부품의 측면 방향으로 방출되는 전자파를 효과적으로 차폐하고 부품의 패키징 공정에 있어서 생산성을 높일 수 있도록 하는 반도체 소자의 패키징 방법을 제공하고자 하는데 그 목적이 있다.The present invention provides a means to block electromagnetic interference between each component at the substrate or module level when various electronic products such as semiconductor chips are mounted on a substrate such as a printed circuit board (PCB), thereby preventing electromagnetic interference emitted toward the side of the component. The purpose is to provide a packaging method for semiconductor devices that effectively shields electromagnetic waves and increases productivity in the component packaging process.
상술한 목적을 달성하기 위해 본 발명에 따른 반도체 소자의 패키징 방법은 전자부품이 실장된 인쇄회로기판을 준비하는 단계; 준비된 인쇄회로기판의 상면으로 EMC(epoxy molding compound)를 일정 두께로 도포하는 EMC 도포단계; EMC가 도포된 인쇄회로기판의 각 부품 사이를 레이저컷팅, 포토리소그래피, 반응성 이온식각, 나노 임프린트 중 하나의 방법을 이용하여 도통홀(Via hole)을 형성시키는 도통홀(Via hole) 형성단계; 전자파 차폐기능이 있는 도전성이 높은 금속재로 이루어진 전자파 차폐재를 무전해 도금이나 전해 도금을 이용하여 EMC 상부면과 수평이 되도록 도통홀(Via hole)을 충진시키는 전자파 차폐재 도통홀(Via hole) 충진단계; EMC 표면과 충진된 도통홀(Via hole) 표면 위로 전자파 차폐기능이 있는 도전성이 높은 금속재로 이루어진 전자파 차폐재를 이용하여 균일한 두께가 유지되도록 일정 두께로 코팅하는 전자파 차폐재 코팅단계;를 포함하여 이루어진다.In order to achieve the above-described object, the packaging method of a semiconductor device according to the present invention includes preparing a printed circuit board on which electronic components are mounted; An EMC application step of applying EMC (epoxy molding compound) to a certain thickness on the upper surface of the prepared printed circuit board; A via hole forming step of forming a via hole between each component of the EMC-coated printed circuit board using one of the following methods: laser cutting, photolithography, reactive ion etching, or nano imprinting; An electromagnetic wave shielding material via hole filling step of filling the electromagnetic wave shielding material made of a highly conductive metal material with an electromagnetic wave shielding function using electroless plating or electrolytic plating so that the via hole is level with the EMC upper surface; It includes an electromagnetic wave shielding material coating step of coating the EMC surface and the filled via hole surface to a certain thickness to maintain a uniform thickness using an electromagnetic wave shielding material made of a highly conductive metal material with an electromagnetic wave shielding function.
특히, 상기 도통홀(Via hole)에 충진되는 전자파 차폐재 및 EMC 표면과 충진된 도통홀(Via hole) 표면 위로 코팅되는 전자파 차폐재는 Cu, Ag, Al 중 어느 하나로 구성되고, 상기 전자파 차폐재 코팅단계에 이용되는 전자파 차폐재는 미세한 금속입자가 고분자 수지바인더 물질에 균일하게 분산된 용액을 이용하고, 상기 용액을 스프레이, 디스펜싱, 딥핑 중 어느 하나의 방법으로 도포한 후 건조시키는 공정을 포함하여 이루어진다.In particular, the electromagnetic wave shielding material and EMC surface filled in the via hole and the electromagnetic wave shielding material coated on the surface of the filled via hole are composed of any one of Cu, Ag, and Al, and are used in the electromagnetic wave shielding material coating step. The electromagnetic wave shielding material used uses a solution in which fine metal particles are uniformly dispersed in a polymer resin binder material, and includes the process of applying the solution by any of spraying, dispensing, or dipping methods and then drying it.
본 발명에 따른 반도체소자의 패키징 방법을 이용할 경우 인쇄회로기판에 실장된 반도체 칩 등 전자부품의 측면으로부터 방사되는 전자파를 효과적으로 차단하여 각 디바이스간 전자파 내부 간섭을 방지할 수 있고, 기존의 부품 레벨의 전자차 차폐가 아닌 기판(모듈) 레벨의 전자파 차폐에 의한 제품의 신뢰성 향상과 오동작을 방지할 수 있도록 한다.When using the packaging method for semiconductor devices according to the present invention, it is possible to effectively block electromagnetic waves radiating from the side of electronic components such as semiconductor chips mounted on a printed circuit board, thereby preventing internal electromagnetic interference between each device, and preventing internal interference of electromagnetic waves between devices at the existing component level. It improves product reliability and prevents malfunctions due to electromagnetic wave shielding at the board (module) level rather than electronic vehicle shielding.
도 1은 본 발명에 따른 반도체 소자의 패키징 방법을 도시한 공정상태도,
도 2는 본 발명에 따른 반도체 소자의 패키징 방법의 공정을 도시한 플로우차트,
도 3은 본 발명에 따른 반도체 소자의 패키징 방법을 이용한 경우의 반도체 부품의 전자파 차폐효과를 개략적으로 도시한 예시도이다.1 is a process diagram showing a packaging method for a semiconductor device according to the present invention;
2 is a flow chart showing the process of the semiconductor device packaging method according to the present invention;
Figure 3 is an example diagram schematically showing the electromagnetic wave shielding effect of semiconductor components when using the semiconductor device packaging method according to the present invention.
본 발명에 따른 반도체 소자의 패키징 방법은 반도체 칩 등 전자부품에서 발생되는 유해한 전자파가 다른 전자부품에 영향을 미치는 것을 차단하여 부품 및 제품의 신뢰성을 향상시키기 위한 것으로, 이를 위해 전자부품이 실장된 인쇄회로기판의 표면에 전자부품의 오염이나 손상을 방지하기 위한 EMC코팅공정과, EMC코팅이 이루어진 각 부품 사이에 도통홀(Via hole)을 형성하는 공정과, 도통홀 내측으로 도전성 금속재로 이루어지는 전자파 차폐재를 충진하는 공정과, EMC코팅 표면과 전자파 차폐재가 코팅된 표면 및 주변으로 도전성 금속재로 이루어진 전자파 차폐재를 추가로 코팅하는 공정으로 이루어진다.The packaging method for semiconductor devices according to the present invention is intended to improve the reliability of components and products by blocking harmful electromagnetic waves generated from electronic components such as semiconductor chips from affecting other electronic components. For this purpose, printing with mounted electronic components is performed. An EMC coating process to prevent contamination or damage to electronic components on the surface of the circuit board, a process to form a conductive hole (via hole) between each EMC-coated component, and an electromagnetic wave shielding material made of a conductive metal material inside the conductive hole. It consists of a process of filling, and a process of additionally coating an electromagnetic wave shielding material made of a conductive metal material on the EMC coating surface, the surface coated with the electromagnetic wave shielding material, and the surrounding area.
명세서에 첨부된 도면을 참고하면서 본 발명에 따른 반도체 소자의 패키징 방법에 대해 더욱 상세하게 설명한다.The packaging method of a semiconductor device according to the present invention will be described in more detail with reference to the drawings attached to the specification.
도 1은 본 발명에 따라 전자부품이 실장된 인쇄회로기판 상면에 반도체 소자의 패키징을 수행하는 과정을 개략적으로 도시한 모식도이고, 도 2는 본 발명에 따른 반도체 소자의 패키징 방법을 간략한 플로우차트로 도시하고 있다.Figure 1 is a schematic diagram schematically showing the process of packaging a semiconductor device on the upper surface of a printed circuit board on which electronic components are mounted according to the present invention, and Figure 2 is a brief flow chart of the packaging method of a semiconductor device according to the present invention. It is showing.
도면에 도시된 실시예는 전자부품 등이 실장된 인쇄회로기판의 일부를 개략적으로 도시하고 있는 것으로, 본 발명은 인쇄회로기판에 자수의 전자부품이 실장된 상태에서 전자파 차폐를 위한 패키징 공정이 수행된다.The embodiment shown in the drawing schematically shows a portion of a printed circuit board on which electronic components are mounted. In the present invention, a packaging process for electromagnetic wave shielding is performed with embroidered electronic components mounted on a printed circuit board. do.
인쇄회로기판에 실장되는 다수의 전자부품들은 표면실장기술(SMT)을 이용하여 장착되며, 이때 각 전자부품들은 기판 표면의 전기배선을 위한 Cu배선 등과 Au 와이어로 본딩하여 연결된다.Many electronic components mounted on a printed circuit board are mounted using surface mount technology (SMT), and each electronic component is connected by bonding with Au wire, such as Cu wiring for electrical wiring on the surface of the board.
물론, 전자부품들을 실장하는 방법은 와이어본딩 기법 이외에도 solder bump 등을 이용한 flip chip bonding 방법 등으로 전자부품과 기판 사이를 전기적으로 연결할 수 있다.Of course, in addition to the wire bonding technique, electronic components can be mounted using a flip chip bonding method using solder bumps, etc. to electrically connect the electronic components to the board.
이와 같이 각종 전자부품이 실장된 인쇄회로기판을 준비(S10)한 후에, 반도체 칩을 비롯한 각 전자부품의 오염방지, 물리적 손상이 화학적 손상(부식, 산화)으로부터 보호하기 위해 EMC(epoxy molding compound)를 사용하여 전체 전자부품을 감싸 밀봉하는 EMC 도포공정(S20)을 수행한다.After preparing the printed circuit board on which various electronic components are mounted (S10), EMC (epoxy molding compound) is applied to prevent contamination of each electronic component, including the semiconductor chip, and to protect physical damage from chemical damage (corrosion, oxidation). Perform the EMC application process (S20) to enclose and seal the entire electronic component using .
EMC 도포공정(S20) 수행 후 도포된 EMC 성분이 경화된 후에 각 전자부품 사이에 미리 정해진 패턴을 따라 도통홀(Via hole)을 형성(S30)시킨다.After the EMC application process (S20) is performed and the applied EMC component is cured, a conductive hole (Via hole) is formed between each electronic component according to a predetermined pattern (S30).
상기 도통홀(Via hole)을 형성(S30)시키는 공정은 레이저 컷팅(laser cutting), 포토리소그래피 및 건식식각(반응성 이온식각, reactive ion ething), 나노 임프린트 중 어느 하나의 방법을 사용하여 도통홀(via hole)을 형성시킨다.The process of forming the via hole (S30) is to create a via hole (S30) using any one of the following methods: laser cutting, photolithography, dry etching (reactive ion etching), and nano imprinting. forms a via hole.
상기 도통홀(Via hole) 형성공정(S30)을 통해 각 전자부품 사이에 형성된 도통홀 내측으로 Cu, Al, Ag등의 도전성이 높은 금속으로 이루어지는 전자파 차폐재를 충진시키는 공정(S40)을 수행한다.A process (S40) is performed to fill the inside of the conduction hole formed between each electronic component through the conduction hole (Via hole) forming process (S30) with an electromagnetic wave shielding material made of a highly conductive metal such as Cu, Al, or Ag.
상기 도통홀 내측으로 전자파 차폐재를 충진시키는 공정은 무전해 도금이나 전해 도금을 이용하여 충진시킬 수 있으며, 충진되는 높이는 EMC가 도포된 표면과 수평상태가 유지되는 정도로 충진을 시키되, 충진속도가 빠르고 하방에서부터 상방으로 결정이 일어날때 공극(void)이 형성되지 않는 방법을 이용하는 것이 바람직하다.The process of filling the inside of the conduction hole with an electromagnetic wave shielding material can be done using electroless plating or electrolytic plating. The filling height is such that it is maintained in a horizontal state with the surface to which the EMC is applied, but the filling speed is fast and the filling is directed downward. It is desirable to use a method that does not form voids when crystals occur upward from the top.
도통홀에 전자파 차폐재를 충진시킨 후 마지막 공정으로 EMC표면과 도통홀 상면에 전체적으로 전자파 차폐재를 코팅하는 전자파 차폐 코팅공정(S50)을 수행하게 된다.After filling the conductive hole with electromagnetic wave shielding material, the final process is an electromagnetic wave shielding coating process (S50), which coats the entire EMC surface and the top surface of the conductive hole with electromagnetic wave shielding material.
상기 전자파 차폐 공정에 이용되는 전자파 차폐재는 도전성이 높은 Cu, Ag, Al 등의 미세입자가 고분자 수지 바인더 물질에 균일하게 분산된 용액을 이용하게 되며, 이러한 금속성 입자가 첨가된 고분자수지 바인더 용액을 스프레이, 디스펜싱, 딥핑 등의 방법으로 도포하게 되며, 도포 후 건조시키는 과정이 이루어진다.The electromagnetic wave shielding material used in the electromagnetic wave shielding process uses a solution in which fine particles such as highly conductive Cu, Ag, and Al are uniformly dispersed in a polymer resin binder material, and the polymer resin binder solution to which these metallic particles are added is sprayed. It is applied by methods such as dispensing and dipping, and a drying process is performed after application.
상기 전자파 차폐재의 코팅공정 중 EMC 코팅면의 윗면을 평탄하게 유지되도록 CMP(chemical mechanical polishing, 화학기계적 연마)공정을 추가하여 수행할 수 있으며, 상기 CMP공정은 고밀도 반도체 공정에서 사용되는 웨이퍼 표면 평탄화기술로 업게에서 널리 사용되고 있어 이에 대한 설명은 생략한다.During the coating process of the electromagnetic wave shielding material, a CMP (chemical mechanical polishing) process can be added to keep the upper surface of the EMC coating surface flat. The CMP process is a wafer surface flattening technology used in high-density semiconductor processes. Since it is widely used in the industry, its description will be omitted.
이와 같이, 본 발명은 인쇄회로기판 상면에 실장되는 각종 전자부품들에 대해서 전체적으로 EMC도포를 수행하고, 각 전자부품 간에 식각작업을 통해 도통홀을 형성시킨 후 형성된 도통홀 내부에 도전성 금속재로 이루어진 전자파 차폐재를 충진시킨 다음, EMC 표면과 도통홀 상면을 전체적으로 도전성 금속재로 이루어지는 전자파 차폐재를 일정 두께로 코팅하는 공정을 통해 인쇄회로기판에 실장되는 모든 전자부품에 대해 패키징이 이루어지게 된다.In this way, the present invention performs EMC application as a whole on various electronic components mounted on the upper surface of a printed circuit board, forms conductive holes between each electronic component through an etching process, and then transmits electromagnetic waves made of a conductive metal material inside the formed conductive hole. After filling the shielding material, packaging is performed for all electronic components mounted on the printed circuit board through a process of coating the EMC surface and the upper surface of the conduction hole with an electromagnetic wave shielding material made of a conductive metal material to a certain thickness.
이와 같은 공정으로 패키징이 이루어진 인쇄회로기판의 일부 개략도 도 3에 도시되어 있다.A partial schematic diagram of a printed circuit board packaged through this process is shown in Figure 3.
도 3에 도시된 바와 같이, 인쇄회로기판에 실장된 전자부품에서는 동작과 함께 전자파가 발생되는데, 이때 전자부품에서 발생되어 주변으로 빠져나가는 전자파중 측방으로 나가는 전자파는 각 전자부품 사이의 도통홀에 충진도니 전자파 차폐재에 의해 흡수되어 다른 전자부품에 영향을 미치지 않게 되고, 상부로 빠져나가는 전자파 역시 상면에 코팅된 전자파 차폐재에 흡수되어 다른 전자부품에 영향을 미치지 못하게 된다.As shown in Figure 3, electronic components mounted on a printed circuit board generate electromagnetic waves as they operate. At this time, among the electromagnetic waves generated from the electronic components and passing out to the surroundings, the electromagnetic waves that exit laterally are connected to the conduction hole between each electronic component. As it is filled, it is absorbed by the electromagnetic wave shielding material and does not affect other electronic components, and the electromagnetic waves that escape through the top are also absorbed by the electromagnetic wave shielding material coated on the top and do not affect other electronic components.
물론, 다른 전자부품에서 발생되는 전자파 역시 도통홀에 충진된 전자파 차폐재 및 상면에 코팅된 전자파 차폐재에 의해 흡수 또는 반사되어 다른 전자부품에 영향을 미칠 수가 없게 됨으로써 각 전자부품의 동작이 원활하게 이루어질 수 있도록 하고, 전자부품의 성능 및 품질이 유지되어 제품의 신뢰성을 높일 수 있도록 한다.Of course, electromagnetic waves generated from other electronic components are also absorbed or reflected by the electromagnetic wave shielding material filled in the conduction hole and the electromagnetic wave shielding material coated on the top, so they cannot affect other electronic components, so that each electronic component can operate smoothly. Ensure that the performance and quality of electronic components are maintained to increase product reliability.
10 : 인쇄회로기판 12 : 전자부품
14 : 금속와이어
20 : EMC 25 : 도통홀(Via hole)
30,40 : 전자파 차폐재10: printed circuit board 12: electronic components
14: metal wire
20: EMC 25: Via hole
30,40: Electromagnetic wave shielding material
Claims (2)
상기 준비된 인쇄회로기판의 상면으로 EMC(epoxy molding compound)를 일정 두께로 도포하는 EMC 도포단계;
상기 EMC가 도포된 인쇄회로기판의 각 전자부품 사이를 레이저컷팅, 포토리소그래피, 반응성 이온식각, 나노 임프린트 중 어느 하나의 방법을 이용하여 도통홀(Via hole)을 형성시키는 도통홀(Via hole) 형성단계;
무전해 도금이나 전해 도금을 이용하여 전자파 차폐기능을 가지는 금속재로 이루어진 전자파 차폐재를 EMC 상부면과 수평이 되도록 도통홀(Via hole)을 충진시키되, 하방에서부터 상방으로 결정이 일어날 때 공극(void)이 형성되지 않도록 하는 전자파 차폐재 도통홀(Via hole) 충진단계;
상기 EMC의 표면과 상기 충진된 도통홀(Via hole) 표면 위로 전자파 차폐기능을 가지는 금속재로 이루어진 전자파 차폐재를 코팅하고, 상기 코팅된 면을 평탄화하는 전자파 차폐재 코팅단계;를 포함하고,
상기 도통홀에 충진되는 전자파 차폐제는,
Cu 또는 Al 인 도전성 금속이고,
상기 EMC의 표면과 상기 도통홀 표면 위로 코팅되는 전자파 차폐제는,
Cu 또는 Al 인 미세입자가 포함된 고분자 수지 바인더 물질에 균일하게 분산된 용액이며,
상기 용액은,
스프레이, 디스펜싱, 딥핑 중 어느 하나의 방식으로 코딩되고, 건조되는 것을 특징으로 하는 반도체 소자의 패키징 방법.Preparing a printed circuit board on which electronic components are mounted;
An EMC application step of applying EMC (epoxy molding compound) to a certain thickness on the upper surface of the prepared printed circuit board;
Formation of a via hole between each electronic component of the EMC-coated printed circuit board using any one of the following methods: laser cutting, photolithography, reactive ion etching, or nano imprinting. step;
Using electroless plating or electrolytic plating, fill the via hole with an electromagnetic wave shielding material made of a metal material with an electromagnetic wave shielding function so that it is level with the upper surface of the EMC, but when crystals occur from the bottom to the top, a void is formed. A step of filling conductive holes (via holes) with electromagnetic wave shielding material to prevent them from being formed;
An electromagnetic wave shielding material coating step of coating an electromagnetic wave shielding material made of a metal material with an electromagnetic wave shielding function on the surface of the EMC and the surface of the filled via hole, and flattening the coated surface,
The electromagnetic wave shielding agent filled in the conduction hole is,
It is a conductive metal that is Cu or Al,
The electromagnetic wave shielding agent coated on the surface of the EMC and the surface of the conduction hole is,
It is a solution uniformly dispersed in a polymer resin binder material containing fine particles of Cu or Al.
The solution is,
A packaging method for a semiconductor device characterized in that the semiconductor device is coded and dried using any one of spraying, dispensing, and dipping.
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