KR102461572B1 - Thin film trnasistor, method for manufacturing the same and display device comprising the same - Google Patents

Abstract

An embodiment of the present invention provides a gate electrode on a substrate, a gate insulating film on the gate electrode, an oxide semiconductor layer on the gate insulating film that at least partially overlaps the gate electrode, a source electrode connected to the oxide semiconductor layer, and the source electrode and and a drain electrode spaced apart and connected to the oxide semiconductor layer, wherein the oxide semiconductor layer includes: a first oxide semiconductor layer on the gate insulating layer; and a second oxide semiconductor layer on the first oxide semiconductor layer, wherein the first oxide semiconductor layer has a first surface in a direction opposite to the gate electrode and a first surface in a direction toward the gate electrode, wherein the second oxide semiconductor layer The layer has a nitrogen concentration higher than that of the first oxide semiconductor layer, and the second oxide semiconductor layer has a surface resistance of 10 ² to 10 ⁶ times that of the first oxide semiconductor layer.

Description

Thin film transistor, manufacturing method thereof, and display device including same

The present invention relates to a thin film transistor, a method for manufacturing the thin film transistor, and a display device including the thin film transistor.

A transistor is widely used as a switching device or a driving device in the field of electronic devices. In particular, since a thin film transistor can be manufactured on a glass substrate or a plastic substrate, it is used as a switching element of a display device such as a liquid crystal display device or an organic light emitting device. It is widely used.

The thin film transistor, based on the material constituting the active layer, is an amorphous silicon thin film transistor in which amorphous silicon is used as an active layer, a polycrystalline silicon thin film transistor in which polycrystalline silicon is used as an active layer, and an oxide semiconductor as an active layer. It may be classified as an oxide semiconductor thin film transistor.

Among these, oxide semiconductor TFTs can form oxides constituting the active layer at a relatively low temperature, have high mobility, and have a large resistance change according to the oxygen content. , has the advantage that desired physical properties can be easily obtained, and its use has been expanded recently. In addition, since the oxide semiconductor is transparent due to the characteristics of the oxide, it is advantageous for realizing a transparent display. However, due to the characteristics of the oxide, the oxide semiconductor layer may be damaged during a process such as etching or patterning, and defects may occur in the oxide semiconductor layer. Therefore, it is necessary to protect the oxide semiconductor layer during the patterning process.

An embodiment of the present invention is to provide a thin film transistor having a protective layer containing nitrogen.

Another embodiment of the present invention is to provide a thin film transistor that can have excellent reliability even when the passivation layer containing nitrogen protects the channel layer and is patterned in a BCE (Back Channel Etch) structure.

Another embodiment of the present invention is to provide a method of manufacturing a thin film transistor having a protective layer containing nitrogen.

Another embodiment of the present invention is to provide a display device including such a thin film transistor.

An embodiment of the present invention for achieving the above technical problem, a gate electrode on a substrate, a gate insulating film on the gate electrode, at least partially overlapping the gate electrode, an oxide semiconductor layer on the gate insulating film, the oxide semiconductor layer and a source electrode connected to the source electrode and a drain electrode spaced apart from the source electrode and connected to the oxide semiconductor layer, wherein the oxide semiconductor layer includes: a first oxide semiconductor layer on the gate insulating layer; and a second oxide semiconductor layer on the first oxide semiconductor layer, wherein the first oxide semiconductor layer has a first surface in a direction opposite to the gate electrode and a first surface in a direction toward the gate electrode, wherein the second oxide semiconductor layer The layer has a nitrogen concentration higher than that of the first oxide semiconductor layer, and the second oxide semiconductor layer has a surface resistance of 10 ² to 10 ⁶ times that of the first oxide semiconductor layer.

The nitrogen is uniformly distributed in the second oxide semiconductor layer.

The concentration of nitrogen (N) in the second oxide semiconductor layer is 3 to 10 atomic% (at%) based on the number of atoms.

The first oxide semiconductor layer has a mobility of 50 to 5000 times that of the second oxide semiconductor layer.

The second oxide semiconductor layer has a thickness of 3 nm or more.

The second oxide semiconductor layer covers a region of the first surface of the first oxide semiconductor layer that does not overlap the source electrode and the drain electrode.

At least a portion of the first surface of the first oxide semiconductor layer is in contact with the source electrode, and another portion of the first surface of the first oxide semiconductor layer is in contact with the drain electrode.

Another embodiment of the present invention includes forming a gate electrode on a substrate, forming a gate insulating film on the gate electrode, and on the gate insulating film, a first oxide semiconductor layer and a second oxide semiconductor layer and forming an oxide semiconductor layer, each of which is connected to the oxide semiconductor layer, and forming a source electrode and a drain electrode spaced apart from each other, wherein the forming of the oxide semiconductor layer is performed under an oxygen gas-containing atmosphere in a chamber. forming a first oxide semiconductor material layer on the gate insulating film by sputtering deposition; forming a second oxide semiconductor material layer on the first oxide semiconductor material layer in an atmosphere containing oxygen gas and nitrogen gas in a chamber; and patterning the first oxide semiconductor material layer and the second oxide semiconductor material layer to form the first oxide semiconductor layer and the second oxide semiconductor layer, wherein the second oxide semiconductor layer comprises the first Provided is a method of manufacturing a thin film transistor having a surface resistance of 10 ² to 10 ⁶ times that of an oxide semiconductor layer.

In the forming of the second oxide semiconductor material layer, the nitrogen has a flow rate of 0.1 to 50% relative to the oxygen.

The second oxide semiconductor layer includes nitrogen (N) in a concentration of 3 to 10 atomic% (at%) based on the number of atoms.

The second oxide semiconductor layer has a thickness of 3 nm or more.

The first oxide semiconductor layer has a first surface in a direction opposite to the gate electrode and a second surface in the direction of the gate electrode, and in the forming of the oxide semiconductor layer, at least a portion of the first surface is formed in the second oxide semiconductor The second oxide semiconductor layer is patterned to be exposed from the layer.

Another embodiment of the present invention provides a display device including a substrate, the above-described thin film transistor on the substrate, and a first electrode connected to the thin film transistor.

According to an embodiment of the present invention, a thin film transistor having electrical characteristics suitable for each application state can be manufactured by adjusting the concentration of nitrogen during the manufacturing process. According to an embodiment of the present invention, since the second oxide semiconductor layer serving as a protective layer including nitrogen protects the first oxide semiconductor layer serving as a channel layer in the etching or patterning process, BCE ( A thin film transistor with a back channel etch) structure can be made.

Since the thin film transistor according to an embodiment of the present invention has excellent thermal stability, excellent reliability can be maintained even in a high-temperature process applied during a manufacturing process of a display device. Accordingly, a display device including such a thin film transistor may have excellent reliability and display characteristics.

In addition to the above-mentioned effects, other features and advantages of the present invention will be described below or will be clearly understood by those skilled in the art from such description and description.

1 is a cross-sectional view of a thin film transistor according to an embodiment of the present invention.
2 is a cross-sectional view of a thin film transistor according to another embodiment of the present invention.
3A to 3H are flowcharts of a manufacturing process of a thin film transistor according to another exemplary embodiment of the present invention.
4 is a schematic diagram illustrating sputtering deposition for forming a first oxide semiconductor layer.
5 is a schematic diagram illustrating sputtering deposition for forming a second oxide semiconductor layer.
6 is a schematic cross-sectional view of a display device according to still another exemplary embodiment of the present invention.
7 is a schematic cross-sectional view of a display device according to another exemplary embodiment of the present invention.
8A to 8D are the threshold voltage (Vth) measurement results for the thin film transistor.
9 is an X-ray photoelectron spectroscopic analysis graph for an oxide semiconductor layer.
10A and 10B are graphs of current change measurement of an oxide semiconductor layer, respectively.
11A and 11B are schematic diagrams illustrating a bonding state of nitrogen in the second oxide semiconductor layer.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention belongs It is provided to inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims.

Since the shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are exemplary, the present invention is not limited to the matters shown in the drawings. Like elements may be referred to by the same reference numerals throughout the specification. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless the expression 'only' is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise.

In interpreting the components, it is interpreted as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., 'right' Alternatively, unless the expression 'directly' is used, one or more other parts may be positioned between the two parts.

The spatially relative terms "below, beneath", "lower", "above", "upper", etc. are one element or component as shown in the drawings. and can be used to easily describe the correlation with other devices or components. Spatially relative terms should be understood as terms including different directions of the device during use or operation in addition to the directions shown in the drawings. For example, when an element shown in the figures is turned over, an element described as "beneath" or "beneath" another element may be placed "above" the other element. Accordingly, the exemplary term “below” may include both directions below and above. Likewise, the exemplary terms “above” or “on” may include both directions above and below.

In the case of a description of a temporal relationship, for example, 'immediately' or 'directly' when a temporal relationship is described as 'after', 'following', 'after', 'before', etc. It may include cases that are not continuous unless the expression "

Although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present invention.

The term “at least one” should be understood to include all possible combinations from one or more related items. For example, the meaning of "at least one of the first, second, and third items" means 2 of the first, second, and third items as well as each of the first, second, or third items. It may mean a combination of all items that can be presented from more than one.

Each feature of the various embodiments of the present invention may be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each of the embodiments may be implemented independently of each other or may be implemented together in a related relationship. may be

Hereinafter, a thin film transistor, a method of manufacturing the same, and a display device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. In adding reference numerals to components in each drawing, the same components may have the same reference numerals as much as possible even if they are indicated in different drawings.

1 is a cross-sectional view of a thin film transistor 100 according to an embodiment of the present invention.

The thin film transistor 100 according to an embodiment of the present invention includes a gate electrode 140 on a substrate 110 , a gate insulating film 120 on the gate electrode 140 , an oxide semiconductor layer 130 on the gate insulating film 120 , It includes a source electrode 150 connected to the oxide semiconductor layer 130 , and a drain electrode 160 spaced apart from the source electrode 150 and connected to the oxide semiconductor layer 130 . Here, the oxide semiconductor layer 130 at least partially overlaps the gate electrode 140 .

Glass or plastic may be used as the substrate 110 . As the plastic, a transparent plastic having flexible properties, for example, polyimide may be used. When polyimide is used as the substrate 110 , when a high-temperature deposition process is performed on the substrate 110 , a heat-resistant polyimide capable of withstanding a high temperature may be used.

The gate electrode 140 is disposed on the substrate 110 . The gate electrode 140 is an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, molybdenum ( Mo) or a molybdenum-based metal such as a molybdenum alloy, may include at least one of chromium (Cr), tantalum (Ta), neodium (Nd), and titanium (Ti). The gate electrode 140 may have a multilayer structure including at least two conductive layers having different physical properties.

A gate insulating layer 120 is disposed on the gate electrode 140 . The gate insulating layer 120 may include at least one of silicon oxide and silicon nitride, and may include aluminum oxide (Al ₂ O ₃ ). The gate insulating layer 120 may have a single layer structure or a multilayer structure.

The oxide semiconductor layer 130 is disposed on the gate insulating layer 120 . The oxide semiconductor layer 130 is insulated from the gate electrode 140 by the gate insulating layer 120 . A detailed configuration of the oxide semiconductor layer 130 will be described later.

A source electrode 150 and a drain electrode 160 are disposed on the oxide semiconductor layer 130 . The source electrode 150 is connected to the oxide semiconductor layer 130 . The drain electrode 160 is spaced apart from the source electrode 150 and is connected to the oxide semiconductor layer 130 .

The source electrode 150 and the drain electrode 160 include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodium (Nd), copper ( Cu), and at least one of alloys thereof. Each of the source electrode 150 and the drain electrode 160 may be formed of a single layer made of a metal or a metal alloy, or may be formed of a multilayer of two or more layers.

The oxide semiconductor layer 130 , the gate electrode 140 , the source electrode 150 , and the drain electrode 160 form the thin film transistor 100 .

Hereinafter, the configuration of the oxide semiconductor layer 130 will be described in detail.

According to an embodiment of the present invention, the oxide semiconductor layer 130 includes a first oxide semiconductor layer 131 on the gate insulating layer 120 and a second oxide semiconductor layer 132 on the first oxide semiconductor layer 131 . do. The first oxide semiconductor layer 131 has a first surface S1 facing the gate electrode 140 and a second surface S2 facing the gate electrode 140 , and the second oxide semiconductor layer 132 is 1 has a nitrogen concentration higher than that of the oxide semiconductor layer 131 .

The channel of the thin film transistor 100 is formed in the first oxide semiconductor layer 131 . Accordingly, the first oxide semiconductor layer 131 is also referred to as a “channel layer” or an “active layer”. The first oxide semiconductor layer 131 includes an oxide semiconductor material. For example, the first oxide semiconductor layer 131 is IZO (InZnO)-based, IGO (InGaO)-based, ITO (InSnO)-based, IGZO (InGaZnO)-based, IGZTO (InGaZnSnO)-based, GZTO (GaZnSnO)-based, GZO It may be made of an oxide semiconductor material such as (GaZnO)-based, ITZO (InSnZnO)-based, or the like. However, the embodiment of the present invention is not limited thereto, and the first oxide semiconductor layer 131 may be made of other oxide semiconductor materials known in the art.

The second oxide semiconductor layer 132 protects the first oxide semiconductor layer 131 serving as a channel layer. Accordingly, the second oxide semiconductor layer 132 is also referred to as a “protective layer”. The second oxide semiconductor layer 132 includes an oxide semiconductor material and nitrogen (N). For example, the second oxide semiconductor layer 132 is IZO (InZnO)-based, IGO (InGaO)-based, ITO (InSnO)-based, IGZO (InGaZnO)-based, IGZTO (InGaZnSnO)-based, GZTO (GaZnSnO)-based, GZO oxide semiconductor materials such as (GaZnO) based, ITZO (InSnZnO) based, and nitrogen (N). The second oxide semiconductor layer 132 includes the same oxide semiconductor material as that of the first oxide semiconductor layer 131 , and may further include nitrogen (N).

The second oxide semiconductor layer 132 includes nitrogen having a higher concentration than that of the first oxide semiconductor layer 131 . Nitrogen included in the second oxide semiconductor layer 132 forms a stable bond with oxygen and may be stably disposed between metal elements. As such, the second oxide semiconductor layer 132 including nitrogen has excellent film stability. The second oxide semiconductor layer 132 has excellent resistance to processes such as exposure, etching, patterning, and heat treatment for manufacturing the thin film transistor 100 , and protects the lower first oxide semiconductor layer 131 .

Nitrogen is added to the oxide semiconductor layer 130 by preventing oxygen (O) or other elements from escaping during the etching, patterning, or heat treatment process during the manufacturing process of the thin film transistor 100 or the manufacturing process of the display device using the thin film transistor. prevent defects from occurring. For example, when an oxygen defect ( _VO ) is generated in the second oxide semiconductor layer 132 , the etchant penetrates through the defect site and the oxygen defect ( _VO ) may further increase. have. However, according to an embodiment of the present invention, since the oxygen defect (VO) position is filled by nitrogen, the oxygen defect ( _VO ) is reduced and the oxygen defect ( _VO ) is not increased by the etchant, so that the film stability is improved. can be improved 11A and 11B are schematic diagrams illustrating a bonding state of nitrogen in the second oxide semiconductor layer 132 . 11A and 11B, “N1” is nitrogen, “M1”, “M2”, and “M3” indicate a metal element, and “O” indicates oxygen. 11A and 11 , it can be seen that nitrogen (N1) forms a stable bond with oxygen (O) and metals (M1, M2, and M3) in the second oxide semiconductor layer 132 .

More specifically, the thin film transistor 100 of FIG. 1 has a BCE (Back Channel Etch) structure in which a channel region is exposed during the formation of the source electrode 150 and the drain electrode 160 . In the process of manufacturing the thin film transistor 100 of the BCE (Back Channel Etch) structure, the channel portion is etched and patterned for the formation of the source electrode 150 and the drain electrode 160 to form the source electrode 150 and the drain electrode ( 160). At this time, the oxide semiconductor layer 130 is exposed to an etching gas or an etching solution. According to an embodiment of the present invention, although the second oxide semiconductor layer 132 is exposed to an etching gas or an etching solution, it is not damaged by the etching gas or the etching solution because it has excellent film stability including nitrogen. Accordingly, the second oxide semiconductor layer 132 may protect the lower first oxide semiconductor layer 131 .

Specifically, the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 may be formed by sputtering deposition. In particular, the second oxide semiconductor layer 132 may be formed by sputtering deposition using an oxide semiconductor material and nitrogen. Accordingly, nitrogen may be uniformly distributed in the second oxide semiconductor layer 132 . As nitrogen is uniformly distributed in the second oxide semiconductor layer 132 , the second oxide semiconductor layer 132 has excellent film stability over the entire region, thereby effectively protecting the first oxide semiconductor layer 131 . have.

The concentration of nitrogen (N) included in the second oxide semiconductor layer 132 is 3 to 10 atomic% (at%) based on the number of atoms. When the concentration of nitrogen is less than 3 atomic %, the stability of the second oxide semiconductor layer 132 may not be sufficiently secured, so that the second oxide semiconductor layer 132 may not sufficiently protect the first oxide semiconductor layer 131 . On the other hand, when the concentration of nitrogen exceeds 10 atomic %, unbound nitrogen may exist in the second oxide semiconductor layer 132 , and thus the film quality of the second oxide semiconductor layer 132 is deteriorated, and thus the second oxide semiconductor layer 132 . The layer 132 may not sufficiently protect the first oxide semiconductor layer 131 .

The second oxide semiconductor layer 132 may have a surface resistance of 10 ² to 10 ⁶ times that of the first oxide semiconductor layer 131 . When the surface resistance of the second oxide semiconductor layer 132 is less than 100 times the surface resistance of the first oxide semiconductor layer 131 , the film stability of the second oxide semiconductor layer 132 may not be sufficiently secured. On the other hand, when the second oxide semiconductor layer 132 contains an excess of nitrogen such that the surface resistance of the second oxide semiconductor layer 132 exceeds 10 ⁶ times the surface resistance of the first oxide semiconductor layer 131 , the second oxide semiconductor layer 132 contains an excess of nitrogen. The film-forming ability of the 2 oxide semiconductor layer 132 may be lowered, and film stability may be lowered.

For example, the first oxide semiconductor layer 131 may have a surface resistance of 1 to 10 kΩ/square, and the second oxide semiconductor layer 132 may have a surface resistance of 1 MΩ/square to 10 GΩ/square. can When the surface resistance of the first oxide semiconductor layer 131 is less than 1 kΩ/square, the first oxide semiconductor layer 131 may exhibit a conduction behavior, and when the surface resistance of the first oxide semiconductor layer 131 exceeds 10 kΩ/square, the current of the thin film transistor 100 Driving characteristics may be deteriorated. When the surface resistance of the second oxide semiconductor layer 132 is less than 1 MΩ/square, oxygen defects (Vo) are not sufficiently filled by nitrogen (N), and film stability due to the presence of defect sites this may be lowered. When the surface resistance of the second oxide semiconductor layer 132 is 10 GΩ/square, it corresponds to a state in which oxygen defects Vo are sufficiently filled by nitrogen (N). Therefore, it is not necessary to consume an additional process or cost for increasing the surface resistance of the second oxide semiconductor layer 132 to exceed 10 GΩ. However, the embodiment of the present invention is not limited thereto, and the second oxide semiconductor layer 132 may have a surface resistance exceeding 10 GΩ. For example, the second oxide semiconductor layer 132 may have a surface resistance of greater than 10 GΩ and less than or equal to 100 GΩ.

The first oxide semiconductor layer 131 may have a mobility of 50 to 5000 times that of the second oxide semiconductor layer 132 . When the mobility of the first oxide semiconductor layer 131 is less than 50 times the mobility of the second oxide semiconductor layer 132 , the electrical characteristics of the first oxide semiconductor layer 131 are lowered and the thin film transistor 100 is switched Characteristics or driving characteristics may be degraded. On the other hand, when the mobility of the first oxide semiconductor layer 131 exceeds 5000 times that of the second oxide semiconductor layer 132 , the first oxide semiconductor layer 131 is excessively conductive and the oxide semiconductor layer 130 may exhibit a behavior similar to that of a conductor as a whole.

According to an embodiment of the present invention, the second oxide semiconductor layer 132 has a thickness of 3 nm or more. When the thickness of the second oxide semiconductor layer 132 is less than 3 nm, coupling between nitrogen and other elements in the second oxide semiconductor layer 132 may not be smooth and nitrogen may not sufficiently fill defect sites. . Therefore, when the thickness of the second oxide semiconductor layer 132 is less than 3 nm, the second oxide semiconductor layer 132 is etched or lost in the etching and patterning process so that the second oxide semiconductor layer 132 is formed as the first oxide semiconductor layer ( 131) may not be sufficiently protected. On the other hand, when the thickness of the second oxide semiconductor layer 132 is 10 nm, it is sufficient to protect the first oxide semiconductor layer 131, so the thickness of the second oxide semiconductor layer 132 is increased more than necessary to increase the amount of material used or There is no need to increase the process cost. Accordingly, the thickness of the second oxide semiconductor layer 132 may be adjusted in a range of 3 to 10 nm. However, an embodiment of the present invention is not limited thereto, and the second oxide semiconductor layer 132 may have a thickness exceeding 10 nm. For example, the second oxide semiconductor layer 132 may have a thickness of greater than 10 nm and less than or equal to 50 nm, and may have a thickness of greater than 10 nm and less than or equal to 100 nm.

According to an embodiment of the present invention, the second oxide semiconductor layer 132 does not overlap the source electrode 150 and the drain electrode 160 among the first surface S1 of the first oxide semiconductor layer 131 . cover the area Specifically, a region of the first surface S1 of the first oxide semiconductor layer 131 that does not overlap the source electrode 150 and the drain electrode is protected by the second oxide semiconductor layer 132 . Referring to FIG. 1 , the second oxide semiconductor layer 132 covers the entire first surface S1 of the first oxide semiconductor layer 131 . Accordingly, the entire first surface S1 of the first oxide semiconductor layer 131 may be protected by the second oxide semiconductor layer 132 . In addition, a region overlapping the source electrode 150 and the drain electrode 160 of the first surface S1 of the first oxide semiconductor layer 131 is also protected by the source electrode 150 and the drain electrode 160 .

In the thin film transistor 100 of FIG. 1 , a part of the first oxide semiconductor layer 131 contacts the source electrode 150 , and another part of the first oxide semiconductor layer 100 contacts the drain electrode 160 . Referring to FIG. 1 , the first oxide semiconductor layer 131 contacts the source electrode 150 on the left side and the drain electrode 160 on the right side. As described above, the first oxide semiconductor layer 131 in contact with the source electrode 150 and the drain electrode 160 may serve as a channel layer.

2 is a cross-sectional view of a thin film transistor 200 according to another embodiment of the present invention. Hereinafter, in order to avoid duplication, descriptions of the already described components will be omitted.

According to another embodiment of the present invention, the second oxide semiconductor layer 132 has a different plane from the first oxide semiconductor layer 131 , and the second oxide semiconductor layer 132 is the first oxide semiconductor layer 131 . covers a portion of the first surface S1 of the More specifically, at least a portion of the first surface S1 of the first oxide semiconductor layer 131 is exposed from the second oxide semiconductor layer 132 .

Referring to FIG. 2 , a portion of the first surface S1 is exposed from the second oxide semiconductor layer 132 . Accordingly, at least a portion of the first surface S1 of the first oxide semiconductor layer 131 may be in contact with the source electrode 150 , and another portion of the first surface S1 of the first oxide semiconductor layer 131 may be in contact with the source electrode 150 . may be in contact with the drain electrode 160 . As a result, compared to the thin film transistor 100 shown in FIG. 1 , in the thin film transistor 200 shown in FIG. 2 , the contact region between the first oxide semiconductor layer 131 and the source electrode 150 and the first oxide A contact area between the semiconductor layer 131 and the drain electrode 160 increases. Due to the increase in the contact area, electrical connection characteristics between the first oxide semiconductor layer 131 and the source electrode 150 and the first oxide semiconductor layer 131 and the drain electrode 160 may be improved.

Hereinafter, a method of manufacturing the thin film transistor 200 will be described with reference to FIGS. 3A to 3H . 3A to 3H are manufacturing process diagrams of a thin film transistor 200 according to another exemplary embodiment of the present invention.

Referring to FIG. 3A , the gate electrode 140 is formed on the substrate 110 .

Glass may be used as the substrate 110 , and transparent plastic that can be bent or bent may be used. An example of the plastic used as the substrate 110 is polyimide. When plastic is used as the substrate 110 , the manufacturing process may be performed while the substrate 110 is disposed on a carrier substrate made of a highly durable material.

A gate electrode 140 is formed on the substrate 110 . The gate electrode 140 is an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, molybdenum ( Mo) or a molybdenum-based metal such as a molybdenum alloy, it may be formed of at least one of chromium (Cr), tantalum (Ta), neodium (Nd), and titanium (Ti). The gate electrode 140 may be formed of a single layer or a multi-layered layer.

Referring to FIG. 3B , the gate insulating layer 120 is formed on the gate electrode 140 . As a result, the first deposition target substrate 101 is formed. According to an embodiment of the present invention, the first deposition target substrate 101 is formed by forming the gate electrode 140 and the gate insulating layer 120 on the substrate 110 .

Next, the oxide semiconductor layer 130 is formed on the gate insulating layer 120 . The oxide semiconductor layer 130 includes a first oxide semiconductor layer 131 and a second oxide semiconductor layer 132 , and overlaps the gate electrode 140 .

Specifically, referring to FIGS. 3C and 4 , the first oxide semiconductor material layer 131a on the gate insulating film 120 by sputtering deposition under an oxygen gas (O ₂ ) containing atmosphere in the chamber 10 . this is formed As a result, the second deposition target substrate 102 is formed.

The first oxide semiconductor material layer 131a is, for example, an IZO (InZnO)-based oxide semiconductor material, an IGO (InGaO)-based oxide semiconductor material, an ITO (InSnO)-based oxide semiconductor material, or an IGZO (InGaZnO)-based oxide semiconductor material. , IGZTO (InGaZnSnO)-based oxide semiconductor material, GZTO (GaZnSnO)-based oxide semiconductor material, GZO (GaZnO)-based oxide semiconductor material, and ITZO (InSnZnO)-based oxide semiconductor material may be made of at least one. The first oxide semiconductor material layer 131a may be formed by sputtering deposition.

3D and 5, the first oxide semiconductor material layer 131a by sputtering deposition under an atmosphere containing oxygen gas (O ₂ ) and nitrogen gas (N ₂ ) in the chamber 10 . Two oxide semiconductor material layer 132a is formed. The second oxide semiconductor material layer 132a includes an oxide semiconductor material and nitrogen (N). The second oxide semiconductor layer 132 is IZO (InZnO)-based, IGO (InGaO)-based, ITO (InSnO)-based, IGZO (InGaZnO)-based, IGZTO (InGaZnSnO)-based, GZTO (GaZnSnO)-based, GZO (GaZnO)-based , it may be made of an oxide semiconductor material such as InSnZnO (ITZO) and nitrogen (N). For example, the second oxide semiconductor material layer 132a may include the same oxide semiconductor material as the first oxide semiconductor material layer 131a.

Hereinafter, sputtering deposition for forming the oxide semiconductor layer 130 will be described in detail with reference to FIGS. 4 and 5 .

4 is a schematic diagram illustrating sputtering deposition for forming the first oxide semiconductor layer 131 .

Referring to FIG. 4 , in order to form the oxide semiconductor layer 130 , first, the first deposition target substrate 101 formed by forming the gate electrode 140 and the gate insulating layer 120 on the substrate 110 is performed in a chamber. (10) is introduced. Next, a first oxide semiconductor material layer 131a is formed on the gate insulating layer 120 by sputtering deposition under an oxygen gas (O ₂ ) containing atmosphere in the chamber 10 .

In FIG. 4 , a sputtering target is disposed on a cathode of the chamber 10 . According to an embodiment of the present invention, a metal for forming an oxide semiconductor layer is used as a sputtering target. For example, the sputtering target includes at least one of indium (In), gallium (Ga), zinc (Zn), and tin (Sn). A first deposition target substrate 101 is disposed on an anode of the chamber 10 .

A sputtering gas is introduced into the chamber 10 for sputtering deposition. Argon (Ar) and oxygen gas (O ₂ ) are used as sputtering gases for forming the first oxide semiconductor material layer 131a. Plasma is formed in the chamber 10 , and a first oxide semiconductor material layer 131a is formed on the gate insulating layer 120 by plasma deposition. As a result, the second deposition target substrate 102 is formed.

FIG. 5 is a schematic diagram illustrating sputtering deposition for forming the second oxide semiconductor layer 132 .

Referring to FIG. 5 , a second oxide semiconductor material layer 132a is formed on the first oxide semiconductor material layer 131a in an atmosphere containing oxygen gas (O ₂ ) and nitrogen gas (N ₂ ) in the chamber 10 . . The forming of the first oxide semiconductor material layer 131a and the forming of the second oxide semiconductor material layer 132a may be performed in a continuous process in the same chamber 10 .

In FIG. 5 , a sputtering target is disposed on a cathode of the chamber 10 . The sputtering target includes at least one of indium (In), gallium (Ga), zinc (Zn), and tin (Sn). A second deposition target substrate 102 is positioned at an anode of the chamber 10 .

The sputtering gas for forming the second oxide semiconductor material layer 131a includes argon (Ar), oxygen gas (O ₂ ), and nitrogen gas (N ₂ ). Plasma is formed in the chamber 10 , and a second oxide semiconductor material layer 132a is formed on the first oxide semiconductor material layer 131a by plasma deposition.

By sputtering deposition, nitrogen is uniformly distributed irrespective of position in the second oxide semiconductor material layer 132a. As a result, the second oxide semiconductor layer 132 may have a uniform nitrogen concentration in the entire region.

In the step of forming the second oxide semiconductor material layer 132a shown in FIGS. 3D and 5 , nitrogen gas (N ₂ ) has a flow rate of 0.1 to 50% compared to oxygen gas (O ₂ ). When the flow rate of nitrogen gas (N ₂ ) is less than 0.1% compared to the flow rate of oxygen gas (O ₂ ), nitrogen is included in a trace amount in the second oxide semiconductor material layer 132a, so that the second oxide semiconductor layer 132 is excellent. It may not have membrane stability. On the other hand, when the flow rate of the nitrogen gas (N ₂ ) exceeds 50% of the flow rate of the oxygen gas (O ₂ ), the film stability of the second oxide semiconductor material layer 132a is reduced due to the excessive nitrogen, and as a result , the film stability of the second oxide semiconductor layer 132 may be reduced.

In the step of forming the second oxide semiconductor material layer 132a, the flow rate of the nitrogen gas (N ₂ ) is adjusted to 0.1 to 50% compared to the flow rate of the oxygen gas (O ₂ ), the second oxide semiconductor material layer 132a ), the second oxide semiconductor layer 132 may include nitrogen (N) at a concentration of 3 to 10 atomic% (at%) based on the number of atoms.

In addition, the second oxide semiconductor material layer 132a is formed to have a thickness of 3 nm or more. As a result, the second oxide semiconductor layer 132 may have a thickness of 3 nm or more to stably protect the first oxide semiconductor layer 131 .

After the first oxide semiconductor material layer 131a and the second oxide semiconductor material layer 132a are formed, the first oxide semiconductor material layer 131a and the second oxide semiconductor material layer 132a are patterned to form a first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 are formed.

Specifically, referring to FIG. 3E , a photoresist layer 175 is formed on the second oxide semiconductor material layer 132a. The photoresist layer 175 may be formed of, for example, a negative photoresist.

Next, after the pattern mask 210 is disposed on the photoresist layer 175 , exposure is performed. The pattern mask 210 includes a light blocking portion 211 , a semi-transmissive portion 212 , and a light transmitting portion 213 . Selective exposure is performed by irradiating the light L1 through the pattern mask 210 . Ultraviolet rays may be irradiated for exposure.

Referring to FIG. 3F , a photoresist pattern 176 is formed by exposure and development using the pattern mask 210 . Etching is performed using the photoresist pattern 176 as a mask. As the etching method, dry etching (D/E) may be applied.

Referring to FIG. 3G , the first oxide semiconductor material layer 131a and the second oxide semiconductor material layer 132a are patterned by dry etching (D/E) to form the first oxide semiconductor layer 131 and the second oxide semiconductor layer. Layer 132 is formed.

Referring to FIG. 3G , the first oxide semiconductor layer 131 has a first surface S1 facing the gate electrode 140 and a second surface S2 facing the gate electrode 140 . In addition, in the step of forming the oxide semiconductor layer 130 , the second oxide semiconductor layer S2 is patterned so that at least a portion of the first surface S1 is exposed from the second oxide semiconductor layer.

Referring to FIG. 3H , a source electrode 150 and a drain electrode 160 respectively connected to the oxide semiconductor layer 130 and spaced apart from each other are formed. As a result, the thin film transistor 200 is completed. At this time, as the second oxide semiconductor layer 132 is patterned so that the first surface S1 of the first oxide semiconductor layer 131 can directly contact the source electrode 150 and the drain electrode 160 , the oxide Electrical connection characteristics between the semiconductor layer 130 and the source electrode 150 and the drain electrode 160 may be improved.

However, the exemplary embodiment is not limited thereto, and the second oxide semiconductor layer 132 may be patterned to have the same plane as the first oxide semiconductor layer 131 . More specifically, in the exposure and development step of FIG. 3E , when a pattern mask having only the light-shielding portion 211 and the light-transmitting portion 213 without the semi-transmissive portion 212 is used, the second oxide semiconductor layer 132 . It may be patterned to have the same plane as the first oxide semiconductor layer 131 . In this case, the thin film transistor 100 as shown in FIG. 1 may be manufactured.

6 is a schematic cross-sectional view of a display device 300 according to another embodiment of the present invention.

The display device 300 according to another embodiment of the present invention includes a substrate 110 , a thin film transistor 200 , and an organic light emitting diode 270 connected to the thin film transistor 200 .

6 illustrates a display device 300 including the thin film transistor 200 of FIG. 2 . However, another embodiment of the present invention is not limited thereto, and the thin film transistor 100 shown in FIG. 1 may be applied to the display device 300 of FIG. 6 .

Referring to FIG. 6 , the display device 300 includes a substrate 110 , a thin film transistor 200 on the substrate 110 , and a first electrode 271 connected to the thin film transistor 200 . In addition, the display device 300 includes an organic layer 272 on the first electrode 271 and a second electrode 273 on the organic layer 272 .

Specifically, the substrate 110 may be made of glass or plastic. A buffer layer (not shown) may be disposed on the substrate 110 .

The thin film transistor 200 is disposed on the substrate 110 . The thin film transistor 200 is connected to the gate electrode 140 on the substrate 110 , the gate insulating film 120 on the gate electrode 140 , the oxide semiconductor layer 130 on the gate insulating film 120 , and the oxide semiconductor layer 130 . It includes a source electrode 150 and a drain electrode 160 spaced apart from the source electrode 150 and connected to the oxide semiconductor layer 130 . The oxide semiconductor layer 130 at least partially overlaps the gate electrode 140 . In addition, the oxide semiconductor layer 130 includes a first oxide semiconductor layer 131 on the gate insulating layer 120 and a second oxide semiconductor layer 132 on the first oxide semiconductor layer 131 . The first oxide semiconductor layer 131 has a first surface S1 facing the gate electrode 140 and a second surface S2 facing the gate electrode 140 , and the second oxide semiconductor layer 132 is 1 has a nitrogen concentration higher than that of the oxide semiconductor layer 131 .

An interlayer insulating layer 191 is disposed on the thin film transistor 200 . The interlayer insulating film 191 protects the thin film transistor 200 .

The planarization layer 190 is disposed on the interlayer insulating layer 191 to planarize an upper portion of the substrate 110 . The planarization layer 190 may be made of an organic insulating material such as an acrylic resin having photosensitivity, but is not limited thereto.

The first electrode 271 is disposed on the planarization layer 190 . The first electrode 271 is connected to the drain electrode 160 of the thin film transistor 200 through a contact hole provided in the planarization layer 190 .

The bank layer 250 is disposed on the first electrode 271 and the planarization layer 190 to define a pixel area or a light emitting area. For example, since the bank layer 250 is disposed in a matrix structure in a boundary region between a plurality of pixels, a pixel region may be defined by the bank layer 250 .

The organic layer 272 is disposed on the first electrode 271 . The organic layer 272 may also be disposed on the bank layer 250 . That is, the organic layer 272 may be connected to each other between adjacent pixels without being separated for each pixel.

The organic layer 272 includes an organic emission layer. The organic layer 272 may include one organic emission layer, or two or more organic emission layers stacked vertically. Light having any one of red, green, and blue may be emitted from the organic layer 272 , and white light may be emitted from the organic layer 272 .

The second electrode 273 is disposed on the organic layer 272 .

The first electrode 271 , the organic layer 272 , and the second electrode 273 may be stacked to form the organic light emitting diode 270 . The organic light emitting device 270 may serve as a light amount adjusting layer in the display device 300 .

Although not shown, when the organic layer 272 emits white light, each pixel may include a color filter for filtering the white light emitted from the organic layer 272 for each wavelength. A color filter is formed on the path of light. In the case of a so-called bottom emission method in which light emitted from the organic layer 272 travels in the direction of the lower substrate 110 , a color filter is disposed under the organic layer 272 and emitted from the organic layer 272 . In the case of a so-called top emission method in which the emitted light travels in the direction of the upper second electrode 273 , the color filter is disposed on the organic layer 272 .

7 is a schematic cross-sectional view of a display device 400 according to another exemplary embodiment of the present invention.

Referring to FIG. 7 , a display device 400 according to another embodiment of the present invention includes a substrate 110 , a thin film transistor 200 disposed on the substrate 110 , and a first connected thin film transistor 200 . It includes an electrode 381 . Also, the display device 400 includes a liquid crystal layer 382 on the first electrode 381 and a second electrode 383 on the liquid crystal layer 382 .

The liquid crystal layer 382 acts as a light quantity control layer. As such, the display device 400 illustrated in FIG. 7 is a liquid crystal display device including the liquid crystal layer 382 .

Specifically, the display device 400 of FIG. 7 includes a substrate 110 , a thin film transistor 200 , a planarization film 190 , a first electrode 381 , a liquid crystal layer 382 , a second electrode 383 , It includes a barrier layer 320 , color filters 341 and 342 , a light blocking unit 350 , and a counter substrate 310 .

The substrate 110 may be made of glass or plastic. A buffer layer (not shown) may be disposed on the substrate 110 .

Referring to FIG. 7 , the thin film transistor 200 is disposed on a substrate 110 . Since the thin film transistor 200 has already been described, a detailed description of its configuration will be omitted.

An interlayer insulating layer 191 is disposed on the thin film transistor 200 . The interlayer insulating film 191 protects the thin film transistor 200 .

The planarization layer 190 is disposed on the interlayer insulating layer 191 to planarize an upper portion of the substrate 110 .

The first electrode 381 is disposed on the planarization layer 190 . The first electrode 381 is connected to the drain electrode 160 of the thin film transistor 200 through the contact hole CH5 provided in the planarization layer 190 .

The opposing substrate 310 is disposed to face the substrate 110 .

A light blocking unit 350 is disposed on the opposite substrate 310 . The light blocking unit 350 has a plurality of openings. The plurality of openings are disposed to correspond to the first electrode 381 which is a pixel electrode. The light blocking unit 350 blocks light in portions except for the openings. The light blocking unit 350 is not necessarily required and may be omitted.

The color filters 341 and 342 are disposed on the opposite substrate 310 and selectively block the wavelength of light incident from the backlight unit (not shown). Specifically, the color filters 341 and 342 may be disposed in a plurality of openings defined by the light blocking unit 350 . Each of the color filters 341 and 342 may express any one of red, green, and blue colors. Each of the color filters 341 and 342 may express colors other than red, green, and blue.

A barrier layer 320 may be disposed on the color filters 341 and 342 and the light blocking unit 350 . The barrier layer 320 may be omitted.

The second electrode 383 is disposed on the barrier layer 320 . For example, the second electrode 383 may be positioned on the front surface of the opposite substrate 310 . The second electrode 383 may be made of a transparent conductive material such as ITO or IZO.

The first electrode 381 and the second electrode 383 are disposed to face each other, and a liquid crystal layer 382 is disposed therebetween. The second electrode 383 applies an electric field to the liquid crystal layer 382 together with the first electrode 381 .

When the opposing surfaces between the substrate 110 and the opposite substrate 310 are respectively defined as the upper surface of the corresponding substrate, and surfaces located opposite the upper surfaces are respectively defined as the lower surface of the corresponding substrate, the substrate 110 A polarizing plate may be respectively disposed on the lower surface of the polarizer and the lower surface of the opposite substrate 310 .

Hereinafter, the present invention will be described in more detail with reference to Examples, Comparative Examples and Test Examples.

[Example 1]

A 100 nm-thick gate electrode 140 made of an alloy of Mo/Ti was formed on the substrate 110 made of glass, and a gate insulating layer 120 made of silicon oxide was formed thereon. The oxide semiconductor layer 130 was formed on the gate insulating layer 120 to overlap the gate electrode. The oxide semiconductor layer includes a first oxide semiconductor layer 131 on the gate insulating layer 120 and a second oxide semiconductor layer 132 on the first oxide semiconductor layer 131 . The first oxide semiconductor layer 131 is formed of an IGZO-based oxide semiconductor material having a ratio of indium (In) gallium (Ga) to zinc (Zn) 1:1:1 based on the number of atoms. The second oxide semiconductor layer 132 was formed to include nitrogen (N) and an IGZO-based oxide semiconductor material having a ratio of indium (In), gallium (Ga), and zinc (Zn) of 1:1:1 based on the number of atoms. . When forming the first oxide semiconductor layer 131 by sputtering deposition, the flow rate of oxygen gas was adjusted to 50 sccm. In addition, when forming the second oxide semiconductor layer 132 by sputtering deposition, the flow rate of oxygen gas was adjusted to 50 sccm and the flow rate of nitrogen gas to 5 sccm. Next, the thin film transistor was completed by forming a source electrode 150 and a drain electrode 160 having a thickness of 100 nm having a BCE structure using a Mo/Ti alloy.

[Comparative Example 1]

After the thin film transistor was manufactured in the same manner as in Example 1, except that only the first oxide semiconductor layer 131 was formed without forming the second oxide semiconductor layer 132 among the oxide semiconductor layers 130 , the comparison was made. It was called Example 1.

[Comparative Example 2]

After manufacturing a thin film transistor in the same manner as in Example 1, except that only the second oxide semiconductor layer 132 was formed without forming the first oxide semiconductor layer 131 among the oxide semiconductor layers 130, this was used as a comparative example. was called 2. In the process of forming the second oxide semiconductor layer 132 , the flow rate of oxygen gas was adjusted to 100 sccm and the flow rate of nitrogen gas to 2 sccm.

[Comparative Example 3]

In the process of forming the second oxide semiconductor layer 132, a thin film transistor was manufactured in the same manner as in Comparative Example 2, except that the flow rate of oxygen gas was adjusted to 100 sccm and the flow rate of nitrogen gas to 4 sccm, and this was referred to as Comparative Example 3. .

[Test Example 1] Threshold voltage (Vth) measurement

Threshold voltages (Vth) were measured for the thin film transistors of Comparative Examples 1 to 3 and Example 1. To measure the threshold voltage (Vth), the drain current ( _IDS ) was measured while applying a gate voltage (V _G ) in the range of -20V to +20V. Voltages of 0.1V and 10V were applied between the source electrode 150 and the drain electrode 160 .

8A to 8D are the threshold voltage (Vth) measurement results for the thin film transistor.

8A is a measurement result of the threshold voltage (Vth) of the thin film transistor of Comparative Example 1. Referring to FIG. Referring to FIG. 8A , it can be seen that, in the case of the thin film transistor of Comparative Example 1, the deviation of the current distribution is large, so that it is difficult to measure the threshold voltage. This is determined to be a result of damage to the channel region in the process of forming the source electrode 150 and the drain electrode 160 of the thin film transistor having the BCE structure.

8B is a measurement result of the threshold voltage (Vth) of the thin film transistor of Comparative Example 2. Referring to FIG. According to Comparative Example 2, the oxide semiconductor layer 130 does not include the first oxide semiconductor layer 131 , but includes only the second oxide semiconductor layer 132 , and the second oxide semiconductor layer 132 containing nitrogen It acts as a channel layer. Referring to FIG. 8B , it can be seen that the thin film transistor of Comparative Example 2 has poor current characteristics. In the thin film transistor of Comparative Example 2, it was confirmed that the threshold voltage (Vth) was 1.06 V, the mobility was 0.06 cm ² /V*s, and the surface resistance was 91 mΩ.

8C is a measurement result of the threshold voltage (Vth) of the thin film transistor of Comparative Example 3. Referring to FIG. According to Comparative Example 3, the oxide semiconductor layer 130 includes only the second oxide semiconductor layer 132, and the second oxide semiconductor layer 132 includes nitrogen at a higher concentration than in Comparative Example 2. Referring to FIG. 8C , it can be seen that the thin film transistor of Comparative Example 3 has very poor current characteristics. In the thin film transistor of Comparative Example 3, it was confirmed that the threshold voltage (Vth) was 1.51 V, the mobility was 0.006 cm ² /V*s, and the surface resistance was 1 GΩ.

8D is a measurement result of a threshold voltage (Vth) for the thin film transistor of Example 1. Referring to FIG. Referring to FIG. 8D , in the thin film transistor according to Example 1, it was confirmed that the threshold voltage (Vth) was 0.83 V, the mobility was 7.31 cm ² /V*s, and the surface resistance was 2.79 kΩ. As such, it was confirmed that the thin film transistor according to Example 1 had superior electrical characteristics compared to the thin film transistors according to Comparative Examples 1 to 3.

[Test Example 2] Binding energy measurement

The binding energy distribution of the oxide semiconductor layer was measured by X-ray photoelectron spectroscopy. When X-rays are irradiated to a material, photoelectrons are emitted out of the material. Since the kinetic energy reflects the magnitude of the bonding force of the atoms constituting the material, it is possible to investigate the atomic composition of the material and the bonding state of electrons.

9 is an X-ray photoelectron spectroscopic analysis graph for an oxide semiconductor layer. In FIG. 9 , reference numeral 131 denotes a measurement result of the first oxide semiconductor layer 131 , and reference numeral 132 denotes a measurement result of the second oxide semiconductor layer 132 . Referring to FIG. 9 , in the measurement result of the second oxide semiconductor layer 132, a peak is generated in a binding energy region near 404 eV corresponding to an N-O bond and a binding energy region near 403 eV corresponding to an N-N bond. Able to know. Accordingly, it can be seen that the second oxide semiconductor layer 132 has a greater ratio of N-O bonds and N-N bonds than the first oxide semiconductor layer 131 .

[Example 2] and [Test Example 3] Current change measurement

The same as in Example 1, except that in the process of forming the second oxide semiconductor layer 132, the flow rate of oxygen gas was adjusted to 50 sccm and the flow rate of nitrogen gas to 25 sccm to manufacture a thin film transistor, which was referred to as Example 2.

For the thin film transistor of Example 2 and the thin film transistor of Comparative Example 2, while applying the gate voltages V _G of 0, 5, 10, 15, 20, 25 and 30V, the source electrode 150 and the drain electrode 160 ) to measure the change in the drain current (I _DS ) according to the change in the voltage (V _DS ) between them.

10A and 10B are graphs of current change measurement of an oxide semiconductor layer, respectively. In FIGS. 10A and 10B , the x-axis represents the voltage V _DS applied between the source electrode 150 and the drain electrode 160 , and the y-axis represents the drain current I _DS .

10A shows a change in current measured in the thin film transistor of Example 2. FIG. Referring to FIG. 10B , when gate voltages V _G of 10, 15, 20, 25, and 30V are applied, it can be seen that a drain current ( _IDS ) characteristic suitable for a switching device is obtained.

10B shows a change in current measured in the thin film transistor of Comparative Example 2. Referring to FIG. The oxide semiconductor layer 130 constituting the thin film transistor of Comparative Example 2 has a high resistance. Accordingly, referring to FIG. 10B , when the gate voltages V _G of 5, 10, 15, 20, 25 and 30V are respectively applied, the voltage V _DS between the source electrode 150 and the drain electrode 160 is Even if it increases, there is no period in which the drain current I _DS is saturated after the instantaneous change. As such, it can be seen that the thin film transistor of Comparative Example 2 does not have on-off switching characteristics, and thus is not suitable as an element such as a display device.

As such, the thin film transistor according to an embodiment of the present invention has excellent reliability. In addition. A display device according to an embodiment of the present invention including such a thin film transistor may have excellent display characteristics.

The present invention described above is not limited by the above-described embodiments and the accompanying drawings, and it is in the technical field to which the present invention pertains that various substitutions, modifications and changes are possible without departing from the technical matters of the present invention. It will be clear to those of ordinary skill in the art. Therefore, the scope of the present invention is indicated by the following claims, and all changes or modifications derived from the meaning, scope, and equivalent concepts of the claims should be construed as being included in the scope of the present invention.

100, 200: thin film transistor
110: substrate 121: first insulating film
122: second insulating layer 130: oxide semiconductor layer
131: first oxide semiconductor layer 132: second oxide semiconductor layer
140: gate electrode 150: source electrode
160: drain electrode 190: planarization film
250: bank layer 270: organic light emitting device
271, 381: first electrode 272: organic layer
273, 383: second electrode 310: opposing substrate
341, 342: color filter 350: light blocking part
382: liquid crystal layer 300, 400: display device
S1: first surface S2: second surface

Claims (15)

a gate electrode on the substrate;
a gate insulating film on the gate electrode;
an oxide semiconductor layer on the gate insulating layer that at least partially overlaps the gate electrode;
a source electrode connected to the oxide semiconductor layer; and
and a drain electrode spaced apart from the source electrode and connected to the oxide semiconductor layer;
The oxide semiconductor layer may include a first oxide semiconductor layer on the gate insulating layer; and a second oxide semiconductor layer on the first oxide semiconductor layer;
The first oxide semiconductor layer has a first surface opposite to the gate electrode and a second surface facing the gate electrode,
The second oxide semiconductor layer has a higher nitrogen concentration than the first oxide semiconductor layer,
The second oxide semiconductor layer has a surface resistance of 10 ² to 10 ⁶ times that of the first oxide semiconductor layer, the thin film transistor. According to claim 1,
The nitrogen is uniformly distributed in the second oxide semiconductor layer, the thin film transistor. According to claim 1,
The concentration of nitrogen (N) in the second oxide semiconductor layer is 3 to 10 atomic% (at%) based on the number of atoms, the thin film transistor. According to claim 1,
The first oxide semiconductor layer has a mobility of 50 to 5000 times that of the second oxide semiconductor layer, the thin film transistor. According to claim 1,
The second oxide semiconductor layer has a thickness of 3 nm or more, a thin film transistor. According to claim 1,
and the second oxide semiconductor layer covers a region of the first surface of the first oxide semiconductor layer that does not overlap the source electrode and the drain electrode. According to claim 1,
at least a portion of the first surface of the first oxide semiconductor layer is in contact with the source electrode, and another portion of the first surface of the first oxide semiconductor layer is in contact with the drain electrode. forming a gate electrode on the substrate;
forming a gate insulating layer on the gate electrode;
forming an oxide semiconductor layer including a first oxide semiconductor layer and a second oxide semiconductor layer on the gate insulating layer;
and forming a source electrode and a drain electrode respectively connected to the oxide semiconductor layer and spaced apart from each other;
The step of forming the oxide semiconductor layer,
forming a first oxide semiconductor material layer on the gate insulating layer by sputtering deposition in an oxygen gas-containing atmosphere in a chamber;
forming a second oxide semiconductor material layer on the first oxide semiconductor material layer under an atmosphere containing oxygen gas and nitrogen gas in a chamber; and
patterning the first oxide semiconductor material layer and the second oxide semiconductor material layer to form the first oxide semiconductor layer and the second oxide semiconductor layer;
The second oxide semiconductor layer has a surface resistance of 10 ² to 10 ⁶ times that of the first oxide semiconductor layer,
A method for manufacturing a thin film transistor. 9. The method of claim 8,
In the forming of the second oxide semiconductor material layer, the nitrogen has a flow rate of 0.1 to 50% relative to the oxygen, a method of manufacturing a thin film transistor. 9. The method of claim 8,
The second oxide semiconductor layer includes nitrogen (N) in a concentration of 3 to 10 atomic% (at%) based on the number of atoms, the thin film transistor manufacturing method. 9. The method of claim 8,
The second oxide semiconductor layer has a thickness of 3 nm or more, a method of manufacturing a thin film transistor. 9. The method of claim 8,
The first oxide semiconductor layer has a first surface opposite to the gate electrode and a second surface facing the gate electrode,
In the forming of the oxide semiconductor layer, the second oxide semiconductor layer is patterned so that at least a portion of the first surface is exposed from the second oxide semiconductor layer. Board;
a thin film transistor on the substrate; and
a first electrode connected to the thin film transistor;
The thin film transistor is
a gate electrode on the substrate;
a gate insulating film on the gate electrode;
an oxide semiconductor layer on the gate insulating layer that at least partially overlaps the gate electrode;
a source electrode connected to the oxide semiconductor layer; and
and a drain electrode spaced apart from the source electrode and connected to the oxide semiconductor layer;
The oxide semiconductor layer may include a first oxide semiconductor layer on the gate insulating layer; and a second oxide semiconductor layer on the first oxide semiconductor layer;
The first oxide semiconductor layer has a first surface in a direction opposite to the gate electrode and a first surface in a direction toward the gate electrode,
The second oxide semiconductor layer has a higher nitrogen concentration than the first oxide semiconductor layer,
The second oxide semiconductor layer has a surface resistance of 10 ² to 10 ⁶ times that of the first oxide semiconductor layer,
display device.
According to claim 1,
the second oxide semiconductor layer is disposed on the first surface of the first oxide semiconductor layer;
at least a portion of the first surface of the first oxide semiconductor layer is exposed from the second oxide semiconductor layer. 14. The method of claim 13,
the second oxide semiconductor layer is disposed on the first surface of the first oxide semiconductor layer;
at least a portion of the first surface of the first oxide semiconductor layer is exposed from the second oxide semiconductor layer.

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