KR102436556B1 - Display Device - Google Patents

Abstract

An object of the present invention is to realize a narrow-bezel display device by discharging a node of a dummy stage circuit unit with a signal provided by itself. To this end, the present invention provides a display device having a display panel and a built-in gate driver. The built-in gate driver includes a next signal generator that provides a next signal to at least one stage circuit unit. The next signal generator generates a next signal based on at least one clock signal, a high potential power, and a low potential power.

Description

Display Device

The present invention relates to a display device.

As information technology develops, the market for display devices, which is a connection medium between users and information, is growing. Accordingly, the use of display devices such as an organic light emitting display (OLED), a liquid crystal display (LCD), and a plasma display panel (PDP) is increasing.

Some of the display devices described above, for example, a liquid crystal display device or an organic light emitting display device, include a display panel including a plurality of sub-pixels arranged in a matrix form and a driving unit for driving the display panel. The driver includes a gate driver that supplies a gate signal (or a scan signal) to the display panel, and a data driver that supplies a data signal to the display panel.

In the above-described display device, when a gate signal and a data signal are supplied to sub-pixels arranged in a matrix form, the selected sub-pixel emits light to display an image.

The gate driver for outputting a gate signal is divided into an external type mounted on an external substrate of the display panel in the form of an integrated circuit and a built-in type formed on the display panel in the form of a gate in panel (GIP) formed with a thin film transistor process.

The built-in gate driver sequentially outputs the gate signal based on the dependently connected shift registers. For this reason, the built-in gate driver requires a signal of the next stage to discharge the Q node existing inside the shift registers.

However, in the case of the last shift register(s), since there is no next stage, a separate signal must be received from the outside. As a result, the conventionally proposed built-in gate driver uses a method of further forming a signal line in the non-display area of the display panel and transmitting an external signal therethrough.

However, the conventionally proposed method leads to an increase in the bezel size when additional signal lines are to be formed in the non-display area, such as an enlargement of a display panel or an increase in a clock signal, and thus an improvement is required.

The present invention for solving the problems of the background art described above is to realize a narrow-bezel display device by discharging a node of a dummy stage circuit unit with a signal provided by itself.

As a means of solving the above problems, the present invention provides a display device having a display panel and a built-in gate driver. The display panel displays an image. The built-in gate driver includes shift registers having stage circuit parts cascadedly connected to supply a gate signal to the display panel, and a next signal generator providing a next signal to at least one stage circuit part of the stage circuit parts. The next signal generator generates a next signal based on at least one clock signal, a high potential power, and a low potential power.

The next signal generating unit may be disposed adjacent to the at least one stage circuit unit.

The next signal generating unit may be disposed in a non-display area of the display panel together with the stage circuit units.

The next signal generator may provide the next signal to the dummy stage circuit part that does not output the gate signal to the display area of the display panel among the stage circuit parts.

The next signal generating unit generates logic high next signals output from the first and second transistors corresponding to two clock signals having opposite phases and outputs a logic high next signal, and outputs a logic high next signal output from the first and second transistors to a logic low level. It may include a third transistor for resetting to the next signal.

The first and second transistors may have a period in which they are turned on simultaneously during a blank period in which an image of the display panel is not displayed, and the third transistor may have a period in which the first and second transistors are turned off and then turned on during the blank period. .

A plurality of next signal generators may be disposed to commonly supply one next signal to M (M is an integer greater than or equal to 1) dummy stage circuit units.

One next signal generating unit may be disposed for each of the four dummy stage circuit units.

The next signal generating unit generates a first next signal generating unit that supplies the first next signal in common to the dummy stage circuit units of the first group, and generates a second next signal to the dummy stage circuit unit of the second group located at the rear end of the first group. It may include a second next signal generator that is commonly supplied.

The present invention has the effect of realizing a narrow-bezel display device by discharging the node of the dummy stage circuit unit based on the next signal provided by itself inside the built-in gate driver without adding additional signal lines. In addition, since the present invention provides the next signal by the built-in gate driver without generating the next signal in the external circuit, cost reduction (CI) effect can be expected due to the reduction in the number of pins of the external circuit.

1 is a schematic block diagram of a display device;
FIG. 2 is an exemplary configuration diagram of the sub-pixel shown in FIG. 1;
3 is a first exemplary view of stage circuit units arranged in a display panel;
4 is a second exemplary view of stage circuit units arranged in a display panel;
5 is a layout view of stage circuit units for explaining a problem of a built-in gate driver according to an experimental example;
FIG. 6 is a waveform diagram for explaining the operation characteristics of the stage circuit units shown in FIG. 5;
7 is an exemplary arrangement diagram for explaining the concept of stage circuit parts according to the first embodiment of the present invention;
8 is a schematic circuit configuration diagram of a stage circuit unit;
9 is an exemplary arrangement view for explaining the concept of stage circuit parts according to the second embodiment of the present invention.
10 is a detailed circuit configuration diagram of stage circuit parts according to a third embodiment of the present invention.
11 is a waveform diagram for explaining the operational characteristics of stage circuit units according to a third embodiment of the present invention;
12 is a simulation result diagram of stage circuit units according to an experimental example;
13 is a simulation result diagram of stage circuit parts according to a third embodiment of the present invention;

Hereinafter, specific details for carrying out the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a schematic block diagram of a display device, and FIG. 2 is an exemplary configuration diagram of the sub-pixels shown in FIG. 1 .

1 , the display device includes a display panel 100 , a timing controller 110 , a data driver 120 , and built-in gate drivers 130 , 140L and 140R.

The display panel 100 includes sub-pixels separated and connected to the data lines DL and the scan lines GL that cross each other. The display panel 100 includes a display area AA in which sub-pixels are formed and a non-display area LNA and RNA in which various signal lines or pads are formed outside the display area AA. The display panel 100 may be implemented as a liquid crystal display (LCD), an organic light emitting display (OLED), an electrophoretic display (EPD), or the like.

As shown in FIG. 2 , one sub-pixel SP has a gate signal supplied through the switching transistor SW and the switching transistor SW connected to the first gate line GL1 and the first data line DL1 . A pixel circuit PC operating in response to the data signal DATA supplied in response to is included. The sub-pixel SP is implemented as a liquid crystal display panel including a liquid crystal element or an organic light emitting display panel including an organic light emitting element according to the configuration of the pixel circuit PC.

When the display panel 100 is composed of a liquid crystal display panel, it is a TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In Plane Switching) mode, FFS (Fringe Field Switching) mode, or ECB (Electrically Controlled Birefringence) mode. implemented in mode. When the display panel 100 is configured as an organic light emitting display panel, it is implemented in a top-emission method, a bottom-emission method, or a dual-emission method.

The timing controller 110 receives timing signals such as a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a dot clock through an LVDS or TMDS interface receiving circuit connected to the image board. The timing controller 110 generates timing control signals for controlling the operation timings of the data driver 120 and the built-in gate driver 130 , 140L and 140R based on the input timing signal.

The data driver 120 includes a plurality of source drive integrated circuits (ICs). The source drive ICs receive the data signal DATA and the source timing control signal DDC from the timing controller 110 . The source drive ICs convert the data signal DATA from a digital signal to an analog signal in response to the source timing control signal DDC, and supply it through the data lines DL of the display panel 100 . The source drive ICs may be connected to the data lines DL of the display panel 100 by a chip on glass (COG) process or a tape automated bonding (TAB) process, but is not limited thereto.

The built-in gate drivers 130 , 140L and 140R include a level shifter 130 and shift registers 140L and 140R. The level shifter 130 is formed on an external substrate connected to the display panel 100 in the form of an IC. The level shifter 130 shifts the level of a signal and power supplied through a clock signal line, a start signal line, a high potential power line, a low potential power line, etc. under the control of the timing controller 11, and then the shift register 140L , 140R).

The shift registers 140L and 140R are built-in and formed in the display panel 100 in a gate-in-panel (GIP) method. The shift registers 140L and 140R include stage circuit units formed in the form of thin film transistors in the non-display areas LNA and RNA of the display panel 100 . The stage circuit units are separately formed in the left non-display area LNA and the right non-display area RNA of the display panel 100 . A plurality of stage circuit units exist from the first stage circuit unit to the N-th (N is an integer greater than or equal to 10) stage circuit unit.

The above-described built-in gate driver implements the shift registers 140L and 140R using oxide or amorphous silicon thin film transistors. Oxide thin film transistors have an advantage in that the size of the circuit can be reduced compared to amorphous silicon thin film transistors because of excellent current movement characteristics. On the other hand, the amorphous silicon thin film transistor can maintain a constant threshold voltage even over time, and thus has a better recovery characteristic of the threshold voltage according to the stress bias compared to the oxide thin film transistor.

3 is a first exemplary diagram of stage circuit units arranged in the display panel, and FIG. 4 is a second exemplary view of stage circuit units arranged in the display panel.

As shown in FIG. 3 , the shift registers 140L and 140R are the stage circuit units GIPL1, GIPR1, GIPL2, GIPR2).

The method illustrated in FIG. 3 has a structure in which shift registers are disposed on both sides of the display area AA in order to reduce signal delay due to a line load of a gate line when a display device with a large area and high resolution is implemented.

The first left stage circuit part GIPL1 and the first right stage circuit part GIPR1 are disposed to face each other on the first gate line GL1 of the display panel 110 . The first gate line GL1 is provided by the operation of the first left stage circuit unit GIPL1 disposed in the left non-display area LNA and the first right stage circuit unit GIPR1 disposed in the right non-display area RNA. pass the gate signal.

The second left stage circuit part GIPL2 and the second right stage circuit part GIPR2 are disposed to face each other on the second gate line GL2 of the display panel 110 . The second gate line GL2 is provided by the operation of the second left stage circuit unit GIPL2 disposed in the left non-display area LNA and the second right stage circuit unit GIPR2 disposed in the right non-display area RNA. pass the gate signal.

As shown in FIG. 4 , the shift registers 140L and 140R are stage circuit units GIPL1 and GIPL2 for shifting and outputting a gate signal in response to a signal and power (eg, clk, vst, etc.) supplied from the level shifter. is composed of

In the method shown in FIG. 4, the output characteristic of the gate signal is somewhat reduced compared to the method shown in FIG. 3, but in order to reduce the area occupied by the circuit when implementing a narrow bezel, the shift register is placed on one side (left or right) of the display area AA. It is a structure placed only in

The first left stage circuit part GIPL1 is disposed on the first gate line GL1 of the display panel 110 . The first gate line GL1 transmits a gate signal prepared by the operation of the first left stage circuit unit GIPL1 disposed in the left non-display area LNA.

The second left stage circuit part GIPL2 is disposed on the second gate line GL2 of the display panel 110 . The second gate line GL2 transmits a gate signal prepared by the operation of the second left stage circuit unit GIPL2 disposed in the left non-display area LNA.

3 and 4 , it has been illustrated and described that the stage circuit units are disposed only on the first gate line GL1 and the second gate line GL2 to simplify the description. However, the stage circuits are arranged up to the last gate line.

On the other hand, the built-in gate driver configured as described above has the stage circuit parts connected to each other. In the dependent connection structure of the stage circuit units, after the gate signal of the previous stage circuit unit is output, the output end of the upper stage is connected to the input end of the lower stage so that the gate signal of the next stage circuit unit is output.

The stage circuit units having such a connection structure sequentially output gate signals as the shift registers configured therein operate sequentially (or in stages).

In addition, since the built-in gate driver has to discharge the Q node present in the shift registers to cause the gate signal of the gate high voltage to drop to the gate signal of the gate low voltage, the next stage signal is needed to implement this. .

However, in the case of the last shift register(s), since there is no next stage, a separate signal must be received from the outside. As a result, the built-in gate driver proposed in the related art and the following experimental examples uses a method of further forming a signal line in a non-display area of the display panel and transmitting a next signal (or a discharge signal) through the signal line.

Hereinafter, in order to help the understanding of the above-described problem, an explanation is added with reference to an experimental example as follows. However, hereinafter, a built-in gate driver operating based on a 10-phase clock signal to drive a 1080*1920 display panel is taken as an example.

FIG. 5 is a layout diagram of stage circuit units for explaining a problem of the built-in gate driver according to an experimental example, and FIG. 6 is a waveform diagram for explaining operation characteristics of the stage circuit units shown in FIG. 5 .

As shown in FIG. 5 , the built-in gate driver is disposed with a dependent connection relationship from the first stage circuit unit GIP0001 to the 1080th stage circuit unit GIP1080. The first stage circuit unit GIP0001 to the 1080th stage circuit unit GIP1080 sequentially output from the first gate signal Vgout0001 to the 1080th gate signal Vgout1080.

Since the 1071th stage circuit unit GIP1071 is connected to receive the 1079th gate signal Vgout1079 output from the 1079th stage circuit unit GIP1079, it can discharge its own Q node based on this.

Since the 1072th stage circuit unit GIP1072 is connected to receive the 1080th gate signal Vgout1080 output from the 1080th stage circuit unit GIP1080, it can discharge its own Q node based on this.

However, since the stage circuit part does not exist from the rear end of the 1072th stage circuit part GIP1072, a plurality of next signal lines VNEXT are formed in the non-display area of the display panel. And the Q node of the 1073th to 1080th stage circuit units GIP1073 to GIP1080 is configured to be discharged based on the next signal (or discharge signal) transmitted through the next signal line VNEXT.

The 1073 th to 1080th stage circuit units GIP1073 to GIP1080 correspond to a dummy stage circuit unit rather than a stage circuit unit for outputting a gate signal for driving the display area AA of the display panel. The dummy stage circuit unit is disposed in the non-display area NA like the stage circuit unit, but performs various roles different from that of the stage circuit unit, such as providing a signal capable of discharging the Q node of the previously arranged stage circuit unit.

As shown in FIG. 6, in the case of the N-th stage circuit unit, the Q node ( Q node[n]) is normally discharged.

However, the conventional and the methods proposed in the above experimental examples lead to an increase in the bezel size when additional signal lines need to be formed in the non-display area, such as an enlargement of a display panel or an increase in a clock signal. In addition, since the method proposed in the related art and the above experimental example requires generation of a next signal in an external circuit, it leads to an increase in the number of pins of the corresponding circuit.

Hereinafter, an embodiment for solving the above-described problem will be described, but a built-in gate driver operating based on a 10-phase clock signal to drive a 1080*1920 display panel is taken as an example.

However, the embodiments described below may be applied to a built-in gate driver for driving a display panel having a large line load of a gate line or a built-in gate driver operating based on a clock signal of 8 or more phases.

7 is an exemplary arrangement diagram for explaining the concept of stage circuit parts according to the first embodiment of the present invention, FIG. 8 is a schematic circuit configuration diagram of the stage circuit part, and FIG. 9 is a second embodiment of the present invention. It is an exemplary arrangement diagram for explaining the concept of stage circuit units.

As shown in FIG. 7 , the built-in gate driver is disposed with a dependent connection relationship from the first stage circuit unit GIP0001 to the 1080th stage circuit unit GIP1080. The first stage circuit unit GIP0001 to the 1080th stage circuit unit GIP1080 sequentially output from the first gate signal Vgout0001 to the 1080th gate signal Vgout1080.

The 1073 th to 1080th stage circuit units GIP1073 to GIP1080 correspond to a dummy stage circuit unit rather than a stage circuit unit for outputting a gate signal for driving the display area AA of the display panel. The dummy stage circuit unit is disposed in the non-display area NA like the stage circuit unit, but performs various roles different from that of the stage circuit unit, such as providing a signal capable of discharging the Q node of the previously arranged stage circuit unit.

As shown in FIG. 8 , each stage circuit unit includes output circuits TPU and TPD, a Q node charging circuit QC, and a QB node charging circuit QBC. The output circuits TPU and TPD are circuits for outputting the gate signal Vgout, and the Q node charging circuit QC and QB node charging circuit QBC are circuits for operating the output circuits TPU and TPD.

The output circuits TPU and TPD include a pull-up transistor TPU and a pull-down transistor TPD. When the Q node Q is in a charged state, the pull-up transistor TPU outputs a logic high gate signal (or gate high voltage). When the QB node QB is in a charged state, the pull-down transistor TPD outputs a logic low gate signal (or gate low voltage).

The output circuits TPU and TPD operate based on the signal and power transmitted through the clock signal line CLK and the low potential power line VSS. The Q node charging circuit (QC) and the QB node charging circuit (QBC) are connected to the signal transmitted through the high potential power line (VDD), the start signal line (VST) (or the output signal of the previous stage) and the next signal line (VNEXT) and It operates based on power.

The charging and discharging states of the Q node charging circuit QC and the QB node charging circuit QBC alternately occur. The Q node charging circuit QC and the QB node charging circuit QBC may be configured in various forms based on a transistor, which is schematically illustrated as a block.

7 and 9, the 1071th stage circuit unit (GIP1071) is connected to receive the 1079th gate signal (Vgout1079) output from the 1079th stage circuit unit (GIP1079). can be discharged.

Since the 1072th stage circuit unit GIP1072 is connected to receive the 1080th gate signal Vgout1080 output from the 1080th stage circuit unit GIP1080, it can discharge its own Q node based on this.

However, in the 1073th to 1080th stage circuit units GIP1073 to GIP1080, the Q node of each circuit unit is discharged in response to the operation of the next signal generating unit 145 separately formed in the non-display area of the display panel.

The next signal generator 145 operates based on a signal and power transmitted through at least one clock signal line CLK, a high potential power line VDD, and a low potential power line VSS. The next signal generator 145 provides a next signal (or discharge signal) capable of discharging the Q node of the stage circuit part that cannot receive a signal from the rear end, such as the 1073th to 1080th stage circuit parts (GIP1073 to GIP1080). .

The next signal generator 145 is formed in the non-display area NA of the display panel. The next signal generator 145 is disposed in an outer non-display area of the stage circuit unit(s) requiring a next signal or disposed in an inner non-display area.

The next signal generating unit 145 may be included in the stage circuit unit(s) requiring the next signal. In addition, the next signal generator 145 may be integrated into one circuit block as shown in FIG. 7 . In the case of FIG. 7 , the next signal generator 145 generates and outputs a next signal to be supplied to the 1073 th to 1080th stage circuit units GIP1073 to GIP1080.

The next signal generator 145 includes first and second transistors for outputting a logic high next signal in response to two clock signals having opposite phases, and a logic high next output from the first and second transistors. and a third transistor for resetting the signal to the next signal of logic low.

The first and second transistors have a period in which they are simultaneously turned on during the first period, and the third transistor has a period in which the first and second transistors are turned off during the first period and then are turned on (or immediately turned on period). The first section corresponds to a blank section in which an image of the display panel is not displayed.

In addition, the next signal generator 145 may be divided into two or M circuit blocks 145a and 145b (M is an integer greater than or equal to 2) as shown in FIG. 8 . The circuit blocks 145a and 145b divided into two or M pieces (M is an integer greater than or equal to 2) as shown in FIG. 8 have the same circuit configuration, but receive different clock signals and operate in response thereto.

In the case of FIG. 8 , the first next signal generator 145a corresponds to the first, third, and sixth clock signals transmitted through the first, third, and sixth clock signal lines CLK1, CLK3, and CLK6. Thus, a next signal to be supplied to the 1073 to 1076th stage circuit units (GIP1073 to GIP1076) is generated and output. In addition, the second next signal generator 145b is configured to correspond to the second, fourth, and seventh clock signals transmitted through the second, fourth, and seventh clock signal lines CLK2, CLK4, and CLK7. Generates and outputs the next signal to be supplied to the 1080 stage circuit units (GIP1077 ~ GIP1080).

As shown in FIG. 9 , when the built-in gate driver operates based on a 10-phase clock signal, the first and second next signal generators 145a and 145b are disposed one for each of the four dummy stage circuits. Accordingly, a plurality of next signal generating units are arranged to commonly supply one next signal to M (M is an integer greater than or equal to 1) dummy stage circuit units.

Hereinafter, a detailed circuit configuration will be described with an example in which the first and second next signal generators 145a and 145b are separated.

10 is a detailed circuit diagram of the stage circuit parts according to the third embodiment of the present invention, and FIG. 11 is a waveform diagram for explaining the operational characteristics of the stage circuit parts according to the third embodiment of the present invention.

As shown in FIG. 10 , the built-in gate driver is disposed with a dependent connection relationship from the first stage circuit unit GIP0001 to the 1080th stage circuit unit GIP1080. The first stage circuit unit GIP0001 to the 1080th stage circuit unit GIP1080 sequentially output from the first gate signal Vgout0001 to the 1080th gate signal Vgout1080.

The 1073 th to 1080th stage circuit units GIP1073 to GIP1080 correspond to a dummy stage circuit unit rather than a stage circuit unit for outputting a gate signal for driving the display area AA of the display panel. The dummy stage circuit unit is disposed in the non-display area NA like the stage circuit unit, but performs various roles different from that of the stage circuit unit, such as providing a signal capable of discharging the Q node of the previously arranged stage circuit unit.

Since the 1071th stage circuit unit GIP1071 is connected to receive the 1079th gate signal Vgout1079 output from the 1079th stage circuit unit GIP1079, it can discharge its own Q node based on this.

Since the 1072th stage circuit unit GIP1072 is connected to receive the 1080th gate signal Vgout1080 output from the 1080th stage circuit unit GIP1080, it can discharge its own Q node based on this.

However, in the 1073th to 1080th stage circuit units GIP1073 to GIP1080, the Q node of each circuit unit is discharged in response to the operation of the next signal generating unit 145 separately formed in the non-display area of the display panel.

10 and 11 , the first next signal generator 145a transmits the first, third, and third clock signal lines CLK1, CLK3, and CLK6 through the first, third, and sixth clock signal lines CLK1, CLK3, and CLK6. A first next signal to be supplied to the 1073 th to 1076th stage circuit units GIP1073 to GIP1076 is generated and output in response to the 6 clock signal. The 1073 th to 1076th stage circuit units GIP1073 to GIP1076 may be defined as a first group of dummy stage circuit units.

The first next signal generator 145a includes first to third transistors T1 to T3. The output terminal VNEXT1 of the first next signal generating unit 145a is commonly connected to the next signal lines of the 1073 th to 1076 th stage circuit units GIP1073 to GIP1076.

The first transistor T1 has a gate electrode connected to the first clock signal line CLK1 and a first electrode connected to the high power supply line VDD. The second transistor T2 has a gate electrode connected to the sixth clock signal line CLK6, a first electrode connected to the second electrode of the first transistor T1, and an output terminal of the first next signal generator 145a. The second electrode is connected to (VNEXT1). The third transistor T3 has a gate electrode connected to a third clock signal line CLK3, a first electrode connected to a low potential power line VSS, and an output terminal VNEXT1 of the first next signal generator 145a. The second electrode is connected to

The Q nodes of the 1073 to 1076th stage circuit units GIP1073 to GIP1076 are simultaneously discharged in response to the first next signal output from the first next signal generating unit 145a. The Q nodes of the 1073 th to 1076 th stage circuit units GIP1073 to GIP1076 are simultaneously discharged in response to the logic high first next signal during the blank period.

The second next signal generator 145b corresponds to second, fourth, and seventh clock signals transmitted through the second, fourth, and seventh clock signal lines CLK2, CLK4, and CLK7; A second next signal to be supplied to the stage circuit units GIP1077 to GIP1080 is generated and output. The 1077th to 1080th stage circuit units GIP1077 to GIP1080 may be defined as the dummy stage circuit unit of the second group positioned at the rear end of the dummy stage circuit unit of the first group.

The second next signal generator 145b includes fourth to sixth transistors T4 to T6. The output terminal VNEXT2 of the second next signal generator 145b is commonly connected to the next signal lines of the 1077th to 1080th stage circuit units GIP1077 to GIP1080.

The fourth transistor T4 has a gate electrode connected to the second clock signal line CLK2 and a first electrode connected to the high power supply line VDD. The fifth transistor T5 has a gate electrode connected to the fifth clock signal line CLK5, a first electrode connected to the second electrode of the fourth transistor T4, and an output terminal of the second next signal generator 145b. The second electrode is connected to (VNEXT2). The sixth transistor T6 has a gate electrode connected to the fourth clock signal line CLK4, a first electrode connected to a low potential power line VSS, and an output terminal VNEXT2 of the second next signal generator 145b. The second electrode is connected to

The Q nodes of the 1077th to 1080th stage circuit units GIP1077 to GIP1080 are simultaneously discharged in response to the second next signal output from the second next signal generating unit 145b. The Q nodes of the 1077th to 1080th stage circuit units GIP1077 to GIP1080 are simultaneously discharged in response to the logic high second next signal during the blank period.

As shown in FIGS. 10 and 11, the first and second next signal generators 145a and 145b generate two clock signals (eg, a first clock signal and a sixth clock signal or a second clock signal) having opposite phases. The next signal is generated based on the second clock signal and the seventh clock signal) and one reset clock signal (eg, the third clock signal or the fourth clock signal).

The first clock signal and the sixth clock signal should have opposite phases so as not to simultaneously become logic high during an image display period (display period) of the display panel. Only then, a logic high voltage is not applied to the next signal during the image display period.

However, the first clock signal and the sixth clock signal must have a logic high phase at the same time during a blank period (Blank period) of the display panel. Then, during the blank period (the blank period), the output terminal VNEXT1 of the first next signal generator 145a outputs the logic high first next signal charged by the high potential power source.

Therefore, the gate electrodes of the first and second transistors T1 and T2 have opposite phases during the image display period of the display panel and clock signals having the same phase during the blank period (the same time period). It is connected to the clock signal lines that transmit the clock signals that become logic high to .

In contrast, the gate electrode of the third transistor T3 is connected to a clock signal line that transmits a clock signal that rises to a logic high as opposed to a clock signal having the same phase falling to a logic low during a blank period.

Such operation characteristics are the same for not only the first next signal generator 145a but also the second next signal generator 145b. However, since the second next signal generator 145b must be output after a delay of a predetermined time from the first next signal, a clock that forms a logic high or logic low later than the clock signal used in the first next signal generator 145a It works based on signals.

Therefore, the clock signals for operating the first next signal generating unit 145a and the second next signal generating unit 145b may take the form shown in FIG. 11 or a form similar thereto, and are limited to the number determining the order of the clock signals. doesn't happen

In addition, although the third embodiment has been described with reference to the two next signal generators, the number may be increased to one or more depending on the number of clock signals or the size of the display panel. That is, the next signal generator may include at least one per one built-in gate driver.

On the other hand, in order to divide the phase (logic state) of clock signals into an image display section (Display section) and a blank section (Blank section) of the display panel, it is necessary to change the timing of the clock signal only during the blank section (Blank section). . In this case, the timing change of the clock signal may be performed by the timing controller, but is not limited thereto.

Hereinafter, an experimental example and simulation results using stage circuit units according to a third embodiment of the present invention will be described.

12 is a simulation result diagram of stage circuit parts according to an experimental example, and FIG. 13 is a simulation result diagram of stage circuit parts according to a third embodiment of the present invention.

12 is a simulation result diagram illustrating a case in which a next signal is not applied to stage circuit units according to an experimental example.

As shown in (a) of FIG. 12 , when the next signal is not applied to the stage circuit units, the Q node shows an abnormal output that does not fall from logic high to logic low. As a result, as shown in (b) of FIG. 12 , an abnormally large amount of output is displayed at the output terminals of the stage circuit units. The reason for such an abnormal output is that the discharge does not occur in the period or time when the discharge of the Q node should occur.

13 is a simulation result diagram illustrating a case in which a next signal is not applied to the stage circuit units according to the third embodiment of the present invention.

As shown in (a) of FIG. 13 , since the first and second next signals are applied to the stage circuit units, the Q node shows a normal output that falls from a logic high to a logic low. As a result, as shown in (b) of FIG. 13 , a normal output is displayed at the output terminals of the stage circuit units. The reason for such a normal output is that an appropriate discharge occurs in a period or time in which the discharge of the Q node should occur due to the operation of the first and second next signal generators.

As described above, the present invention has the effect of realizing a narrow-bezel display device by discharging a node of the dummy stage circuit unit based on the next signal provided by itself inside the built-in gate driver without adding additional signal lines. In addition, since the present invention provides the next signal by the built-in gate driver itself without generating the next signal in the external circuit, a cost reduction (CI) effect can be expected due to the reduction in the number of pins of the external circuit.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the technical configuration of the present invention can be changed to other specific forms by those skilled in the art to which the present invention pertains without changing the technical spirit or essential features of the present invention. It will be appreciated that this may be practiced. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. In addition, the scope of the present invention is indicated by the claims to be described later rather than the above detailed description. In addition, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention.

100: display panel 110: timing control unit
120: data driver 130, 140L, 140R: built-in gate driver
145: next signal generator T1 to T6: first to sixth transistors
VDD: high potential power line VSS: low potential power line
CLK: clock signal line VNEXT1, VNEXT2: output terminal
AA: display region LNA, RNA, NA: non-display region

Claims (10)

a display panel for displaying an image; and
and a built-in gate driver including shift registers having stage circuit parts cascadedly connected to supply a gate signal to the display panel and a next signal generator providing a next signal to at least one of the stage circuit parts;
The next signal generating unit generates the next signal based on at least one clock signal, high potential power and low potential power;
The next signal generator
first and second transistors for outputting a logic high next signal in response to two clock signals;
a third transistor for resetting the next signal of logic high output from the first and second transistors to the next signal of logic low;
The two clock signals have opposite phases during an image display period in which an image is displayed, and have the same phase during a blank period in which an image is not displayed. According to claim 1,
The next signal generator
A display device disposed adjacent to the at least one stage circuit unit. According to claim 1,
The next signal generator
a display device disposed in a non-display area of the display panel together with the stage circuit parts. According to claim 1,
The next signal generator
and providing the next signal to a dummy stage circuit part that does not output a gate signal to a display area of the display panel among the stage circuit parts. delete According to claim 1,
The first and second transistors have a section in which they are turned on at the same time during a blank section in which an image of the display panel is not displayed,
The display device having a period in which the third transistor is turned on after the first and second transistors are turned off during the blank period. According to claim 1,
The first transistor has a gate electrode connected to a first clock signal line and a first electrode connected to a high power supply line,
The second transistor has a gate electrode connected to a sixth clock signal line, a first electrode connected to a second electrode of the first transistor, and a second electrode connected to an output terminal of the next signal generator,
In the third transistor, a gate electrode is connected to a third clock signal line, a first electrode is connected to a low potential power line, and a second electrode is connected to an output terminal of the next signal generator. According to claim 1,
The next signal generator
A display device arranged in plurality so as to supply one next signal in common to M (M is an integer greater than or equal to 1) dummy stage circuit units. 9. The method of claim 8,
The next signal generator
A display device arranged one for each of the four dummy stage circuit units. According to claim 1,
The next signal generator
a first next signal generating unit for supplying a first next signal in common to the first group of dummy stage circuit units;
and a second next signal generator for supplying a second next signal in common to a dummy stage circuit portion of a second group located at a rear end of the first group.

Images