KR102254503B1 - Liquid crystal display - Google Patents

Abstract

The present invention provides a substrate, a gate wiring and a data wiring crossing each other on the substrate to define a pixel region, a common wiring adjacent to the gate wiring, a thin film transistor disposed at the intersection of the gate wiring and the data wiring, A liquid crystal display device including a first electrode electrically connected to an electrode, a second electrode connected to a common wire, and a first pattern electrically connected to the common wire and partially or entirely overlapped with the first electrode.

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY}

The present invention relates to a liquid crystal display device that displays an image.

Liquid crystal display technology continues to develop and is replacing the existing fixed-type display market using CRT (Cathode-Ray Tube), and the display device for laptops, computer monitors, TVs, etc. are gradually becoming larger and DID (Digital Information Display). ) Or PID (Public Information Display) market.

The liquid crystal display device has a problem in that the aperture ratio decreases as the resolution gradually increases.

An object of the present invention is to provide a liquid crystal display device that improves the aperture ratio since the area of the light emitting area of the display device can be wide.

In order to achieve the above object, in one aspect, the present invention provides a gate wiring and a data wiring crossing each other on a substrate to define a pixel region, a common wiring adjacent to the gate wiring, and the intersection of the gate wiring and the data wiring. A liquid crystal display including an arranged thin film transistor, a first electrode electrically connected to one electrode of the thin film transistor, a second electrode connected to a common wire, and a first pattern extending from the common wire and partially or entirely overlapping the first electrode Provide the device.

The liquid crystal display according to the exemplary embodiment of the present invention has an effect of improving the aperture ratio since the area of the light emitting area can be wide.

1 is a system configuration diagram of a liquid crystal display to which embodiments are applied.
2 is a plan view of each pixel area P of a liquid crystal display according to an exemplary embodiment.
3 is a partially enlarged view of FIG. 2.
4 is a cross-sectional view taken along line A-A' of FIG. 3.
5A to 5C are process plan views sequentially illustrating a method of manufacturing a liquid crystal display according to an exemplary embodiment.
6 is a plan view of each pixel area P of a liquid crystal display according to another exemplary embodiment.
7 is a partially enlarged view of FIG. 6.
8 is a cross-sectional view taken along line B-B' of FIG. 7.
9 is a diagram comparing the aperture ratios of each pixel area of a display device according to an exemplary embodiment and each pixel area of a display device according to another exemplary embodiment.
10 is a graph comparing an increase in the aperture ratio (%) of each pixel area of a display device according to an exemplary embodiment and each pixel area of a display device according to another exemplary embodiment.

Hereinafter, some embodiments of the present invention will be described in detail through exemplary drawings. In adding reference numerals to elements of each drawing, it should be noted that the same elements are assigned the same numerals as possible, even if they are indicated on different drawings. In addition, in describing the embodiments of the present invention, when it is determined that a detailed description of a related known configuration or function may obscure the subject matter of the present invention, a detailed description thereof will be omitted.

In addition, in describing the constituent elements of the invention, terms such as first, second, A, B, (a) and (b) may be used. These terms are for distinguishing the constituent element from other constituent elements, and the nature, order, or order of the constituent element is not limited by the term. When a component is described as being "connected", "coupled" or "connected" to another component, the component may be directly connected or connected to that other component, but another component between each component It will be understood that elements may be “connected”, “coupled” or “connected”. In the same context, when it is described that a component is formed "above" or "below" another component, the component is all formed directly on the other component or indirectly through another component. It should be understood as including.

1 is a system configuration diagram of a liquid crystal display device to which embodiments are applied.

Referring to FIG. 1, a liquid crystal display device 100 includes a liquid crystal display panel 140, a data driver 120, a gate driver 130, a timing controller 110, and the like.

First, the timing controller 110 controls the data driver 120 based on external timing signals such as vertical/horizontal synchronization signals (Vsync, Hsync) input from the host system, image data, and clock signals CLK. A data control signal DCS for controlling the gate driver 130 and a gate control signal GCS for controlling the gate driver 130 are output. In addition, the timing controller 110 converts image data input from the host system into a data signal format used by the data driver 120 and supplies the converted image data data' to the data driver 120. have.

In response to the data control signal DCS input from the timing controller 110 and the converted image data data', the data driver 120 converts the image data data' into a data signal that is a voltage value corresponding to the grayscale value. It is converted into an analog pixel signal or data voltage) and supplied to the data line.

The gate driver 130 sequentially supplies a scan signal (a gate pulse or a scan pulse, a gate on signal) to the gate line in response to the gate control signal GCS input from the timing controller 110.

Meanwhile, the liquid crystal display panel 140 may be a display panel including two substrates, a liquid crystal layer, an alignment layer, and the like positioned between the two substrates.

In addition, the first substrate (lower substrate) of the liquid crystal display panel 140 includes a plurality of data lines (D1 to Dm, m is a natural number), and a plurality of gate lines (or scans) intersecting the data lines D1 to Dm. Lines) (G1 to Gn, n is a natural number), a plurality of pixel regions P may be disposed at intersections between the data lines D1 to Dm and the gate lines G1 to Gn.

Meanwhile, the pixel regions P of the liquid crystal display panel 140 are formed in the pixel regions defined by the data lines D1 to Dm and the gate lines G1 to Gn and are arranged in a matrix form. The liquid crystal cells of each of the pixel regions include a transistor, a pixel electrode for charging a data voltage, a common electrode for forming an electric field with the pixel electrode, a storage capacitor connected to the pixel electrode to maintain the voltage of the liquid crystal cell, etc. Can include. The liquid crystal cells of each of the pixel regions are driven by an electric field applied according to a voltage difference between the data voltage applied to the pixel electrode and the common voltage applied to the common electrode to control the transmission amount of incident light.

Meanwhile, the second substrate (upper substrate) of the liquid crystal display panel 140 may include a light blocking layer (eg, a black matrix), a color filter, and the like. The first substrate of the liquid crystal display panel 140 may be implemented in a color filter on TFT (COT) structure. In this case, the light blocking layer and the color filter may be formed on the first substrate.

2 is a plan view of each pixel area P of a liquid crystal display according to an exemplary embodiment. 3 is a partially enlarged view of FIG. 2. 4 is a cross-sectional view taken along line A-A' of FIG. 3.

Referring to FIGS. 2 to 4, one pixel region P1 of the liquid crystal display 100 crosses each other on a substrate 210 to define a pixel region, a gate wire 212 and a data wire 214, The gate electrode 216a, the source electrode 216b, and the drain electrode 216c are at the intersection of the common wiring 213 and the gate wiring 212 and the data wiring 214 passing through the pixel region and adjacent to the gate wiring 212. ) And a thin film transistor Tr.

The gate wiring 212 extends in the first direction and is connected to the gate pad 212a. The data line 214 may have a bent structure. The data line 214 extends in the second direction and is connected to the data pad 214a.

In this case, the common wiring 213 may be formed adjacent to the upper or lower side of the gate wiring 212, and may be substantially parallel to the gate wiring 212, but is not limited thereto.

The thin film transistor Tr includes a gate electrode 216a protruding from the gate wiring 212, a source electrode 216b protruding from the data wiring 214 and formed in a "U" shape on the gate electrode 216a, and And a drain electrode 216c that is spaced apart from the source electrode 216b and partially enters the “U”-shaped pattern of the source electrode 216b. At this time, a semiconductor layer (not shown) in which a channel is defined is interposed between the layer of the gate electrode 216a and the layer of the source/drain electrodes 216b and 216c. At this time, the roles of the source electrode 216b and the drain electrode 216c in the thin film transistor Tr may be reversed depending on whether the semiconductor layer of the thin film transistor Tr is a P-type or an N-type.

The source electrode 216b is connected to the data line 214 by the source connection pattern 217. The source connection pattern 217 may include two patterns 217a and 217b positioned on both sides of the gate wiring 212 so as not to overlap with the gate wiring 212.

One pixel region P1 of the liquid crystal display 100 is branched from the first electrode 218 electrically connected to the drain electrode 216c in the pixel region and the common wiring 213 in the pixel region to form the first electrode 218. ) And a second electrode 220 formed by alternating with each other.

The data voltage is supplied to the first electrode 218 through the data line 212. The second electrode 220 is supplied with a reference voltage for driving the liquid crystal, that is, a common voltage through the common wiring 214. Accordingly, an electric field is formed between the first electrode 218 supplied with the data voltage (pixel voltage signal) and the second electrode 220 supplied with the common voltage. In addition, the light transmittance that transmits through the pixel region P1 varies according to the degree of rotation of the liquid crystal molecules, thereby implementing an image.

In this case, the first electrode 218 may be a pixel electrode and the second electrode 220 may be a common electrode. The first electrode 218 has a structure in which two or more branches 218a and 218b are bent, and the second electrode 220 has a structure in which two or more branches 220a and 220b are bent, so that liquid crystal molecules are arranged in two directions. By forming a 2-domain (domain) the viewing angle is further improved compared to the mono-domain. However, the first electrode 218 and the second electrode 220 are not limited to a 2-domain structure, and may have a multi-domain structure of a 2-domain or more, and may not have a bent structure. The first electrode 218 and the second electrode 220 may be positioned on the same plane.

The first electrode 218 is electrically connected to the second pattern 221 extending from the drain electrode 216c through a contact hole (not shown). The second pattern 221 overlaps with the common wiring 213 in whole or in part. Accordingly, the second pattern 221 and the common line 213 function as a first storage capacitor that maintains the data voltage supplied through the data line 212 until the next frame.

A first pattern 222 extending from the common wiring 213 is formed. The first pattern 222 is formed on the same plane as the common wiring 213 and the gate wiring 214. The first pattern 222 is formed on a plane different from the first electrode 213, an upper plane, or a lower plane. As shown in FIG. 4, the first pattern 222 may be positioned under the first electrode 218. An insulating layer 223 or a dielectric is positioned between the first pattern 222 and the first electrode 218.

The first pattern 222 has two or more branches 222a, 222b, and 222c. Meanwhile, one branch 222c of the first pattern 222 is electrically connected to the second electrode connection pattern 224 of the second electrode 220 through a contact hole (not shown).

At least one of the branches 222a, 222b, and 222c of the first pattern 222 is positioned between the branches 220a and 220b of the second electrode 220, respectively. At this time, the branches 222a and 222b of the first pattern 222 may overlap with one of the branches 218a and 218b of the first electrode 218, respectively, but are not limited thereto. The number of the branches 222a and 222b of the first pattern 222 and the branches 218a and 218b of the first electrode 218 may be the same, and both branches may partially or all overlap one-to-one.

Meanwhile, the branches 222a and 222b of the first pattern 222 may not overlap one of the branches 218a and 218b of the first electrode 218, respectively. For example, even though the branches 222a and 222b of the first pattern 222 do not overlap one of the branches 218a and 218b of the first electrode 218, respectively, the branches 218a of the first electrode 218 , 218b) is short, the dielectric constant of the first pattern 222 and the first electrode 218 is large, or the width of the first pattern and the first electrode is wide so that it can function as a storage capacitor.

Accordingly, the first pattern 222 and the first electrode 218 function as a second storage capacitor that maintains the data voltage supplied through the data line 214 until the next frame.

Therefore, the second pattern 221 and the common wiring 213 function as a first storage capacitor, and the first pattern 222 and the first electrode 218 function as a second storage capacitor, The supplied data voltage can be maintained until the next frame. In the above example, it has been described that the second pattern 221 extending from the drain electrode 216c and overlapping all or part of the common wiring 213 functions as the common wiring 213 and the first storage capacitor. The storage capacitor 221 may not be substantially present and only the first pattern 222 and the first electrode 213 may be formed.

Here, the gate wiring 212 including the gate electrode 216a for each pixel region P1, the gate pad 212a formed on one side extending from the gate wiring 212, the common wiring 213, and the common wiring 213 The first patterns 222 extending from) are all formed on the same plane or on the same layer, but are not limited thereto.

In addition, the data line 214, the source/drain electrodes 216b and 216c, the second pattern 221 extending from the drain electrode 216c, and the data pad 214a formed on one side extending from the data line 214 All are formed on the same plane or on the same layer, but are not limited thereto.

In addition, the first electrode 218 and the second electrode 220 formed by alternating with the first electrode 218 are all formed on the same plane or on the same layer, but are not limited thereto.

As described above, it has been described that the first pattern 222 is formed on the same plane or on the same layer as the gate wiring 212 and the common wiring 213, but the first pattern 222 includes the data wiring 214 and the data pad. 214a) and the like may be formed on the same plane or on the same layer. At this time, since the first pattern 222 and the common wiring 213 are located on different layers, they may be electrically connected through a contact hole.

Although not shown in FIGS. 1 to 4, components located on different planes or on different layers and connected to each other are electrically connected to each other through a contact hole. Meanwhile, one or two or more layers having an insulating function, such as the insulating layer 223 illustrated in FIG. 4, may be positioned between different layers.

Hereinafter, a method of manufacturing a liquid crystal display according to an exemplary embodiment will be described with reference to FIGS. 5A to 5C.

5A to 5C are process plan views sequentially illustrating a method of manufacturing a liquid crystal display device according to an exemplary embodiment.

In a method of manufacturing a liquid crystal display according to an embodiment, first, as shown in FIG. 5A, by depositing a first metal on a substrate and selectively removing the first metal using a first mask (not shown), a plurality of A gate wiring 212 having a gate electrode 216a and a gate pad 212a on one extended side, a common wiring 213 adjacent to the gate wiring 212, and two or more branches extending from the common wiring 213 A first pattern 222 including (222a, 222b, 222c) is formed. At this time, two or more branches 222a, 222b, and 222c of the first pattern 222 have a bent structure when they are parallel to each other.

Thereafter, a gate insulating film (not shown) is formed on the entire surface of the substrate.

As shown in FIG. 5B, a second metal is deposited on the gate insulating layer, and data including a “U”-shaped source electrode 216b and a data pad 214a extending on one side thereof using a second mask (not shown) The wiring 214, the drain electrode 216c spaced apart from the source electrode 216b by a predetermined distance, the second pattern 221 connected to the drain electrode 216c, the source connecting the source electrode 216b and the data line 214 A connection pattern 217 is formed.

As described above, in the etching process using the second mask, the channel is formed when the source electrode 216b and the drain electrode 216c are formed after forming the semiconductor layer formed on the gate insulating layer and depositing the second metal on the semiconductor layer. A defined semiconductor layer (not shown) can be formed at the same time.

Alternatively, a semiconductor layer may be formed on the gate insulating layer at a position corresponding to the gate electrode by using an additional mask process, and the source electrode 216b and the drain electrode 216c may be formed by using an etching process using the second mask. .

Here, the data wiring 214 has a bent structure. The source connection pattern 217 includes two patterns 217a and 217b positioned on both sides of the gate wiring 212 so as not to overlap with the gate wiring 212.

5C, a first electrode 218 including two or more branches 218a and 218b alternating with each other by depositing a transparent conductive film (ITO) on the substrate and using a third mask (not shown), and A second electrode 220 including two or more branches 220a and 220b and a connection pattern 224 are formed.

Although not shown, a black matrix layer is formed on another substrate opposite to the substrate to cover portions of the gate wiring 212, the data wiring 214, and the thin film transistor Tr. In this case, R, G, and B color filter layers may be formed on or on another substrate corresponding to each pixel.

Subsequently, an alignment layer is formed on a substrate different from the substrate on which the TFT array process and the color filter array process have been completed, and then rubbing the same.

In this way, after distributing a spacer on any one of the two substrates in which the respective formation process has been made, dispensing a sealing material on a portion corresponding to the outer side, bonding the two substrates, and then cutting the spacer into a single panel unit. . Then, liquid crystal is injected into each panel to form a liquid crystal panel. Next, the liquid crystal display device 100 is completed by connecting the data driver 120, the gate driver 130, the timing controller 110, and a backlight (not shown) shown in FIG. 1 to the liquid crystal panel.

6 is a plan view of each pixel area P2 of a liquid crystal display according to another exemplary embodiment. 7 is a partially enlarged view of FIG. 6. 8 is a cross-sectional view taken along line B-B' of FIG. 7.

6 to 8, one pixel region P2 of the liquid crystal display 100 crosses each other on a substrate 610 to define a pixel region, and a gate wire 612 having a bent structure and a data wire 614 having a bent structure. ), a common wiring 613 adjacent to the gate wiring 612 passing through the pixel region, and a gate electrode 616a at the intersection of the gate wiring 612 and the data wiring 614, and a "U"-shaped source electrode 616b and a drain electrode 616c partially entering the "U"-shaped pattern of the source electrode 616b, and a thin film transistor Tr made of a semiconductor layer (not shown) in which a channel is defined.

The gate wiring 612 extends in the first direction and is connected to the gate pad 612a. The data line 614 extends in the second direction and is connected to the data pad 614a.

The source electrode 616b is connected to the data line 614 by a source connection pattern 617. The source connection pattern 617 includes two patterns 617a and 617b positioned on both sides of the gate line 612 so as not to overlap with the gate line 612.

One pixel region P2 of the liquid crystal display 100 extends from the drain electrode 616c in the pixel region and includes a first electrode 618 and a pixel region including two or more branches 618a and 618b having a bent structure. And a second electrode 620 having two or more branches 620a and 620b branched from the common wiring 613 and having a bent structure therein.

The first electrode 618 is electrically connected to the second pattern 621 extending from the drain electrode 616c through a contact hole (not shown). The second pattern 621 overlaps with the common wiring 613 in whole or in part. Accordingly, the second pattern 621 and the common wiring 613 function as a storage capacitor that maintains the data voltage supplied through the data line 612 until the next frame.

Each pixel area P1 of the display device according to the exemplary embodiment described with reference to FIGS. 2 to 4 includes a first pattern 222 extending from a common wiring 213, and as shown in FIG. Although the first pattern 222 and the first electrode 218 function as a storage capacitor, each pixel area P2 of the display device according to another exemplary embodiment described with reference to FIGS. 6 to 8 does not include the first pattern.

9 is a diagram comparing the aperture ratios of each pixel area P1 of the display device according to an exemplary embodiment and each pixel area P2 of the display device according to another exemplary embodiment.

Referring to FIG. 9, a width W2 of a common wiring 613 of each pixel area P2 of a display device according to another exemplary embodiment is of a common wiring of each pixel area P1 of the display device according to an exemplary embodiment. It is larger than the width W1. Also, the width W4 of the second pattern 621 of each pixel area P2 of the display device according to another exemplary embodiment is also the second pattern 221 of each pixel area P1 of the display device according to the exemplary embodiment. Is greater than the width (W3). As a result, as a storage capacitor of the common wiring 613 and the second pattern 621, the capacitance is the capacitance of the first storage capacitor of the first pattern 222 and the first electrode 218 and the common wiring 213 according to an embodiment. ) And the width W2 of the common wiring 613 and the width W4 of the second pattern 621 are substantially equal to the capacitance of the second storage capacitor of the second pattern 221.

10 is a graph comparing an increase in an aperture ratio per inch (%) between a display device according to an exemplary embodiment and a display device according to another exemplary embodiment.

As described above, the display device according to an exemplary embodiment functions as a storage capacitor with the first pattern 222 and the first electrode 218, so even if the widths of the common wiring 213 and the second pattern 221 are made small, The data voltage can be maintained until the next frame. Accordingly, the width W1 of the common wiring 213 and the width W3 of the second pattern 221 are smaller than the width W2 of the common wiring 613 and the width W4 of the second pattern 621. As a result, the display device according to the exemplary embodiment reduces the width W1 of the common wiring 213 and the width W3 of the second pattern 221 to narrow the non-emission area, Since the one electrode 218 functions as a storage capacitor, the data voltage can be sufficiently maintained until the next frame.

Accordingly, the display device according to the exemplary embodiment can have a wider area of the light emitting area compared to the display device according to the other exemplary embodiment, thereby improving the aperture ratio.

In particular, in the display device according to an embodiment, the aperture ratio per inch is increased even when the resolution is not only FHD but also UHD, compared to the display device according to another embodiment.

The embodiments have been described above with reference to the drawings, but the present invention is not limited thereto.

The terms such as "include", "consist of" or "have" described above mean that the corresponding component may be embedded, unless otherwise specified, and thus other components are not excluded. It should be construed as being able to further include other components. All terms, including technical or scientific terms, unless otherwise defined, have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. Terms generally used, such as terms defined in the dictionary, should be interpreted as being consistent with the meaning in the context of the related technology, and are not interpreted as ideal or excessively formal meanings unless explicitly defined in the present invention.

The above description is merely illustrative of the technical idea of the present invention, and those of ordinary skill in the art to which the present invention pertains will be able to make various modifications and variations without departing from the essential characteristics of the present invention. Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but to explain the technical idea, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

100: liquid crystal display 110: timing controller
120: data driver 130: gate driver
140: liquid crystal display panel 213: common wiring
216c: drain electrode 218: first electrode
221: second pattern 222: first pattern

Claims (6)

A thin film transistor disposed in the first pixel region on the substrate and disposed at an intersection of a gate line disposed in a row direction and a data line disposed in a column direction;
A common wiring adjacent to the gate wiring;
A first electrode disposed in a light emitting area within the first pixel area and electrically connected to one electrode of the thin film transistor;
A second electrode disposed in the emission region and connected to the common wiring; And
A first pattern electrically connected to the common wiring, extending from the common wiring adjacent to the gate wiring to the emission region, and partially or entirely overlapping with the first electrode in the emission region,
Further comprising a second pattern extending from the one electrode of the thin film transistor and electrically connected to the first electrode,
The first electrode is a pixel electrode of the first pixel region electrically connected to the one electrode of the thin film transistor through the second pattern,
The common wiring, the second electrode, and the first pattern are electrically connected to each other to form a common electrode, and among the common wiring, the second electrode, and the first pattern constituting the common electrode, the second An electrode is disposed on the same layer as the first electrode, which is the pixel electrode, the common wiring and the first pattern are disposed on a different layer from the first electrode and disposed on the same layer as the gate wiring,
The first pattern overlaps with the first electrode in the emission region, and the second pattern overlaps with the common wiring in a non-emission region other than the emission region in the first pixel region,
The common wiring, the second electrode, and the first pattern constituting the common electrode form the first electrode, which is the pixel electrode, and a storage capacitor in the first pixel region,
The storage capacitor of the first pixel area includes a first storage capacitor formed by the first pattern and the first electrode overlapping in the emission area, and the second pattern and the common wiring overlapping in the non-emission area. Including a second storage capacitor formed by,
The first pattern includes a plurality of branches extending from the common wiring, and both branches of the plurality of branches included in the first pattern are disposed adjacent to and parallel to the data wiring, and the first electrode and Is not overlapped, and the remaining branches except for the branches on both sides of the plurality of branches included in the first pattern overlap the first electrode in the emission region,
The second electrode includes a second electrode connection pattern and a plurality of branches connected to the second electrode connection pattern, and a portion of the second electrode connection pattern is disposed parallel to the data line, and the data line and the column direction are Overlaps with,
The common wiring is disposed adjacent to the thin film transistor in the first pixel region, and the thin film transistor is positioned in the first pixel region in a portion where the plurality of branches of the second electrode are connected in the second electrode connection pattern. A liquid crystal display device located on the opposite side of the screen. delete delete The method of claim 1,
The first electrode includes a plurality of branches alternating with a plurality of branches included in the second electrode, and at least one of the plurality of branches included in the first pattern is attached to the first electrode in the light emitting area. A liquid crystal display device overlapping at least one of a plurality of included branches. The method of claim 4,
The liquid crystal display device, wherein the number of the branches of the first pattern overlapping and the branches of the first electrode are the same. delete

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