KR102094551B1 - Resistance-change memory device and method of operating the same - Google Patents

Abstract

A memory element that is connected between the bit line, the voltage supply layer, and the bit line and the voltage supply layer, and whose resistance value changes in response to an applied voltage, and a first current flows through the bit line, and thereafter, the first current And a drive control circuit for controlling a lower resistance, which causes the memory element to transition from a high resistance state to a low resistance state with the second current by passing a smaller second current through the bit line. The device is started.

Description

Resistorance-changing memory device and its operating method {RESISTANCE-CHANGE MEMORY DEVICE AND METHOD OF OPERATING THE SAME}

The present invention relates to a resistance change type memory device that connects a memory element whose resistance value changes according to an applied voltage between a bit line and a voltage supply layer called a source line or plate, and an operation method thereof.

A resistance-changeable memory device having a memory element whose resistance value changes for each memory cell by implanting conductive ions into the insulating film or by drawing out conductive ions from the insulating film is known (for example, " A Novel Resistance Memory with High Scalability and Nanosecond Switching "K. Aratani, K. Ohba, T. Mizuguchi, S. Yasuda, T. Shiimoto, T. Tsushima, T. Sone, K. Endo, A. Kouchiyama, S. Sasaki , A. Maesaka, N. Yamada, and H. Narisawa, Technical Digest IEDM 2007, pp. 783-786. (Hereinafter referred to as Non-Patent Document 1)).

The memory element has a stacked structure formed of a supply layer of the conductive ions and an insulating film between two electrodes. The memory cell is configured by connecting a storage element and an access transistor in series between a bit line and a plate to enable active matrix driving.

Since such a memory cell has one transistor T and one (variable) resistor R, it is a type of 1T1R type current-driven memory. The memory using the conductive ions is widely referred to as ReRAM in general, along with a memory using oxidation and reduction of an insulating layer.

In ReRAM, the size of the resistance value is corresponded to the writing and erasing of data, so that a write or erase operation is possible with a short duration pulse of nanosecond size. Therefore, ReRAM has attracted attention as a nonvolatile memory (NVM) capable of high-speed operation at a random access memory (RAM) level.

Fig. 1 shows a correlation diagram of conductance and current in a low resistance state of a memory (ReRAM) using conductive ions.

The horizontal axis in Fig. 1 represents the reciprocal (conductance) of the resistance value RLRS in the low resistance state LRS. In addition, the vertical axis in FIG. 1 represents the value of the set current Iset in the low-resistance operation (herein referred to as a set operation).

As is apparent from Fig. 1, the resistance value of the storage element changes almost linearly in response to the set current. Such characteristics can be realized in other resistance-change-type memories such as ReRAM.

As described above, ReRAM has the advantage of narrowing the resistance value distribution or realizing a multi-value memory by precisely controlling the current.

On the other hand, however, if the precision of current control is low, it is difficult to obtain a desired resistance value, and particularly, the application of excessive current makes it difficult to perform a high-resistance (reset) operation, or the disadvantage that repetitive characteristics are lowered. I also have it.

As a method of controlling the element current, a method of regulating the element current by gate potential control (word line control) of the access transistor and a method of controlling the current of the bit line are known.

Of these, the word line is formed of a gate metal, and since a large gate capacitance is included as a large number of parasitic capacitances, the wiring capacity is large and difficult to control, so high-speed driving is difficult. In addition, when trying to operate at high speed, since it is necessary to increase the driving force of the word line control circuit, there is a fear that the circuit area increases and costs increase.

On the other hand, since the bit line is formed in the upper wiring layer, and the wiring capacity is relatively small, so that it is easy to control, high-speed operation is possible in the current control method using the bit line. In addition, the current control of the bit line can suppress the circuit area, and it is possible to reduce the cost in this regard. Therefore, it is possible to achieve both low cost and high speed by adopting the current control method of the bit line.

In the method of regulating the element current by controlling the current of the bit line, it is necessary to separate the source line in addition to the bit line and word line in the row direction so that potential driving is possible. In that sense, the method (or access method) to which the current control method is applied is referred to as a three-wire system.

With regard to the current control of the bit line in the 3-wire system, the inventor of the present application has already made several proposals (for example, see Japanese Unexamined Patent Publication No. 2010-170617). In addition, an example in which this current control method is applied to a resistive change type memory of a spin injection method is disclosed in, for example, Japanese Patent Publication No. WO2007 / 015358.

Further, Non-Patent Document 1 has an array configuration in which the upper electrode is machined in a plate shape for ease of processing, the drain of the access transistor is a storage node, and the source is connected to a bit line machined in a line shape. It is a method (two-wire type) in which one memory cell is selected by two lines of a bit line and a word line.

In the method of performing current control described in JP 2010-170617 A, for example, the drain of the current control transistor (NMOS transistor) is connected to the bit line, and the gate voltage is controlled by the control circuit. In this control, after the inversion of the storage element to the low resistance state, the control circuit controls the current control transistor, thereby operating the access transistor in the saturation region, and controlling the bit line potential so that the element current becomes constant. do. For this reason, even if the resistance value of the storage element changes, or even if there is a variation in the storage element, the set current (element current after inversion) becomes constant, and since excessive current does not flow, deterioration of the element characteristics is effectively prevented. Or is suppressed.

However, as in the non-patent document 1, since the current control of the plate is not possible in a two-wire type memory that emphasizes ease of processability, application of the current control method to the bit line is essential. In addition, in the case of a 3-wire type having source lines separated for each row of memory cells instead of plates, there is a case where a current control method is applied to the bit lines for some reason.

By this current control method, it is possible to suppress variations in resistance distribution after a change in resistance. In addition, this system has an advantage that the driving area may be lower than that of the word line control system, so that the total area of the control circuit is small, and therefore, it is low cost.

More specifically, in the low-resistance operation of the storage element, in the state where the plate or source line is fixed at a constant potential, the potential of the bit line is changed from the constant potential, and voltage is applied to flow the device current to the storage element.

However, since the current of the bit line is regulated to prevent excessive application of current to the storage element, it is impossible to change the bit line potential abruptly. For this reason, since the wiring capacity of the bit line is smaller than that of the word line, it is not possible to sufficiently increase the operating speed that can be naturally high-speed.

The present invention discloses a resistance-changeable memory device that starts a low-resistance operation by changing the potential of a bit line and performs current control of the bit line, and a technique for further improving high-speed in the operation method.

The resistance changeable memory device according to the present invention has a bit line, a voltage supply layer, a memory element, and a drive control circuit.

The memory element is connected between the bit line and the voltage supply layer, and the resistance value changes in response to the applied voltage.

The drive control circuit flows a first current through the bit line, and then flows a second current smaller than the first current through the bit line, and transitions the memory element from a high resistance state to a low resistance state. Resistance is controlled by the second current.

The operation method of the resistance change type memory device according to the present invention is a low resistance which is connected between a bit line and a voltage supply layer, and changes a memory element whose resistance value changes in response to an applied voltage from a high resistance state to a low resistance state. Around this time, a first current is passed through the bit line, and a second current smaller than the first current is passed through the bit line, thereby controlling the resistance reduction of the memory element.

According to the above structure, in the initial stage of the low resistance operation, the bit line is driven with a larger first current. If the first current continues to flow as described above, excess current is applied to the above-described memory element. For this reason, in the present technology, the current flowing through the bit line is switched from the first current to the smaller second current. Then, control of the element current flowing through the storage element is performed by the second current flowing through the bit line. Therefore, for example, the potential of the bit line is controlled so that the desired current flows even if there is a deviation in the storage element.

When the present invention is not applied, since the current control of the bit line is performed without switching the current, the current value is suppressed to some extent, and the potential change of the bit line takes time.

In contrast, in the present technology, rapid bit line potential change is achieved by the first current at the beginning of operation, and final current control is performed with a smaller second current. The current stress to the storage element depends on, for example, the respective current values of the first current and the second current, and the time for passing them. However, the current control is performed to absorb the device deviation to obtain a desired resistance value, and this object can be sufficiently achieved by controlling the final second current. In this technique, in addition to maintaining this high controllability, since the bit line potential change is rapidly performed at the beginning of operation, the total current application time is shortened.

ADVANTAGE OF THE INVENTION According to this invention, the resistance change type memory device which starts a low-resistance operation by changing the potential of a bit line and performs current control of a bit line, and its operation method further improves high speed.

1 is a correlation diagram of conductance and current in a low resistance state of a memory (ReRAM) using conductive ions.
2A and 2B are equivalent circuit diagrams of memory cells in the case of write current, and equivalent circuit diagrams of memory cells in the case of erase current, respectively.
3 is a schematic diagram showing a device structure of two adjacent memory cells.
4A and 4B, load curves when the resistance of the access transistor using the variable resistance element is reduced, and load curves when the resistance of the access transistor using the variable resistance element is increased, respectively. Graph showing.
Fig. 5 is a circuit diagram showing a column circuit configuration of a resistance-variable memory device according to the first embodiment of the present invention.
6A to 6B are operational waveform diagrams of the column circuit configuration of the resistance change type memory device according to the first embodiment of the present invention.
A and B in Fig. 7 are circuit diagrams and graphs respectively explaining the set operation.
Fig. 8 is a circuit diagram partially showing the entire configuration of the resistance-variable memory device in blocks.
9 is a circuit diagram showing a column circuit configuration of a resistance change type memory device according to a second embodiment of the present invention.
Fig. 10 is a circuit diagram showing a column circuit configuration of a resistance change type memory device according to a third embodiment of the present invention.
11A to 11B are waveform diagrams for explaining the operation of the column circuit configuration of the resistance change type memory device according to the third embodiment of the present invention, respectively.
Fig. 12 is a circuit diagram showing a column circuit configuration of a resistance change type memory device according to a fourth embodiment of the present invention.

An embodiment of the present invention will be described with reference to the drawings, taking as an example a memory device whose resistance changes by the movement of conductive ions.

Hereinafter, description is given in the following order.

1. First embodiment: An example in which the start of the low-resistance operation is performed by lowering the bit line potential and subtracting the current from the bit line. Disclosed is a configuration in which a current flowing through a bit line at the start of a low-resistance operation is switched from a first current to a second current by two transistors in parallel.

2. Second Embodiment: In the case of drawing a bit line current as in the first, an example in which the current is switched with one transistor.

3. Third embodiment: An example in which the start of a low resistance operation is performed by raising the bit line potential and supplying current to the bit line.

4. Fourth embodiment: Example of making the access transistor P-type.

5. Modifications

<1. First embodiment>

[Memory cell configuration]

2A and 2B show equivalent circuit diagrams of memory cells common to the present embodiment. In addition, A in FIG. 2 indicates the direction in relation to write current and B in erase current, but the memory cell configuration itself is common in both figures.

The memory cell MC illustrated in FIG. 1 has one variable resistor element Re as an "memory element" and one access transistor AT.

One end of the variable resistor element Re is connected to the plate PL, the other end is connected to the source of the access transistor AT, the drain of the access transistor AT is the bit line BL, and the gate is the word line ( WL), respectively. Here, the plate PL is an example of the "voltage supply layer". Here, the plate PL may be a single plate-shaped conductive layer common to the memory cell array. Alternatively, the plate PL may be arranged in two dimensions (row and column directions in the cell arrangement of the memory cell array), and may be a lattice-shaped wiring connecting a plurality of memory cells constituting the memory array in common.

In addition, there may be a case where the "voltage supply layer" is wiring. The "wiring" in this case refers to a wiring commonly connected to a plurality of memory cells constituting one row or column in the cell arrangement of the memory cell array.

In this embodiment, the memory cell is more suitable in the two-wire system in which the two lines of the bit line BL and the word line WL are connected in this way. Here, the word line WL controls the access transistor AT, but the control object is not limited to a transistor, and other elements may be used as long as it is a means for selecting a memory cell.

3 shows a device structure of portions corresponding to two adjacent memory cells MC. 3 is a schematic cross-sectional view, and no diagonal line is attached. In addition, the blank portion of FIG. 3, which is not particularly mentioned, is filled with an insulating film, or constitutes a part of another component portion.

In the memory cell MC illustrated in FIG. 3, the access transistor AT is formed on the semiconductor substrate 100.

More specifically, two impurity regions serving as the source S and the drain D of the access transistor AT (AT1 or AT2) are formed on the semiconductor substrate 100, and a gate insulating film is formed on the substrate region therebetween. A gate electrode made of polysilicon or the like is interposed therebetween. Here, the gate electrodes constitute the word lines WL1 and WL2 wired in the row direction (direction perpendicular to the paper plane in Fig. 3), and become the drain D between the word lines WL1 and WL2. Impurity regions are arranged. Further, an impurity region serving as the source S is disposed on the side opposite to the drain D of each word line.

The drain D is connected to the bit line BL formed by the first wiring layer 1M through the bit line contact. Although not shown in FIG. 3, the bit line BL is actually wired long in the column direction (horizontal direction in FIG. 3).

On the source S, the plate contact is formed by repeatedly stacking the plug 105P and the landing pad 105 (formed from the wiring layer). A variable resistance element Re is formed on the plate contact.

The number of layers of the variable resistor element Re is formed on the multilayer wiring structure, but the variable resistor element Re is formed on the fourth to fifth layers.

The variable resistance element Re has, for example, a film structure (laminated body) having an insulator film 102 and a conductor film 103 between the lower electrode 101 and the upper electrode serving as the plate PL. It is made.

Examples of the material of the insulator film 102 include SiN, SiO ₂ , Gd ₂ O ₃ , and the like.

As the material of the conductor film 103, for example, a metal film containing one or more metal elements selected from Cu, Ag, Zr, Al, an alloy film (for example, a CuTe alloy film), a metal compound film, etc. You can. Moreover, if it has the property of being easy to ionize, metal elements other than Cu, Ag, Zr, and Al may be used. Moreover, it is preferable that the element combined with at least one of Cu, Ag, Zr and Al is at least one element among S, Se and Te. The conductor film 103 is formed as a "supply layer of conductive ions".

3, two variable resistance elements Re connected to one plate PL are shown. Here, the memory layers (insulator film 102), ion supply layer (conductor film 103), and plate PL of the two variable resistance elements Re shown are each formed in the same layer. .

Further, in the present embodiment, the plate PL is formed of a conductive layer above the bit line BL. Here, the bit line BL is formed in the first layer wiring layer 1M, and the plate PL is formed in the fourth to fifth layer wiring layer (conductive layer). However, the upper limit relationship of the wiring layer used by the bit line BL and the plate PL may be reversed, and the number of layers of each is arbitrary.

A and B in FIG. 4 are diagrams showing examples of current directions and applied voltage values attached to enlarged views of the variable resistor element Re, respectively.

4 and A, as an example, as an opening of the nitride film (SiN film) 104, the insulator film 102 whose contact area with the lower electrode 101 is regulated is formed of SiO ₂ , and the conductor film ( 103) shows the case where the CuTe alloy-based alloy compound (Cu-Te based) is formed.

In Fig. 4A, voltages are applied to the lower electrode 101 and the upper electrode (plate PL) with the insulator film 102 side as the negative electrode side and the conductor film 103 side as the positive electrode side. For example, the bit line BL is grounded at 0 V, and for example, +3 V is applied to the plate PL.

Then, Cu, Ag, Zr, and Al contained in the conductor film 103 are ionized and attracted to the negative electrode side. Conductive ions of these metals are implanted into the insulator film 102. Therefore, the insulating property of the insulator film 102 is lowered, and the conductivity is reduced and the conductivity is reduced. As a result, the recording current Iw in the direction shown in Fig. 4A flows. This operation is called recording (operation) or set (operation).

On the contrary, in FIG. 4B, a voltage is applied to the lower electrode 101 and the upper electrode (plate PL) with the insulator film 102 side as the positive electrode side and the conductor film 103 side as the negative electrode side. For example, the plate PL is grounded to 0 V, and for example, +1.7 V is applied to the bit line BL.

Then, the conductive ions injected into the insulator film 102 return to the conductor film 103, and are reset to a state where the resistance value before writing is high. This operation is called erase (operation) or reset (operation). In the reset, the erase current Ie in the direction shown in Fig. 4B flows.

Then, the set means &quot; sufficiently injecting conductive ions into the insulator film &quot;, and reset means &quot; extracting sufficiently conductive ions from the insulator film &quot;.

On the other hand, it is arbitrarily defined which state (set or reset) is a data recording state and an erasing state.

In another definition, the transition of the variable resistance element Re from the high resistance state HRS to the low resistance state LRS is set, and vice versa is called reset.

In the following description, when the insulation of the insulator film 102 is deteriorated and the resistance value of the entire variable resistance element Re is lowered to a sufficient level (transition to the low resistance state (LRS)) to the "write (set)" of the data. Match. Conversely, when the insulating property of the insulator film 102 returns to the original initial state and the resistance value of the entire variable resistance element Re rises to a sufficient level (return to the high resistance state (HRS)), data is erased (reset). ) ”.

Here, the arrow of the circuit symbol of the variable resistor element Re shown in A and B in Fig. 2 is usually in the same direction as the current at the time of set (in this case, writing).

By repeating the above-described set and reset, a binary memory that reversibly changes the resistance value of the variable resistance element Re between a high resistance state and a low resistance state is realized. In addition, the variable resistor element Re functions as a nonvolatile memory because data is retained even when the application of voltage is stopped.

However, the present invention may be applied to a multi-valued memory of three or more values other than a two-value memory. In addition, since the resistance value of the insulator film 102 is actually changed by the amount of metal ions in the insulator film 102 at the time of set, data is stored and stored in the insulator film 102. It can be regarded as a "memory layer".

By using this variable resistor element Re to form a memory cell and providing a plurality of memory cells, a memory cell array of a resistance changeable memory can be constructed. The resistance change type memory is configured with this memory cell array and its drive control circuit (peripheral circuit).

[Column circuit composition and operation]

Next, the column circuit configuration and operation will be described with reference to Figs.

Fig. 5 shows a circuit configuration (column circuit configuration) in the column (column) direction of the memory cell array.

In FIG. 5, two memory cells MC1 and MC2 adjacent in the column direction are shown. Each of the memory cells MC1 and MC2, like A and B in Fig. 2, is between the variable resistor element Re connected to the plate PL and the variable resistor element Re and the bit line BL. It has an access transistor AT connected.

The memory cell MC1 is selected by applying a word line driving pulse (represented by WL of the same code) to the word line WL. On the other hand, the word line of the memory cell MC2 is an unselected word line Unsel WL, and in this case, is grounded.

In addition, a plurality of memory cells are connected between the bit line BL and the plate PL.

In FIG. 5, other memory cells are not illustrated, but in this case, the memory cells not illustrated are in a non-selected state in which the word line is grounded, as in the memory cell MC2.

A plurality of memory column configurations having the same configuration are repeatedly arranged in a row direction based on the configuration shown in FIG. 5 to form a memory cell array.

In this column circuit configuration, the voltage driver 51 (voltage driver), the element current control unit 52 of the bit line, and the set driver 5 (drive control circuit) having the initial current driver 53 are a plurality of common. Disclosed is a structure shared by Sunssang.

Therefore, there is a need for a configuration in which any one pair of shared common line pairs is selected and connected to the drive control circuit.

More specifically, the selection transistor 61 of the bit line BL is provided for each memory column. The selection transistor 61 is provided with the number of memory columns sharing the same drive control circuit. In Fig. 5, four selection transistors 61 are shown.

Since the selection transistor 61 shown in FIG. 5 has an NMOS configuration, a positive column selection pulse YSW is applied to the gate.

On the other hand, in the other non-selected selection transistors 61, each gate is grounded.

The common wiring connected to the bit line BL by the selection transistor 61 is called "common bit line CBL".

The set driver 5 (drive control circuit) is a circuit or element connected to the common bit line CBL, and includes a voltage driver 51 (voltage driver), an element current controller 52, and a reset portion 53. And an initial current driver 55.

In addition, the "reset" of the reset section 53 does not mean the above-described erasing or high-resistance operation, but only a non-operational state (so-called standby). Thereafter, the word "reset" may be used in the sense of standby.

The voltage driver 51 has two PMOS transistors P1 and P2 and two NMOS transistors N1 and N2.

The common drain of the PMOS transistor P2 and the NMOS transistor N1 is connected to the common bit line CBL. The PMOS transistor P1 is connected between the source of the PMOS transistor P2 and the supply line of the positive set voltage Vset. The NMOS transistor N2 is connected between the source of the NMOS transistor N1 and the supply line of the ground potential.

The set enable signal SetEn is applied to the gate of the NMOS transistor N1, and the inverted signal of set enable (/ SetEn) is applied to the gate of the PMOS transistor P2.

A set pulse enable signal SetPlsEn is applied to each gate of the PMOS transistor P1 and the NMOS transistor N2.

The element current control unit 52 is a single NMOS transistor connected in series via two NMOS transistors N1 and N2 between a common bit line CBL and a supply line of a reference voltage (for example, ground potential) ( N3).

The set gate voltage Vgset for current control is supplied to the gate of the NMOS transistor N3.

The characteristic configuration in this embodiment is that the NMOS transistor N4 constituting the initial current driving unit 55 is provided in parallel with the NMOS transistor N3 constituting the element current control unit 52. The NMOS transistor N4 is driven by the bit line driving signal BLDRV.

Here, NMOS transistor N3 corresponds to an example of "second transistor TR", and NMOS transistor N4 corresponds to an example of "first transistor TR".

The securing of the bit current controllability by switching the two transistors and its contribution to high-speed operation will be described in the operation described later.

The reset section 53 has a PMOS transistor P5 whose source is connected to the supply line of the set voltage Vset, and its drain is connected to the common bit line CBL. The gate of the PMOS transistor P5 is controlled by the reset signal BLRES.

Before explaining the operation of FIG. 5 using A to I in FIG. 6, the basics of the set operation will be described using A and B in FIG. 7.

The set operation (low resistance operation) starts by lowering the potential (BL potential) of the bit line BL from the state in which the positive set voltage Vset is applied to the bit line BL and the plate PL. At this time, the power supply voltage Vddd) is applied to the word line WL. For this reason, the element current (write current Iw here) flows in the direction of the arrow shown in Fig. 7A. Then, hereinafter, the recording current Iw is also referred to as a "set current".

FIG. 7B is a diagram in which a load voltage by a variable resistor element Re is superimposed on a drain voltage-drain current characteristic (saturation characteristic) of the access transistor AT in which the channel is opened due to a power voltage being applied to the word line. to be.

As shown in Fig. 7A, the node between the variable resistor element Re and the access transistor AT is referred to as a storage node SN. The horizontal axis of B in FIG. 7 shows the SN voltage (drain voltage of the access transistor AT) based on the bit line potential in the ground state. In addition, the vertical axis of B in FIG. 7 shows the Set current (drain current of the access transistor AT).

Before the set operation, since the applied voltage of the word line WL is, for example, the power supply voltage Vddd, the storage node SN and the bit line BL are short-circuited, and the SN potential and the bit line BL ) 'S potential (hereinafter, BL potential) is almost above the coin. In addition, since the bit line BL is maintained at the set voltage Vset at this time, only a very small voltage is applied to the variable resistance element Re, and the variable resistance element Re is almost in a stress-free state. . In addition, the voltage between the source and the drain of the access transistor AT is very small, and does not flow current even when operating in a non-saturation region.

In this state, the set operation starts, and the potential of the bit line BL falls to the reference potential, for example, GND. At the start of the set, the slope of the load straight line is small because the variable resistance element Re is in the high resistance state HRS. For a while from the start of this set operation, the voltage at the operating point (first storage node voltage Vsn1) is very small. Therefore, a large voltage of (Vset-Vsn1) is applied to the variable resistor element Re to expose the voltage stress. Here, since the BL potential is (Vset-Iset × Rcell) and the cell resistance Rcell is very large, the BL potential takes a value close to the reference voltage Vss (here, GND = 0V). Therefore, the applied voltage of the variable resistance element Re is a large voltage close to the set voltage Vset.

When this large stress takes a certain time, the variable resistance element Re transitions from the high resistance state HRS to the low resistance state LRS (LRS inversion). When the LRS inversion occurs, the slope of the load straight line increases rapidly, and the operating point enters the saturation region. The voltage at the operating point transitions from the small first memory node voltage Vsn1 to the second memory node voltage Vsn2. After LRS inversion, the SN potential becomes a voltage (Vsn2) = (Iset × RLRS) determined by the product of Set current (Iset) (element current after inversion) and element resistance value (RLRS) at LRS, The voltage Vset-Vsn2 is applied to the variable resistance element Re.

In the current driving method of the bit line, as shown in Fig. 7A, the NMOS transistor N3 (element current control unit 52) to which the set gate voltage Vgset is applied is effectively, the bit line BL. And a ground potential (see Fig. 5).

Now, for example, assuming the case where the NMOS transistor N3 is not present, the bit line BL is directly connected to the ground potential, and the potential is fixed. In this case, if there is a characteristic variation of the storage element (variable resistance element Re), the operating point also fluctuates, and as a result, the set current value is disturbed.

In contrast, in the current driving method of the bit line, the drain potential (bit line potential) is changed so that the NMOS transistor N3 keeps the current flowing through the bit line (that is, the write current (IW) or Set current) constant. . For this reason, even if there is variation in device characteristics, the set current is constant in the saturation region.

After LRS inversion, the potential of the bit line BL is returned to the original set voltage Vset, and the set operation is ended.

In the above set operation, an example of switching the current and lowering the BL potential will be described in terms of circuit operation using the timing charts shown in A to I in Fig. 6. In addition, in this operation description, reference numerals of the circuit elements used in FIG. 5 are appropriately cited.

In the standby state until the time t0 shown in FIGS. 6A to 6, various (pulse) signals used in FIG. 5 are high (H), respectively, as shown in FIGS. Or take the determined value of row L.

Specifically, the access transistor AT is turned off at WL = L, the selection transistor 61 is turned off at YSW = L, and the bit line BL is separated from the common bit line CBL. (/ BLRES) = L, and the common bit line CBL is connected to the set voltage Vset by the PMOS transistor P5 in the on state, and also because SetEn = L, the voltage by the voltage driver 51 The drive is inactive. Further, the bit line driving signal BLDRV is L at an active level, but the NMOS transistor N1 is turned off with SetEn = L, and therefore, the NMOS transistor N4 constituting the initial current driver 55 does not operate. .

At this time, the set gate voltage Vgset shown in G of FIG. 6 is set to a certain voltage by a control circuit not shown in FIG. 5. However, since SetEn = L, the NMOS transistor N4 is turned off, and the bit line current control by the NMOS transistor N3 does not work (it is invalid).

As in H and I in Fig. 6, in the standby mode, the set voltage Vset is taken because the bit line BL, the common bit line CBL, and the like are SetEn = L, and the device current does not flow.

At time t0, various signals shown in FIGS. 6A to D are inverted.

As a result, the standby state is released, and the column switch conducts, so that the bit line BL is connected to the common bit line CBL.

The access transistor AT becomes conductive.

In addition, in the voltage driver 51, the NMOS transistor N1 and the PMOS transistor P2 can be turned on. However, since SetPlsEn = L is maintained as shown in E of FIG. 6, the voltage driving of the plate by the voltage driver 51 has not been performed yet.

In addition, in the element current control unit 52, it becomes a valid period during which bit line current control is possible by the NMOS transistor N3.

As described above, the preliminary preparation of the set operation is ordered by the signal inversion at time t0.

The set operation (low-resistance operation) starts at a time t1 continued to the time t0. At this time, the bit line BL and the common bit line CBL begin to drop in potential to the ground potential, and the set operation starts.

What is characteristic of this embodiment is that the start of the set operation is driven by the NMOS transistor N4 through which a large first current I1 having a greater driving force flows, and the first current I1 in the middle is smaller than the second. It is to convert to current (I2).

Specifically, when the set pulse enable signal SetPlsEn rises at time t1, both of the NMOS transistors N1 and N2 are turned on, so the NMOS transistor N4 (initial current driver 55) ) Also comes. As a result, as shown in H in Fig. 6, the potentials of the common bit line CBL and the bit line BL fall rapidly.

At a time t3 when the potential is sufficiently reduced, the switching transistor is switched from the NMOS transistor N4 to the NMOS transistor N3 in order to convert the current flowing from I1 to I2. This switching is performed by the bit line driving signal BLDRV falling.

By this two-step current driving, speeding up of the set operation is achieved as follows.

FIG. 6H shows a case where the two-step current driving is not performed by the broken line, that is, the initial current driving unit 55 is not provided. In this case, since only the NMOS transistor N3, which is gate biased for current control and cannot flow a current rapidly, is driven, only a moderate potential drop is obtained.

On the other hand, in this embodiment, rapid dislocation reduction can be obtained by switching between I1 and I2 in two stages, and as a result, the LRS transition is also faster, resulting in shorter set operation time.

Even if such a set operation is started, as shown in the load curve of FIG. 7B, the set driver 5 operates in a linear region because the memory cell is in a high resistance state (HRS), and the BL potential is "(Vset -Iset × RHRS) Vss (GND) ”. Therefore, the variable resistance element Re is exposed to a large voltage stress close to Vset, and LRS is reversed after a while. This is as described above using A and B in Fig. 7.

In H in Fig. 6, the period from time t1 to time t3 indicates the stress application time (practical recording time) until LRS inversion occurs. In this way, in the resistance change type memory element, for example, the memory elements having the structures A and B of Fig. 4, the movement of metal ions starts to occur by application of a voltage that is somewhat large, and a resistance state transition occurs.

When LRS inversion occurs at time t3, the BL potential is controlled so that the bit line current, that is, the device current (Set current) is constant, by controlling the bit line current of the NMOS transistor N3 of the device current control unit 52. do. The BL potential after this control, as shown in H in Fig. 6, takes a value larger than the ground potential GND and smaller than the set voltage Vset. This value is adaptively changed for each memory cell so that the set current Iset is constant even if there is a characteristic variation in the variable resistance element Re. In addition, the set current Iset can be controlled to a desired value by the set gate voltage Vgset applied to the NMOS transistor N3.

Here, the voltage of (Iset × RLRS) is applied to the variable resistor element Re, as shown in H in FIG. 6. At this time, as shown in A and B of FIG. 4, the resistance of the LRS (RLRS) can be controlled by the value of the Set current (Iset). This control is a bit line current control in the present invention, and a desired LRS resistance value RLRS can be obtained by setting the set gate voltage Vgset given to the NMOS transistor N3 shown in FIG. .

Therefore, it is possible to realize a narrow LRS resistance distribution in a large number of memory cells, and it is also easy to realize a multivalued memory with more than 2 bits.

In the subsequent time t4, the set pulse enable signal SetPlsEn returns to L. The BL potential is raised to the potential Vset of the plate PL, whereby the set operation (lower resistance operation) ends.

At time t6, if all signals are returned to the initial logic, the standby state is resumed.

[Block configuration of the entire memory]

In Fig. 8, the entire block configuration of the resistance changeable memory device is illustrated. Fig. 8 is a circuit block diagram showing a main portion of a memory cell array 1 in which a number of 1T-1R type memory cells MC are arranged in a matrix form and their peripheral circuits.

The illustrated memory employs a method in which one set driver 5 and a common pair of lines CBL and CSL to which the set driver 5 is connected are shared for every four memory cell rows. The connection control between the four memory cell columns and one common line pair (CBL, CSL) is performed by the YSW unit 60 having four pairs of selection transistors 61 and 62. This connection control is 1/4 MUX switching, and only one pair is selected from four (BL, SL) pairs connected to the common line pair (CBL, CSL).

A YSW driver 6 is provided for generating the selection signals YSW <0> to YSW <3> of the selection transistors 61 and 62 provided in four pairs for each YSW unit 60.

In addition, a WL driver which selects any one of (N + 1) word lines WL <0> to WL <N> provided in the memory cell array 1 and drives it with, for example, a power supply voltage Vddd) (4) is provided.

In this example employing the 1 / 4MUX switching method, the set driver 5 is provided as many as 1/4 of the number of memory columns, and accordingly, there is room in the set driver 5 deployment space, and efficient arrangement Because it is made of, area reduction is planned.

Each set driver 5 has a circuit configuration shown in Fig. 5, and four kinds of necessary signals are supplied from the set control circuit 11 in the memory. The four types of signals are the set pulse enable signal (SetPlsEn), the set enable signal (SetEn), the bit line drive signal (BLDRV), and the reset signal (BLRES). , A total of six types of signals are generated in the set control circuit 11.

A power circuit 8 for generating the set voltage Vset and the set gate voltage Vgset is provided.

Here, the set control circuit 11 may be realized as part of the functions of the integrated control circuit of a sub-notch that collectively controls all the blocks of the memory device, or may be arranged as individual control circuits controlled by the integrated control circuit.

Further, the power supply circuit 8 is controlled by the integrated control circuit (not shown) or the set control circuit 11 to variably control the value of the set gate voltage Vgset. Thereby, a memory in which the set current is changeable is realized to obtain a desired LSR resistance value.

<2. Second Embodiment>

9, a column circuit configuration diagram is shown.

9, the initial current driver 55 (N3) is omitted, and instead, a control circuit 52A is added. The control circuit 52A constitutes a part of the element current control unit 52. However, the arrangement is provided in the power supply circuit 8 as shown in FIG. 8.

In this second embodiment, the gate bias of the element current control unit 52 is controlled so that a larger first current I1 flows in the initial stage of the set current, and then continues to be smaller than the first current I1. 2, a configuration for switching the gate bias is started so that current flows.

Specifically, the control circuit 52A has an NMOS transistor N6 and a PMOS transistor P6 connected in parallel to the gate of the NMOS transistor N3. The drain of the NMOS transistor is connected to the supply line of the set voltage Vset. The PMOS transistor P6 has an input terminal of the set gate voltage Vgset. The set gate voltage Vgset is generated in the set control circuit 11 of FIG. 8 or the integrated control circuit of the not shown, and is given to the PMOS transistor P6.

The NMOS transistor N6 and the PMOS transistor P6 are differentially controlled by the bit line driving signal BLDRV. Hereinafter, although the reduction of the BL potential by this differential control will be described, the operation waveform diagram is the same as A to I in Fig. 6, and A to I in Fig. 6 are applied as it is.

Since the NMOS transistor N6 is turned on and the PMOS transistor P6 is turned off at the beginning of the start of the set operation, the NMOS transistor N3 constituting the element current control unit 52 is driven with a larger set voltage Vset. . Therefore, rapid pull-down of the BL potential is performed with a large current driving force. When a sufficient potential drop is obtained, the NMOS transistor N6 is turned off and the PMOS transistor P6 is turned on by inversion of the bit line driving signal BLDRV. Thereby, bit line current control is performed by the set gate voltage Vgset of a smaller voltage value after that.

<3. Third embodiment>

The column circuit configuration diagram according to the third embodiment is shown in Fig. 10, and the operation waveform diagram (timing chart) is shown in Figs. 11A to 11, respectively.

In the first embodiment described above, the set operation was performed by lowering the BL potential from a high potential to a low potential. In contrast, in the second embodiment, a set operation is performed by raising the BL potential from a low potential to a high potential.

10, the transistors constituting the element current control unit 52 are arranged on the power supply side (set voltage Vset side) as shown in FIG. 10, and in parallel with this, the initial current driving unit 55 A transistor constituting is also provided. These transistors P3 and P4 are changed from N type to P type. In addition, the active logic of the control signal is also inverted.

Further, the plate PL is maintained at the ground potential.

In this case, the operation waveforms shown in FIGS. 11A to 11 are obtained. Then, A and E in Fig. 11 are inverted from the waveforms A and E in Fig. 6.

Besides, the voltage waveform diagram shown in H in Fig. 11 is different from that shown in H in Fig. 6. In this case, the set operation starts by increasing the BL potential from L to H. In addition, the operation of returning to the standby state at the end is performed by returning the potential to L.

The two-stage current control in the initial stage of the set operation is as described in the first embodiment. This enables high-speed operation while maintaining high current controllability.

In addition, performing such a set operation by raising the BL potential is also applicable to the second embodiment. In addition, the block diagram of FIG. 8 is applicable as it is in this embodiment.

<4. Fourth embodiment>

12 shows the column circuit configuration according to the fourth embodiment.

In the configuration shown in Fig. 12, the access transistor AT of each memory cell MC is changed from the NMOS transistors of the first to third embodiments to PMOS transistors. In connection with this, the active logic of the control signal of the word line WL needs to be inverted with the case of A in Fig. 6 and A in Fig. 11. The block diagram of Fig. 8 is applied as it is.

Other circuit configurations and operation waveform diagrams are common to the first to third embodiments.

As described above, the present invention starts a low-resistance operation (set operation) with a change in the potential of the bit line, and controls the element current (Iset) flowing in the storage element Re at the bit line side during the low-resistance operation. . Then, at the beginning of the start of the set operation, a change in the BL potential at a high speed is achieved with the first current, and the second current is switched to control the bit line current with the second current. This control is executed in a drive control circuit that includes at least the set driver 5. The drive control circuit may include a set control circuit 11 (or integrated control circuit), a power supply circuit 8, and the like as concepts.

As a specific configuration of the drive control circuit, the initial current driver 55 (first transistor N4) connected to the bit line BL to flow the first current I1 and the second current I2 connected in parallel therewith It is sufficient to include an element current control unit 52 (second transistor N3) that performs bit line current driving while flowing. In this case, the first and second transistors N4 and N3 may be differentially controlled to switch the first and second currents.

The driving ability of the first transistor N4 is greater than that of the second transistor N3.

Alternatively, the first transistor N4 is input to the second transistor N3 and is a voltage at a peak value (for example, Vset) larger than the peak value (for example, Vgset) of the control pulse when controlling the device current. It is driven.

Either the configuration that performs the set operation by lowering the BL potential or the configuration that performs the set operation by increasing the BL potential may be used.

Alternatively, the initial current driving unit 55 (N4) is omitted, and the gate of the NMOS transistor N3 of the device current control unit 52 is changed in voltage to initially drive with a large current driving force, and thereafter, for BL current control. It is also possible to switch to a suitable, smaller driving force. This control may be realized as part of the functions of the set control circuit 11 or the integrated control circuit.

<5. Modification>

In the above embodiment, the "voltage supply member" for applying a voltage to the storage element together with the bit line was mainly described as the plate PL. However, this voltage supply member includes, for example, a three-wire embodiment, which is separated for each memory column, such as a source wire. In the block diagram of FIG. 8, the source line SL is provided separately, and individual control is also possible, and it is also possible to collectively drive voltage like a plate.

In general, in the 3-wire system, it is sufficient if the voltage change at the start of the low-resistance operation is performed by a separate wiring (source line SL). However, this is not a reason for excluding the present invention in which operation start and current control are performed on the side of the same bit line BL, in which voltage control and current control are simultaneously performed with the bit line in equation (3). Therefore, it is possible to apply the present invention to a three-wire system.

The resistance change type memory device according to the present invention is suitable for a type in which resistance values are changed by movement of conductive ions, for example, showing structures in A and B of Fig. 4. However, the present invention can be widely applied to other resistance change type memories, such as a type using an oxidation and reduction of an insulating layer.

Various modifications, combinations, partial combinations, and modifications to the above-described embodiments can be carried out by those skilled in the art according to design needs or other factors within the scope of the following claims or equivalents thereof. There will be.

The present invention claims priority to Japanese Patent Application No. 2011-132576 filed with the Japan Patent Office on June 14, 2011.

1: Memory cell array
5: set driver (drive control circuit)
51: voltage driver (voltage driver)
52: current control
53: reset unit
55: initial current driving unit
60: YSW part
8: Power circuit
11: Set control circuit
MC: memory cell
Re: Variable resistance element (memory element)
AT: access transistor
BL: Bit line
SL: Plate
WL: Word line
Iw: Write current (Iset: Set current, device current)

Claims (10)

Bit line,
Voltage supply layer,
A memory element that is connected between the bit line and the voltage supply layer, and whose resistance value changes in response to an applied voltage to the memory element;
The first current is passed through the bit line, and thereafter, a second current smaller than the first current is passed through the bit line, thereby reducing the resistance of the memory element from a high resistance state to a low resistance state. It is provided with a drive control circuit to control the current,
The drive control circuit,
An initial current driver connected to the bit line and passing the first current;
And an element current control unit connected to the bit line in parallel with the initial current driving unit to control the second current,
By controlling the initial current driving unit and the device current control unit, the current flowing through the bit line is switched from the first current to the second current,
The initial current driver has a first transistor connected between a supply line of a reference voltage and the bit line,
The device current control unit includes a second transistor connected between the supply line of the reference voltage and the bit line,
The drive control circuit,
A third transistor for initially setting the bit line to the same potential as the supply line of the reference voltage;
A fourth transistor inverted driving with the third transistor to disconnect the first and second transistors from the bit line during the initial setting, and to connect to the bit line after the initial setting;
And a control circuit for controlling conduction and non-conduction of the first, second, third and fourth transistors. According to claim 1,
The resistance change type memory device, characterized in that the driving capability of the first transistor is greater than the driving capability of the second transistor. According to claim 1,
The first transistor is input to the second transistor, the resistance change type memory device, characterized in that driven by a voltage of a crest value larger than the crest value of the control pulse when controlling the element current. According to claim 1,
The first and second transistors are N-type transistors connected in parallel between a supply line of a reference voltage and the fourth transistor,
The voltage of the initial setting of the bit line is a constant voltage higher than the reference voltage,
The third transistor is a P-type transistor,
And the fourth transistor is an N-type transistor controlled by the same signal as the third transistor. According to claim 1,
The first and second transistors are P-type transistors connected in parallel between a supply line of a constant voltage higher than a reference voltage and the fourth transistor,
The voltage of the initial setting of the bit line is the reference voltage,
The third transistor is an N-type transistor,
Wherein the fourth transistor is a P-type transistor controlled by the same signal as the third transistor. According to claim 1,
The drive control circuit,
A current control transistor connected to the bit line and passing the first current or the second current;
And a control circuit that controls a potential of a control node of the current control transistor, and converts a current flowing through the current control transistor from the first current to the second current. Bit line,
Voltage supply layer,
A memory element that is connected between the bit line and the voltage supply layer, and whose resistance value changes in response to an applied voltage to the memory element;
The first current is passed through the bit line, and thereafter, a second current smaller than the first current is passed through the bit line, thereby reducing the resistance of the memory element from a high resistance state to a low resistance state. It is provided with a drive control circuit to control the current,
The drive control circuit,
An initial current driver connected to the bit line and passing the first current;
And an element current control unit connected to the bit line in parallel with the initial current driving unit to control the second current,
By controlling the initial current driving unit and the device current control unit, the current flowing through the bit line is switched from the first current to the second current,
The initial current driver has a first transistor connected between a supply line of a reference voltage and the bit line,
The device current control unit includes a second transistor connected between the supply line of the reference voltage and the bit line,
The drive control circuit,
A third transistor for initially setting the bit line to the same potential as the supply line of the reference voltage;
A fourth transistor inverted driving with the third transistor to disconnect the first and second transistors from the bit line during the initial setting, and to connect to the bit line after the initial setting;
And a control circuit for controlling conduction and non-conduction of the first, second, third and fourth transistors. delete delete delete

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