KR102012270B1 - Prediction Method of the Information Throughput Change of OBP Satellite Due to Changes of Cosmic Radiation Environment and Prediction Device thereof - Google Patents

Abstract

The present invention relates to a method and a prediction apparatus for predicting a change in information throughput of an OBP satellite according to a change in the space radiation environment, comprising: mitigating and correcting occurrence of SEU in a system of an OBP satellite modem; Calculating a cumulative error rate occurring in the SRAM-based FPGA through error correction using mitigation and correction; And predicting the performance of the OBP system through parameters and mathematical models applied to the mitigating and modifying steps.

Description

Prediction Method of the Information Throughput Change of OBP Satellite Due to Changes of Cosmic Radiation Environment and Prediction Device

The present invention relates to a method and a prediction apparatus for predicting a change in information throughput of an OBP satellite according to a change in the space radiation environment, and more particularly, a system for reducing the probability of system error when a Field Programmable Gate Array (FPGA) is exposed to the space radiation environment. The present invention relates to a method and a prediction apparatus for predicting change in information throughput according to changes in space radiation environment of OBP satellites.

SRAM-based FPGAs are driven by advances in semiconductor integration processes, resulting in higher memory capacity, smaller device size, and faster data throughput. In addition, FPGAs are fast and cheap for prototyping, so they can be used directly in real-world industrial systems, while space-class FPGA devices can be used as controllers or processors that can be directly applied to the embedded processing platform of the aerospace industry. This device is very practical for the market and helps to reduce costs. Because of these advantages, SRAM-based FPGAs are used as controllers and processors in a variety of missions in the space industry, including Mars probes, multipurpose satellites, and communication satellites.

The biggest drawback of SRAM-based FPGAs, however, is the use of SRAM, which is volatile memory. This SRAM memory is used to store configuration bit information containing information about the design of the interconnect structure of the FPGA internal fabric. When SRAM-based FPGAs are used in spacecraft and satellites in space missions outside the atmosphere, single-event upsets (SEUs) caused by heavy ions flying into the Earth by the action of electrons, protons, and the sun inside Van Allen This changes the circuit design implemented inside the SRAM-based FPGA, causing performance degradation and malfunctions.

Two methods are most commonly used to prevent performance degradation and malfunction due to the SEUs. The first method is to design the overall circuit design in three and put each output as the input of the majority voting circuit to eliminate erroneous output caused by SEU phenomenon. This is called Triple Modular Redundancy (TMR). The second method is the configuration scrubbing method, which is a method of rewriting configuration bit information stored in the SRAM at a periodic time or when a change of the configuration bit information is detected by the SEU phenomenon. However, since the configuration bits are not composed of a wide data word, and the configuration bits and the logic configuring the user's circuit design are in direct connection, an error correcting code (ECC) is used to detect errors in the configuration bits caused by the SEU phenomenon. ) Is not suitable for implementation. Therefore, the periodic scrubbing technique, which is the nature of space missions and therefore a simple and reliable error correction method, is frequently used to correct errors in configuration bits.

OBP system used in next-generation communication satellites is a modem processing that receives continuous uplink data and performs various signal processing functions, and receives data in the form of pipeline that transmits the signal processed data to users on the ground through downlink. Because the process-transmission process is continuous, the configuration bit error of the OBP system due to the SEU phenomenon has a lasting adverse effect on the data throughput unless corrected by the correction technique.

As such, error suppression and correction techniques for component bits due to the SEU phenomenon have been devised, but the complete control of the SEU phenomenon is still impossible, and further, how the SEU phenomenon quantitatively affects the OBP satellite communication system. Is a nil situation.

Korea Patent Registration No. 10-1667400 Korean Patent Publication No. 10-2008-0074448

One aspect of the present invention is directed to a change in configuration bit values generated in a configuration memory when a field random access memory (SRAM) based Field Programmable Gate Array (FPGA) based on a satellite communication system is exposed to a cosmic radiation environment. The present invention provides a method and a prediction apparatus for predicting a change in information throughput of an OBP satellite according to a change in the space radiation environment using a system structure for reducing the probability of system error.

The technical problem of the present invention is not limited to the technical problem mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

According to an embodiment of the present invention, a method for predicting a change in information throughput of an OBP satellite according to a change in space radiation environment may include: mitigating and correcting occurrence of SEU in a system of an OBP satellite modem; Calculating a cumulative error rate occurring in the SRAM-based FPGA through error correction using mitigation and correction; And predicting the performance of the OBP system through parameters and mathematical models applied to the mitigating and modifying steps.

In one embodiment, the mitigating and modifying steps include: applying an XTMR design to the OBP system to mitigate the SEU phenomenon; And applying a blind scrubbing scheme to correct an error due to the occurrence of the SEU.

In one embodiment, estimating the performance of the OBP system may comprise: generating a mathematical model representing an SRAM configuration bit error rate that varies with a parameter and a scrubbing period value applied to the mitigation and correction steps; And expressing data performance of the OBP system through the generated mathematical model.

According to an embodiment, the parameter may include at least one of a relaxation window size, a relaxation window number, an average fan-out number, and a configuration bit number used.

In one embodiment, the data performance (G) of the OBP system is 2Gbps, and the SRAM-based FPAG used for the modem may have a 200MHz clock rate (F).

(상기 b는 클럭 당 처리된 비트 수)을 만족할 수 있다.In one embodiment, the data performance (G) of the OBP system is,

(Where b is the number of bits processed per clock).

)은, 수학식

(상기

는 1 클럭 당 SEU 비트를 액세스할 확률)을 만족할 수 있다.In one embodiment, loss of data throughput (

) Is the equation

(remind

May satisfy the probability of accessing the SEU bit per clock.

는, 수학식

(상기 n은 SEU가 발생된 구성 비트, 상기 Nb는 시스템 구성 비트의 수)을 만족할 수 있다.In one embodiment, the

Is the equation

(Where n is the configuration bits from which the SEU is generated and Nb is the number of system configuration bits).

In an embodiment, estimating the performance of the OBP system may further include expressing quantitatively the data performance of the OBP system represented by a formula and expressing it as a BER occurring during data transmission of an OBP satellite. Can be.

으로부터 하한 BER를 예측할 수 있다.In one embodiment, the step of expressing the BER,

The lower limit BER can be predicted from.

An apparatus for predicting change in information throughput of an OBP satellite according to a change in space radiation environment according to an embodiment of the present invention includes: a mitigation correction unit for mitigating and correcting occurrence of SEU in an OBP satellite modem system; An error rate calculator that calculates a cumulative error rate occurring in the SRAM-based FPGA through error correction using mitigation and correction; And a performance predictor for predicting the performance of the OBP system through parameters and mathematical models applied to the mitigation correction unit.

According to the aspect of the present invention described above, it is possible to quantitatively express the performance change of the OBP system implemented by the SRAM-based FPGA, which is changed according to the change of the space environment, to prepare a countermeasure using the same on the ground.

1 is a diagram showing the configuration of Triple Modular Redundancy (TMR).
FIG. 2 is a control block diagram illustrating an apparatus for predicting a change in information throughput of an OBP satellite according to a change in space radiation environment according to an embodiment of the present invention.
3 is a flowchart illustrating a method for predicting a change in information throughput of an OBP satellite according to a change in space radiation environment according to an embodiment of the present invention.
4 is a graph showing the cumulative error rate that occurred during one scrub cycle by SEU error rate.
5 is a three-dimensional plot of the cumulative error rate taking into account the SEU error rate and the number of mitigation windows.
6 is a diagram illustrating a modem for signal processing in an OBP satellite.
FIG. 7 is a flow chart illustrating the mitigation and modification steps in FIG. 3.
8 illustrates a configuration bit upset and a relaxation window.
FIG. 9 is a diagram illustrating a step of predicting the performance of the OBP system of FIG. 3.

DETAILED DESCRIPTION The following detailed description of the invention refers to the accompanying drawings that show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that the various embodiments of the present invention are different but need not be mutually exclusive. For example, certain shapes, structures, and characteristics described herein may be embodied in other embodiments without departing from the spirit and scope of the invention in connection with one embodiment. In addition, it is to be understood that the location or arrangement of individual components within each disclosed embodiment may be changed without departing from the spirit and scope of the invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention, if properly described, is defined only by the appended claims, along with the full range of equivalents to which such claims are entitled. Like reference numerals in the drawings refer to the same or similar functions throughout the several aspects.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the drawings.

Deployed on LEO's communications satellites, OBP systems can implement high-performance reconfigurable architectures using SRAM-based FPGAs. However, because SRAM is very vulnerable to SEU, it is essential to apply SEU mitigation schemes to OBP systems implemented with SRAM-based FPGAs.

There are two ways to solve the SEU phenomenon: error masking schemas and error correction schemas. Both of these SEU solutions require consideration of cost, complexity, requirements, and system performance.

As shown in FIG. 1, there is a Triple Modular Redundancy (TMR) Scheme, which is a structure most widely used in a satellite system to screen an unbalance of configuration bits. TMR is a technique for mitigating erroneous outputs by the SEU, which can mitigate errors by doubling the overall circuit design and placing voter circuits to mask the error signals. The application determines the size of the selected circuit structure and the number of functional logic groups, and the size of the Mitigation Window (MW) can change depending on the number of configuration bits organized into the logic groups. In general, smaller MW sizes will improve mitigation of error masking, but will also increase the ratio of MW and the number, complexity, and power consumption of voter circuits.

Configuration scrubbing is a method used to correct errors due to SEU of configuration bits in SRAM-based FPGAs in satellite systems. Configuration scrubbing is the process of restoring bit upsets in configuration memory by writing the correct configuration data back into configuration memory. In a typical SRAM system, data words are read at once, and Error Correction Coding (ECC) detects and corrects error bits in the data word. The data words then make up your circuit.

However, the configuration SRAM in the FPGA is directly connected to user logic such as LUTs, MUXs, and PIPs in the configuration bits. That is, when confusion occurs in the used configuration bits, confusion occurs in the logic circuit, and since the configuration bits are not composed of wide data words, it is inappropriate to use the ECC scheme as a parity bit.

Therefore, a technique for rewriting the SRAM configuration memory is generally used, and there are two configuration scrubbing methods, blind scrubbing and read-back scrubbing.

In the case of read back scrubbing, it calculates the correct data if there is an upset and writes the modified data. The main advantage of this method is that it writes only when there is confusion, but the disadvantage is that it requires additional nonvolatile memory and space, and increases power consumption. The most important disadvantage is that it is impossible to recover when MBU (Multi Bit Upset) occurs, which can damage the configuration.

Blind scrubbing is a very simple and fast scrub method (in ms). In addition, blind scrubbing does not require additional nonvolatile memory. The requirements for area and power consumption are very low, so this scheme is often used when the SEU rate is low and the environment is not critical during the system's working period.

OBP systems used in communication satellites are a pipelined structure in which input signals on the uplink are continuously transmitted from ground users and data is processed by the OBP modem. The output signal is also transmitted continuously by the OBP satellite. OBP modems with continuous data processing are burdensome to apply readback scrubbing to calculate if an upset has occurred by reading long scrub cycles and configuration bits. This burden not only increases power consumption and complexity, but also increases the probability of causing irreparable system failure. For these reasons, simple blind scrubbing and TMR structures have been applied to the error correction technique in the present invention.

FIG. 2 is a control block diagram illustrating an apparatus for predicting a change in information throughput of an OBP satellite according to a change in space radiation environment according to an embodiment of the present invention.

Referring to FIG. 2, the apparatus 1 for predicting change in information throughput of an OBP satellite according to a change in the space radiation environment includes a mitigation correction unit 10, an error rate calculator 20, and a performance predictor 30.

The mitigation corrector 10 mitigates and corrects the occurrence of SEU in the system of the OBP satellite modem.

The error rate calculator 20 calculates a cumulative error rate occurring in the SRAM-based FPGA through error correction using mitigation and correction.

The performance predictor 30 predicts the performance of the OBP system through parameters and mathematical models applied to the relaxation correction unit 10.

3 is a flowchart illustrating a method for predicting a change in information throughput of an OBP satellite according to a change in space radiation environment according to an embodiment of the present invention.

Referring to FIG. 3, in the method of predicting change in information throughput of an OBP satellite according to a change in the space radiation environment, first, the mitigation correction unit 10 mitigates and corrects generation of SEU in a system of an OBP satellite modem (100).

After mitigating and correcting the occurrence of SEU in the system of the OBP satellite modem in step 100 described above, the error rate calculator 20 calculates the cumulative error rate occurring in the SRAM-based FPGA through error correction using mitigation and correction (200). ).

Since the cumulative error rate must be less than the inverse of the time window or mean time to failure (MTTF) value, the scrub rate must be adjusted to meet the cumulative error rate requirement.

For OBP systems with real-time data processing, larger scrub ratios increase system overhead by increasing the overhead that affects system operation. Repair of the satellite in orbit during the mission is not possible, so it is desirable to meet the requirements and minimize the scrub rate to reduce the chance of permanent failure due to hardware fatigue due to relatively frequent scrubbing. The boundary cumulative error rate by the time window is expressed by Equation 1 below.

는 시간 윈도우에 의한 경계 누적 오류율이고,

는 단위 장치 당 구성 비트 업셋 확률이고, Nb는 시스템 구성 비트의 수이고, NP는 특정 비트와 쌍을 이룰 비트 수이고, NT는 구성 비트의 총 수이고,

는 TW를 가지는 스크럽 비율의 하한값이고, TW는 시간 윈도우이다.here,

Is the boundary cumulative error rate by the time window,

Is the configuration bit upset probability per unit device, Nb is the number of system configuration bits, NP is the number of bits to pair with a particular bit, NT is the total number of configuration bits,

Is the lower limit of the scrub ratio with TW, and TW is the time window.

To define the scrub ratio, first calculate Nb and NP. Nb is the number of configuration bits used to construct the circuit design. Even in complex designs, the number of LUTs used to construct the circuit is almost 30,000 LUTs. The ratio of configuration bits used for logic and routing is 2: 8, and even with XTMR, the Nb / NT ratio is almost 15% or less.

Based on this information, it is assumed below that an OBP system design using various signal processing such as signal filtering, waveform modulation / demodulation, and codec accounts for 15% of the Nb / NT ratio.

Obtaining NP values is also very complicated, so upper and lower limits are used to obtain approximate values. The design complexity is determined by the average value of the fan-out parameters, ie how much of the bit affects the number of mitigation windows. The fan-out may be estimated as in Equation 2 below.

Where φ is the average value of the fan-out and MW is the mitigation window.

In general, the larger the average fan-out value, the more advantageously a high speed circuit can be implemented, but the design is complex and the cumulative error rate is increasing. For fan-out = mitigation window, this corresponds to the upper limit of NP = 2/3 x Nb. That is, every pair of bits is in two other strings except the configuration bit string, including the view for that particular bit.

Therefore, it is impossible in reality because every bit affects all mitigation windows. In contrast, the lower limit means fan-out = 1 and the bit means that only one mitigation window is connected. This means dividing Nb by the number of relaxation windows. The upper limit and the lower limit of NP can be expressed by Equation 3 below.

The lower limit of the scrub ratio having a TW may be expressed by Equation 4 below.

When Equation 3 and Equation 4 are summed, Equation 5 may be expressed as Equation 5 below.

To demonstrate that the amount of cumulative error rate is affected by the scrub cycle, the cumulative error rate will be calculated as the scrub cycle changes.

)은 약 5오류 (

)이고, 수학식 4에 기반을 둔 스크럽 주기는 거의 14일이다.In the normal case of a spatial radiant environment,

) Is approximately 5 errors (

And the scrub cycle based on Equation 4 is almost 14 days.

FIG. 4 is a graph showing cumulative error rates based on Equation 1 on the assumption that the scrub cycle is an arbitrary value of 10, 14, 20, and 25 days. As can be seen in Figure 4, when the FPGA using blind scrubbing encounters the worst environment, the cumulative error rate can be seen to increase rapidly. However, as can be seen in Figure 4, this graph indicates that the shorter the scrub cycle (larger scrub rate), the lower the cumulative error rate, which can also affect the data processing performance of the OBP modem.

Another factor that increases or decreases the cumulative error rate is the number of mitigation windows. According to Equations 2 and 3, NP / NT values can be estimated according to the average fan-out number. By merging these two equations, a new definition of NP / NT can be defined by the following equation (6).

In order to check the correlation between the cumulative error rate and the mitigation window number, the fan-out number is fixed to 10, and the cumulative error rate depending on the mitigation window using the SEU error rate (configuration error rate) and Equations 1 and 6 is calculated.

FIG. 5 is a three-dimensional plot of cumulative error rate considering SEU error rate and number of mitigation windows. As shown in FIG. 5, a large number of mitigation windows may be a good mitigation scheme using an OBP modem, but as described above, system complexity In addition, the sensitivity of power consumption and system failure increases as the number of mitigation windows increases.

After calculating the cumulative error rate in step 200 described above, the performance predictor 30 predicts the performance of the OBP system through a parameter and a mathematical model applied to the step of mitigation and correction (300).

In the method of estimating the change in information throughput of an OBP satellite according to the change of space radiation environment having the above-described steps, a statistical space environment model is used to estimate an error rate of SRAM-based FPGA internal component bits generated by the SEU phenomenon. Mathematical models can be used to estimate how much SEU incidence, as a result of changes in the cosmic radiation environment, appears in the OBP system with error suppression and correction techniques.

Based on this result, it is possible to predict mathematically how the SEU phenomenon affects OBP performance by expressing the change of data throughput of OBP system according to the error rate of component bits.

As shown in FIG. 6, a modem for signal processing in an OBP satellite uses an SRAM-based FPGA and performs uplink data reception and downlink data transmission through a multibeam antenna. When protons and heavy ions distributed in space collide with SRAM-based FPGAs, they cause errors in configuration bits stored inside SRAM inside the device.

The OBP satellite modem system employs TMR, a mitigation technique for SEU, and periodic scrubbing, a modification technique, which reduces the SEU phenomenon that occurs directly and has the ability to correct configuration bit errors caused by the SEU phenomenon. .

However, during the time interval between before and after periodic scrubbing, the configuration bit error cannot be corrected. SRAM configuration bit errors in the building blocks for OBP satellite data processing will accumulate, leading to incorrect data processing or loss.

Accordingly, the present invention provides an SRAM configuration bit error rate that varies depending on the critical parameters (relaxation window size, mitigation window number, average fan-out number, configuration bit number used) and scrubbing cycle values of the correction method. It is a technique that expresses the data throughput of OBP system based on mathematical model that is represented, and it can be expressed quantitatively and also expressed as Bit Error Rate (BER) generated when OBP satellite data transmission.

In addition to quantitatively expressing the performance degradation of the OBP system, it is also possible to quantitatively change the OBP data throughput according to the change of various parameters applied to the mitigation and correction techniques. Can be expressed.

Accordingly, the OBP system performance can be calculated by linking the data throughput of the OBP system, which is dependent on the change in the flux and energy distribution of protons and heavy ions distributed in the space environment, with the parameter changes of the relaxation and correction techniques.

Prior studies and inventions focus only on the error rate at which cosmic radiation changes the information of configuration bits stored inside an SRAM-based FPGA, and studies on the error and degradation of performance in a practically applied system are inadequate.

However, the method of estimating the change of information throughput of OBP satellite according to the change of space radiation environment having the above-mentioned steps is to secure the stable broadband of the next generation communication satellite OBP system, which is shown as a solution to solve the saturation of the radio spectrum. In order to guarantee the performance, we propose a method for predicting the data throughput of OBP satellites due to the change of protons and heavy ions distributed in poor space environment, which is the first approach in the field of communication satellites.

In the method of estimating the change in information throughput of an OBP satellite according to the change in the space radiation environment having the above steps, the field random gate memory (FPGA) based on the Static Random Access Memory (SRAM) used in the implementation of the satellite communication system is the space radiation. Applied to the system structure to reduce the probability of system error caused by the change of the configuration bit value generated in the configuration memory when exposed to the environment, or generated by cosmic radiation when the SRAM-based FPGA is used as the modem processor of the OBP satellite. Implement a mathematical model to express the error of modem system as information throughput degradation of OBP system, and quantitatively express the performance change of OBP system implemented with SRAM-based FPGA that changes according to the change of space environment To build up.

As the frequency of signals used in communication satellites increases, processors used in OBP systems also require fast clock speeds and data processing capabilities. SRAM-based FPGAs are attracting attention as processors for communication satellites.

Accordingly, the method for estimating the change in information throughput of an OBP satellite according to the change in the space radiation environment having the above-described steps is to quantitatively express the performance change of the OBP system implemented by the SRAM-based FPGA according to the change in the space environment. In addition, it is possible to prepare a countermeasure using this, and by applying an optimal value that can cope with changes in the predicted space environment, the important parameters of the mitigation and correction methods used in the OBP system are applied. At the same time, it is possible to reduce the BER of the received downlink, and also to provide better quality communication services by applying parameters considering power consumption and complexity of the OBP system.

FIG. 7 is a flow chart illustrating the mitigation and modification steps in FIG. 3.

Referring to FIG. 7, the mitigation and correction step 100 first applies an XTMR design to an OBP system to mitigate an SEU phenomenon (110).

Global TMR (GTMR) is a concept of a TMR structure that includes the overall circuit design including the clock tree. Xilinx's GTMR implementation is called XTMR. As shown in FIG. 8, this structure includes one or more bit upsets in a string of configuration bits, which is one of three groups of logic circuits forming one relaxation window. It does not cause system failure even if it occurs. However, a system error may occur if a bit upset occurs in one or more configuration bits in which one configuration bit and the other bit are configured in pairs. This can be demonstrated as in Equation 7 below.

는 구성 비트이며,

는 쌍을 이룬 구성 비트이다.Where NT is the total number of configuration bits,

Is the configuration bit,

Is a pair of configuration bits.

는 특정

와 쌍을 이룬 비트 수이며, 이 비트가 하나의 완화 윈도우에 있을 때 동일한 중복 체인에서 두 비트 업셋이 발생하면 시스템 오류가 나타나지 않는다. 그러나 업셋이 다른 문자열의 특정 비트와 쌍을 이루는 비트를 생성하면 세 개의 문자열 중 두 개가 잘못된 출력을 생성하고 유권자는 올바른 출력을 생성할 수 없다. 이 잘못된 출력은 시스템 오류를 초래하고 아래의 수학식 8에서 설명될 수 있다.

Is certain

This is the number of bits paired with and if two bits upset occur in the same redundant chain when this bit is in one mitigation window, no system error appears. However, if the upset generates bits that are paired with specific bits in other strings, two of the three strings will produce incorrect output and voters will not be able to produce the correct output. This incorrect output causes a system error and can be described in Equation 8 below.

는 특정

와 쌍을 이룬 비트 수이다.here,

Is certain

Number of bits paired with.

The probability that bits are upset during a scrub cycle in an SRAM configurable memory with a relaxation window is defined as in Equation 9 below.

는 S 스크램블링 비율을 조건으로 하는 E 비트 업셋의 조건부 확률이고,

는 E 비트 업셋과 S 스크러빙 비율의 결합 확률이고,

는 스크럽 속도(scrub/day)이다.here,

Is the conditional probability of the E bit upset subject to the S scrambling rate,

Is the combined probability of the E bit upset and the S scrubbing ratio,

Is the scrub speed (scrub / day).

Changing the scrub ratio also changes the bit upset probability, so the two are not independent. The error rate that an SRAM-based FPGA is expected to accumulate during one scrub cycle may be defined as shown in Equation 10 below.

는 스크러빙이 발생할 때까지 얼마나 많은 구성 비트 오류가 발생할지를 나타낸다. 스크러빙 비율의 단위는 하루를 기준으로 한 스크럽이며, 비트 업셋의 확률은 하루 동안에 선형적으로 증가한다. 따라서, 1일 후에 정확하게 1비트가 뒤집힐 확률이 dE/dt이면, 하루 동안 선형적으로 증가하는 비트 업셋 확률은 다음의 수학식 11과 같이 연속 시간으로 해석될 수 있다The scrub cycle can be expressed as the scrub probability that a scrub can occur in a day, expressed in dC / dt. Likewise

Denotes how many configuration bit errors will occur until scrubbing occurs. The unit of scrubbing rate is scrub on a daily basis, and the probability of beat upset increases linearly throughout the day. Therefore, if the probability that 1 bit is flipped exactly after 1 day is dE / dt, the bit upset probability that increases linearly during the day may be interpreted as continuous time as in Equation 11 below.

는 하루 후 1 비트가 업셋될 확률이다.here,

Is the probability that one bit is upset after one day.

)은 다음의 수학식 12와 같이 요약될 수 있다.If all of the above equations are applied, the cumulative error rate (

) May be summarized as in Equation 12 below.

를 계산하는 것은 매우 복잡하므로, 다음의 수학식 13과 같이 표현된 각

에 대응한

의 평균수를 사용하기로 한다.all

Since it is very complicated to calculate, the angle represented by

Corresponding to

Let's use the average number of.

는 시스템 구성 비트의 수이다.here,

Is the number of system configuration bits.

The configuration bit upset probability is expressed in one device unit instead of one bit unit as shown in Equation 15 below.

는 한 장치 당 구성 비트 업셋의 확률이다.here,

Is the probability of the configuration bit upset per device.

After alleviating the SEU phenomenon at step 110, the blind scrubbing scheme is applied to correct the error due to the occurrence of the SEU (120).

FIG. 9 is a diagram illustrating a step of predicting the performance of the OBP system of FIG. 3.

Used in next generation satellite communication systems, OBP has a modem that handles data processing, which is implemented in SRAM-based FPGAs. The advantage of modems implemented in FPGAs is that they can handle 600 MHz of raw RF bandwidth, as well as design flexibility and data throughput of more than 2 Gbps.

SRAM-based FPGAs acting as data processors are very sensitive to the SEU of the configuration bits. The present invention attempts to show a change in system performance with the SEU ratio. It is assumed that the input and output data of the OBP system are processed continuously in pipeline format for continuous uplink and downlink transmissions.

For SRAM-based FPGAs used in the payload design of telecommunications satellites, a faulty circuit design occurs only when the configuration bits generated by the SEU access those bits for system operation. These errors produce bad output datagrams (or packets) and bad routing, resulting in bit error rates (BERs) and loss of output packets, resulting in poor data throughput.

In the following description, based on the above information, the effect of changing the SEU ratio on the data processing performance of the OBP system will be analyzed.

Referring to FIG. 3, the step 300 of calculating the performance of the OBP system is a mathematical representation of an SRAM configuration bit error rate that varies depending on the parameters and scrubbing period values that are applied to the mitigation and modification of step 100 described above. Create a model (310).

In an embodiment, the parameter applied to the mitigation technique may include at least one or more of a relaxation window size, a relaxation window number, an average fan-out number, or a configuration bit number used.

After generating the mathematical model in step 310 described above, the data performance of the OBP system is expressed as a formula (320) as described below.

In one embodiment, the data performance G of the OBP system is 2 Gbps, and the SRAM-based FPAG used for the modem may have a 200 MHz clock rate (F).

Assuming that the data processing capability of the OBP modem is 2Gbps and the SRAM-based FPAG used in the modem has a 200MHz clock speed, the expected data performance per clock processed per clock can be expressed as Equation 16 below.

Where G is the data performance of the OBP system, F is the SRAM-based FPAG clock speed used in the modem, and b is the number of bits processed per clock.

In actual OBP system operation, the access ratio of each SRAM configuration bit is different, but it is not possible to analyze the access ratio of all bits.

Therefore, in the present invention, when the SEU affects the data processing performance, the lower limit BER is expressed to calculate the average access ratio using the raw approach. Using the raw approach, the expected bit access rate is given by Equation 17 below.

는 1 클럭 당 SEU 비트를 액세스할 확률을 나타낸다.Where n is the configuration bit where the SEU has occurred, Nb is the number of system configuration bits,

Denotes the probability of accessing the SEU bit per clock.

에 b를 곱하면 1 클럭 당 예상 처리량 손실이 발생하는데, 이것은 얼마나 많은 SEU 비트가 OBP 시스템 성능에 영향을 미치는지를 지정한다. 위에서 언급했듯이 Nb/NT는 약 0.15이고 NT는 44,601,149이데, 이 수를 사용하여 Nb의 수가 6,690,172라고 가정할 수 있다.

Multiplying by b results in an expected loss of throughput per clock, which specifies how many SEU bits affect OBP system performance. As mentioned above, Nb / NT is about 0.15 and NT is 44,601,149. Using this number, we can assume that the number of Nb is 6,690,172.

The bit upset rate that causes the system error is the cumulative error rate given in Table 4, which will be described later. Table 4 can show the cumulative error rate that depends on the change in the radiation environment specified in FIG.

를 계산하기 위해, 시스템 오류에 영향을 미치는 업셋 비율인

를 n으로 설정 한 다음, 데이터 처리를 수행하는 반전된 비트(n)를 읽는 액세스 비율이 F(FPGA 클럭 속도, 200MHz) ×

임을 예측할 수 있다.

To calculate the

Is set to n, and then the access rate of reading the inverted bit (n) to perform data processing is F (FPGA clock rate, 200 MHz) ×

Can be predicted.

Using these results, the loss of data throughput can be estimated as shown in Equation 18 below.

는 초당 데이터 처리량의 손실이다.here,

Is a loss of data throughput per second.

(데이터 처리 성능, 2Gbps)에서 하한 BER을 추정할 수 있는데, 방사선 환경에 대한 하한 BER의 결과는 표 1에 나타나 있다.Finally

The lower limit BER can be estimated at (Data Processing Performance, 2Gbps), and the results of the lower limit BER for the radiation environment are shown in Table 1.

Computing the performance of the OBP system having the configuration as described above (300), as shown in Table 4, quantitatively represents the data performance of the OBP system expressed as a formula and at the same time occurs during the data transmission of the OBP satellite It may further include a step 330 to be expressed as BER.

으로부터 하한 BER를 예측할 수 있다.In one embodiment, the step of expressing BER, as described above

The lower limit BER can be predicted from.

The OBP system consists of an SRAM-based FPGA. For next-generation communication satellites, SEU's data processing performance needs to be considered in space. Radiation environments can overturn SRAM memory and generate system errors due to circuit design changes in SRAM-based FPGAs.

Thus, step 300 of calculating the performance of an OBP system having the steps described above attempts to estimate the SEU ratio associated with solar activity, which will generate LUT errors and routing errors and impair the operation of the communications satellite's mission. Can be.

Apply XTMR design and blind scrubbing schemes to OBP systems before calculating OBP data throughput to mitigate and resolve SEU situations, and use these SEU mitigation concepts and SEU ratio prediction results to calculate the cumulative error rate on SRAM-based FPGAs. Then, finally, the lower limit of BER performance can be calculated in the OBP modem.

As shown in Table 1, there is no BER in OBP data processing performance when the radiation environment is normal, but BER may be predicted in OBP data processing performance when the radiation environment is worst.

Although the above has been described with reference to the embodiments, those skilled in the art will understand that various modifications and changes can be made without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

1: Prediction device for changes in information throughput of OBP satellites due to changes in space radiation environment
10: mitigation
20: error rate calculation unit
30: performance prediction unit

Claims (11)

Mitigating and correcting the occurrence of SEU in the system of the OBP satellite modem;
Calculating a cumulative error rate occurring in the SRAM-based FPGA through error correction using mitigation and correction; And
Predicting the performance of the OBP system through parameters and mathematical models applied to the mitigation and correction steps,
Predicting the performance of the OBP system,
Generating a mathematical model representing an SRAM configuration bit error rate that varies according to a change in a parameter and a scrubbing period value applied to the mitigation and correction steps. Forecast method.
The method of claim 1, wherein the mitigating and modifying,
Applying an XTMR design to the OBP system to mitigate the SEU phenomenon; And
A method of predicting a change in information throughput of an OBP satellite according to a change in space radiation environment, comprising applying a blind scrubbing scheme to correct an error due to the occurrence of an SEU.
The method of claim 1, wherein predicting the performance of the OBP system,
And a method of mathematically expressing data performance of an OBP system through the mathematical model.
The method of claim 3,
The parameter may include at least one or more of a relaxation window size, a relaxation window number, an average fan-out number, and a configuration bit number to be used.
The method of claim 3,
The data performance (G) of the OBP system is 2Gbps, SRAM-based FPAG used in the modem has a 200MHz clock speed (F), characterized in that the information processing variation of the OBP satellite according to the change in the space radiation environment.
The method of claim 5,
Data performance (G) of the OBP system is,

(Where b is the number of bits processed per clock) of OBP satellite information processing change prediction method according to the space radiation environment changes.
The method of claim 6,
Loss of data throughput (

) Is the equation

(remind

(B) a probability of accessing SEU bits per clock).
The method of claim 7, wherein
remind

Is the equation

(N is the configuration bits from which the SEU is generated, and Nb is the number of system configuration bits).
The method of claim 3, wherein predicting the performance of the OBP system,
In addition, the data throughput of the OBP system, which is expressed in a quantitative manner, is expressed in BER generated during data transmission of the OBP satellite. Forecast method.
The method of claim 9, wherein the step of expressing with BER,

A method for predicting change in information throughput of an OBP satellite according to a change in space radiation environment, characterized by estimating a lower limit BER from.
Mitigations that mitigate and correct the occurrence of SEU in systems of OBP satellite modems;
An error rate calculator that calculates a cumulative error rate occurring in the SRAM-based FPGA through error correction using mitigation and correction; And
It includes a performance prediction unit for predicting the performance of the OBP system through the parameters and mathematical models applied to the mitigation correction,
The performance predictor,
An apparatus for predicting information throughput change of an OBP satellite according to a change in space radiation environment, characterized by generating a mathematical model representing an SRAM configuration bit error rate that varies depending on a parameter applied to the mitigation correction unit and a scrubbing period value.

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