KR102007881B1 - Method and system for fast and accurate cycle estimation through hybrid instruction set simulation - Google Patents

Abstract

The present invention relates to a simulation technique, and more particularly, to a hybrid instruction set simulation method and system for predicting through the simulation the execution time of software operating in an embedded system.
According to the present invention, even for complex software using various hardware, the execution time of the processor is calculated using the extension of the Quick Emulator (QEMU), and the extension to the other hardware using the extension of the Open Virtual Platform simulator (OVPsim). After calculating the execution time required for use, you can combine the two results to get more accurate execution time predictions.

Description

Hybrid Instruction Set Simulation Method and System for Fast and Accurate Execution Time Estimation {METHOD AND SYSTEM FOR FAST AND ACCURATE CYCLE ESTIMATION THROUGH HYBRID INSTRUCTION SET SIMULATION}

The present invention relates to a simulation technique, and more particularly, to a hybrid instruction set simulation method and system for predicting through the simulation the execution time of software operating in an embedded system.

Real-time system refers to a system in which each software is executed within a predetermined time limit. In a real-time system, the execution time of the software is a very important factor in ensuring system performance.

Since software execution time is very different depending on the hardware that makes up the system, you should measure the execution time by using both software and hardware together to get accurate results. But building systems with real hardware and analyzing software performance can be very time consuming and expensive. Techniques for analyzing software performance through simulators that simulate the behavior of hardware are widely used to save time and money.

Representative simulators utilize Instruction Set Simulation technology. This simulates each instruction function of a specific hardware in software, enabling the execution of software designed to operate on that hardware without the actual hardware.

It has much faster execution speed than Cycle Accurate Simulation, and enables full system simulation by simulating hardware other than processor, such as memory, disk, and network.

Recently, software execution time estimation techniques based on such instruction set simulation have been proposed. These technologies are evolving toward higher accuracy of runtime prediction, such as considering caches based on processor models, or combining processor models with worst-case execution time analysis techniques.

However, despite these attempts, it is still difficult to achieve high accuracy in software runtime analysis. This is because software uses a variety of hardware resources such as cache, bus, memory, and disk, whereas simulation-based performance analysis techniques are not sufficient.

Simulating the behavior of hardware resources that affect software execution time, modeling how each resource's behavior affects execution time, and estimating execution time based on the diversity and / or complexity of hardware resources It is difficult.

1. Korean Patent Publication No. 10-2014-0140789

1. Eun Hye Kim, "A Study on the Prediction Model of Job Execution Time Based on Parallel Program Log Clustering" v.38 n.3 (2015. 9) pp.56-63 2. Soo-Hyun Yang et al., "A Study on the Performance Evaluation of Mobile Computers Using OVPsim" Korea Information Processing Society, 2011

The present invention has been proposed to solve the problems according to the above background, and an object thereof is to provide a hybrid instruction set simulation method and system for developing a software execution time prediction technique based on instruction set simulation.

In addition, another object of the present invention is to provide a hybrid instruction set simulation method and system capable of obtaining fast and accurate execution time prediction results even when a software uses various hardware resources.

The present invention provides a hybrid instruction set simulation method for developing a software execution time prediction technique based on the instruction set simulation to achieve the above problems.

The hybrid instruction set simulation method,

(a) receiving, by the target binary input unit, the target binary code;

(b) an extended Quick Emulator (QEMU) module converting the target binary code into a first machine instruction to execute an instruction set simulator to calculate a request cycle for a processor;

(c) an expanded Open Virtual Platform simulator (OVPsim) module converting the target binary code into a second machine instruction to execute an instruction set simulator to calculate event statistics for surrounding hardware; And

and (d) a cycle evaluation engine calculating execution time prediction using the request cycles and event statistics for the processor.

At this time, in the step (b), the request cycle for the processor is a request cycle for each code block of the target binary code calculated using a processor pipeline model and each code block executed at least once in the target binary code. It may be characterized in that the final calculation through the number of times of execution.

In addition, in the step (c), the event statistics may be calculated using a hardware operation model, and the hardware operation model may be configured with peripheral hardware modeling APIs.

In addition, the peripheral hardware modeling API may be characterized by including a behavioral hardware modeling (BHM) API, a Peripheral Programming Model (PPM) API.

The step (b) may further include storing the first machine instruction in a cache for reuse.

In addition, the conversion from the target binary code to the machine instruction code is performed by a Just-In-Time (JIT) compilation method or a dynamic binary conversion technique, and may be characterized in that the conversion is performed at the moment the instruction is executed. .

The instruction set simulator may be executed on a host machine.

On the other hand, another embodiment of the present invention, a target binary input unit for receiving a target binary code; An extended QEMU (Quick Emulator) module for converting the target binary code into machine instructions to execute an instruction set simulator to calculate a request cycle for a processor; An extended OVPsim (Open Virtual Platform simulator) module for converting the target binary code into a second machine instruction to execute an instruction set simulator to calculate event statistics for peripheral hardware; And a cycle evaluation engine configured to calculate an execution time prediction using the request cycle for the processor and the event statistic.

 According to the present invention, even for complex software using various hardware, the execution time of the processor is calculated using the extension of the Quick Emulator (QEMU), and the extension to the other hardware using the extension of the Open Virtual Platform simulator (OVPsim). After calculating the execution time required for use, you can combine the two results to get more accurate execution time predictions.

In addition, the QEMU is open-source in the case of QEMU, so it is free to expand, making it easy to implement complex processor models and execution time measurement techniques, and in the case of OVPsim, various hardware affecting software execution time Because we already provide simulations of resources, it is easy to implement the runtime measurement techniques required for the use of other hardware.

In addition, another effect of the present invention is that it shows a more accurate result than the current technology, and has the advantage that it is easy to expand for various hardware.

In addition, another effect of the present invention is to extend and / or combine existing instruction set simulators to quickly and accurately predict execution time of complex software requiring various resources, thereby improving software and hardware design. This is expected to have a significant effect on the time and cost required.

1 is a diagram illustrating the concept of a quick emulator (QEMU).
2 is a view showing the concept of OVPsim (Open Virtual Platform simulator).
3 is a block diagram of a hybrid instruction set simulation system 300 according to an embodiment of the present invention.
4 is a flowchart illustrating a hybrid instruction set simulation process according to an embodiment of the present invention.
5 is a graph comparing measurement results of Fibonacci numbers using only the QEMU and the hybrid method according to an embodiment of the present invention.
FIG. 6 is a graph comparing measurement results of matrix multiplication according to a hybrid method according to an embodiment of the present invention with only QEMU.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all changes, equivalents, and substitutes included in the spirit and scope of the present invention.

In describing each drawing, like reference numerals are used for like elements.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component. The term “and / or” includes any combination of a plurality of related items or any item of a plurality of related items.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art.

Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art, and are not construed in ideal or excessively formal meanings unless expressly defined in this application. Should not.

Hereinafter, a hybrid instruction set simulation method and system for fast and accurate execution time prediction according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

In one embodiment of the present invention, the hybrid instruction set simulation method includes: 1) a processor pipeline model and an execution time measurement technique that extends a Quick Emulator (QEMU); 2) other hardware models and runtime measurement techniques that extend the Open Virtual Platform simulator (OVPsim); 3) It includes total system execution time measurement technique combining QEMU (Quick Emulator) and OVPsim (Open Virtual Platform simulator).

1 is a diagram illustrating the concept of a quick emulator (QEMU). Referring to FIG. 1, the QEMU system 100 includes a target binary input unit 110, a conversion execution module 120 for converting and executing a target binary code, and an execution result output module for outputting an execution result of the converted target binary code ( 130) and the like.

The target binary input unit 110 receives a target binary code (ie, a file) for a processor to be tested.

The conversion execution module 120 converts the target binary into host processor instructions so that the target binary code is executed on the host machine.

To this end, the conversion execution module 120 takes the converted code block and executes it on the host machine, the code executor 212, the dynamic binary converter 214 for converting the code block taken from the target binary code into the host machine instruction code, conversion And a code cache unit 213 for storing the converted code block for reuse of the used code block.

The code executor 212 identifies the target code block, which is the next set of instructions to execute from the target binary code. At this time, if the code block is already converted and stored in the code cache unit 213, the converted code block stored in the code cache unit is executed. At this time, if the converted code block is not stored in the code cache unit, the dynamic binary converter 214 is called for code conversion.

The dynamic binary converter 214 converts the target target code block into a host machine instruction code block, and stores all the converted machine instruction code in the code cache unit 213 to increase the simulation speed.

When execution of all target binaries input from the target binary input unit 110 is finished, a target binary execution result may be obtained from a host machine (not shown). The host machine refers to a device used in the embedded program development process to simulate (simulate) a processor.

For this purpose, dynamic binary translation technology or just-in-time compilation method is used. Dynamic binary conversion or just-in-time compilation is performed in two stages. First, the target binary code is converted into basic block units, and the instructions inside the basic block are converted to intermediate code (Intermediate Representation, IR). Are converted to multiple micro operations. The converted IR is converted into host instructions and registers are generated by machine instruction code.

2 is a view showing the concept of OVPsim (Open Virtual Platform simulator). Referring to FIG. 2, the OVPsim system 200 generates a target binary input unit 210, an engine generation module 220 that generates and executes a peripheral simulation engine according to the target binary code, and executes execution results of the target binary code in the peripheral simulation engine. It may be configured to include a running result output module 230 to output.

The target binary input unit 210 performs a function of receiving a target binary code (ie, a file) for a processor to be tested.

Engine generation module 220 generates virtual machine runtime 221 via platform builder 222 to execute this target binary code, and peripheral device in this virtual machine runtime 221 via peripheral simulation engine 223. Allows you to simulate the behavior of.

To this end, the engine generation module 220 includes a virtual machine runtime unit 221 that mimics the target machine based on a hardware model of hardware mounted on the target machine, and a platform maker 222 that generates a virtual platform for the virtual machine runtime. And a peripheral simulation engine 223 that mimics the operation of various peripheral hardware.

The target binary input through the target binary inputter 210 is converted into a host machine instruction by the virtual machine runtime 221 of the engine generation module 220 and executed.

At this time, the peripheral simulation engine 223 simulates peripheral devices (eg, memory, storage, audio / video, network, etc.) used in the embedded hardware.

At this time, the peripheral simulation engine uses hardware modeling APIs such as behavioral hardware modeling (BHM) API and peripheral programming model (PPM) API to simulate peripheral devices.

At this time, if a peripheral device is used in the converted target binary, the converted target binary uses the peripheral device simulated by the peripheral simulation engine 223.

3 is a block diagram of a hybrid instruction set simulation system 300 according to an embodiment of the present invention. Referring to FIG. 3, in order to accurately analyze execution time of software utilizing various hardware of the entire system, multiple simulators 320a and 320b are simultaneously used to predict execution time.

Referring to FIG. 3, the hybrid instruction set simulation system 300 executes a request cycle for a processor by executing a instruction set simulator by converting the target binary code into a target binary input unit 310 that receives a target binary code, and converting the target binary code into a machine instruction. An extended QEMU module 320a for calculating, an extended OVPsim module 320b for converting the target binary code into a second machine instruction, and executing an instruction set simulator to calculate event statistics about peripheral hardware; and And a cycle evaluation engine 330 for performing execution time prediction by adding up a first execution time according to a request cycle for a processor and a second execution time according to the event statistics.

Depending on the type of hardware resources, the simulator is used to measure the hardware execution time. As shown in FIG. 3, in order to precisely model a processor having a complex operating characteristic, an open-source extended QEMU module 320a is used to measure processor usage time, and to use other hardware resources. In order to measure time consumption, the extended OVPsim module 320b that provides various hardware resource models internally is used.

The instruction set simulator is run on the host machine, which reads software compiled for the target machine and converts the target machine instructions from the software into host machine instructions.

The JIT or dynamic transformation based simulator, represented by the extended QEMU module 320a, is transformed at the moment the instruction is executed for efficiency, and the transformed transformation instruction is stored and reused in the code cache 323.

In other words, the extended QEMU module 320a performs a function of receiving a target binary code (ie, a file) for the processor to be tested by the target binary inputter 310.

Accordingly, the extended QEMU module 320a performs a function of performing conversion into host processor instructions so that the target binary input from the target binary input unit 310 is executed on the host machine. To this end, the extended QEMU module 320a may include a code executor 321, a code cache unit 323, a dynamic binary converter 324, and the like.

In this case, the code executor 321 includes a cycle counter 321-1 for counting the number of cycles.

Dynamic binary converter 324 also includes a processor pipeline model 324-1.

That is, the extended QEMU module 320a has two additional components. In other words, one is processor pipeline model 324-1 and two are cycle counters 321-1. The dynamic binary converter 324 calculates a request cycle for each code block of the target binary code through the processor pipeline model 324-1. In other words, the required cycle for each target instruction is calculated, resulting in a required cycle for each code block of the target binary code.

The code executor 321 counts the number of executions for each code block through the cycle counter 321-1. Since the request cycles for each code block are calculated by the processor pipeline model 324-1, calculating the number of executions of each code block through the cycle counter 321-1, the total cycles when the entire target binary is executed. Can calculate the number At this time, each block of code may be executed one or more times due to the effects of the loop statement.

In other words, in one embodiment of the present invention, the structure of the QEMU shown in FIG. 1 is extended to calculate processor execution cycles required for the processor to complete execution of software. That is, the target machine processor pipeline model 324-1 is added to the code conversion portion of the simulator to calculate and store execution cycles required for execution of each target machine instruction. After that, each time the machine instruction codes converted into host machine instructions are executed, the number of executions of each code is measured. Then, the total execution cycle of the entire software (ie, target binary code) is estimated based on the required execution cycle and the number of execution for each code.

At this time, since the number of cycles that can be executed per unit time for each processor is fixed, the total execution time of the target binary can be calculated based on the total execution cycles.

The full-system simulator enables the operation of software using the hardware without the actual hardware through simulation of various resources used by the software. The system unit simulator, represented by OVPsim, provides an operation model for various hardware resources such as cache, translation look aside buffer (TLB), memory, and disk, which affects execution time.

To this end, in an embodiment of the present invention, the extended OVPsim module 320b is configured. The extended OVPsim module 320b has two additional components than the configuration shown in FIG. That is, the cache / TLB event counter 32-1 and the peripheral event counter 34-1 are further configured.

The cache / TLB event counter 32-1 is configured in the housekeeping machine runtime unit 32 and performs a function of capturing important events such as cache hit / miss and TLB hit / miss. In particular, memory component modeling is performed through a virtual machine interface (VMI). In particular, the cache / TLB event counter 32-1 is performed inside the virtual machine runtime of the virtual machine runtime unit 32, captures events from the cache and the TLB, and generates these event statistics to generate the cycle evaluation engine 330. To transmit.

In addition, the peripheral event counter 34-1 captures events generated from the peripheral hardware, generates event statistics, and sends them to the cycle evaluation engine 330. The peripheral event counter 34-1 also captures these events using a hardware behavior model.

The hardware behavior model is implemented with a peripheral hardware modeling application programming interface (API). Such peripheral hardware modeling APIs include behavioral hardware modeling (BHM) APIs and peripheral programming model (PPM) APIs. The ambient event counter 34-1 is performed inside the ambient simulation engine 34.

In other words, the hardware behavior model provided by the system unit simulator can be used to calculate the execution time required when the software uses hardware resources. The execution time required for each hardware is calculated by storing the number of events (eg cache hit / miss) and multiplying the required execution cycle for each known event.

The cycle evaluation engine 330 collects the request cycles 331 and event statistics 332 for the processor from the extended QEMU module 320a and the extended OVPsim module 320b from the extended QEMU module 320a, respectively, to calculate the execution time prediction. do.

At this time, the cycle evaluation engine 33 calculates the execution time required for using the peripheral device based on the event cycle and the execution cycle requirement for each event based on each hardware specification.

4 is a flowchart illustrating a hybrid instruction set simulation process according to an embodiment of the present invention. Referring to FIG. 4, the target binary input unit 310 receives a target binary code (step S410).

Thereafter, the process of measuring the processor usage time (steps S420 to S423) and the process of measuring other hardware resource usage time (steps S430 to S435) are simultaneously performed.

First, the process of measuring the processor usage time, the extended QEMU (Quick Emulator) module 320a executes the target binary code code, converts the target binary code into a machine instruction to execute the instruction set simulator to calculate the request cycle for the processor (Steps S420, S421, S423).

In the process of measuring other hardware resource usage time, the extended Open Virtual Platform Simulator (OVPsim) module 320b executes the target binary code on the virtual machine, creates the virtual platform, and converts it into machine instructions. Event statistics are calculated for the peripheral hardware by executing (steps S430, S431, S433, S435).

Thereafter, the cycle evaluation engine 330 calculates an execution time prediction using the request cycle for the processor and event statistics (step S440).

5 is a graph comparing measurement results of Fibonacci numbers using only the QEMU and the hybrid method according to an embodiment of the present invention. Referring to FIG. 5, the results of the sole QEUM represent a very accurate cycle estimate, and are similar to the results of the hybrid scheme according to an embodiment of the present invention.

The exact result of a single QEUM on Fibonacci number benchmarks shows that the proposed processor pipeline model can accurately estimate the cycles required for a processor.

FIG. 6 is a graph comparing measurement results of matrix multiplication according to a hybrid method according to an embodiment of the present invention with only QEMU. Referring to FIG. 6, the estimation accuracy of a single QEMU is reduced as the matrix size increases. In contrast, the hybrid scheme according to one embodiment of the present invention shows more accurate cycle estimation.

100: QEMU (Quick Emulator) system
110,210,310: Target Binary Input Method
120,220: Transform Execution Module
130,230: execution result output module
200: Open Virtual Platform simulator (OVPsim) system
320a: extended QEMU (Quick Emulator) module
320b: Extended Open Virtual Platform simulator (OVPsim) module
330 cycle evaluation engine

Claims (8)

(a) receiving, by the target binary input unit, the target binary code;
(b) an extended Quick Emulator (QEMU) module converting the target binary code into a first machine instruction to execute an instruction set simulator to calculate a request cycle for a processor;
(c) an expanded Open Virtual Platform simulator (OVPsim) module converting the target binary code into a second machine instruction to execute an instruction set simulator to calculate event statistics for surrounding hardware; And
(d) a cycle evaluation engine calculating execution time prediction using the demand cycles and event statistics for the processor;
In step (b), the request cycle for the processor is a request cycle for each code block of the target binary code calculated using a processor pipeline model and execution of each code block executed at least once in the target binary code. Hybrid instruction set simulation method for fast and accurate execution time estimation, characterized in that the final calculation through the count.
delete The method of claim 1,
In the step (c), the event statistics are calculated using a hardware operation model, the hardware operation model is a hybrid command for fast and accurate execution time prediction, characterized in that consisting of a hardware modeling API (Application Programming Interface) Set simulation method.
The method of claim 3, wherein
The peripheral hardware modeling API is a hybrid instruction set simulation method for fast and accurate execution time prediction, characterized in that consisting of Behavioral Hardware Modeling (BHM) API, Peripheral Programming Model (PPM) API.
The method of claim 1,
The step (b) further comprises the step of storing the first machine instructions in the cache for reuse; hybrid instruction set simulation method for fast and accurate execution time prediction, characterized in that it further comprises.
The method of claim 1,
The conversion from the target binary code to the machine instruction code is performed by a Just-In-Time (JIT) compilation method or a dynamic binary conversion technique. Hybrid instruction set simulation method for prediction.
The method of claim 1,
And the instruction set simulator is executed on a host machine.
A target binary input unit for receiving a target binary code;
An extended QEMU (Quick Emulator) module for converting the target binary code into machine instructions to execute an instruction set simulator to calculate a request cycle for a processor;
An extended OVPsim (Open Virtual Platform simulator) module for converting the target binary code into a second machine instruction to execute an instruction set simulator to calculate event statistics for peripheral hardware; And
And a cycle evaluation engine configured to calculate execution time prediction using the request cycles for the processor and the event statistics.
The request cycle for the processor is finally calculated through a request cycle for each code block of the target binary code calculated using a processor pipeline model and the number of executions of each code block executed at least once in the target binary code. Features a hybrid instruction set simulation system for fast and accurate execution time prediction.

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