KR101981212B1 - Single inductor multiple output direct current-to-direct current converter and operating method thereof - Google Patents

Abstract

A converter according to an embodiment of the present invention includes a single inductor that stores input energy, a ground switch that provides a ground path for the inductor, an inductor switch that holds energy stored in the inductor, output switches that transfer energy stored in the inductor to multiple outputs , And a controller of the switches. The switch controller may generate switch control signals to determine interference between multiple outputs to reduce interference between multiple outputs. According to the present invention, it is possible to provide a single inductor multi-output DC-DC converter that reduces interference between multiple outputs.

Description

[0001] SINGLE INDUCTOR MULTIPLE OUTPUT DIRECT CURRENT-TO-DIRECT CURRENT CONVERTER AND OPERATING METHOD THEREOF [0002]

The present invention relates to a DC-DC converter, and more particularly, to a single inductor multi-output DC-DC converter and a method of operation thereof.

The dc-to-dc converter takes the DC voltage and boosts or downsteps the output to the required stable voltage. 2. Description of the Related Art In recent years, various types of electronic devices have increased in function, or include a plurality of devices each using a different voltage, requiring a multiple output DC-DC converter. The multi-output DC-DC converter is a multi-inductor multi-output (MIMO) DC-DC converter, or a single inductor multi-output (SIMO) DC-DC converter. The multi-inductor multi-output dc-to-dc converters use inductors as many as the number of outputs, resulting in an increase in area and cost.

A single inductor multi-output dc-to-dc converter can reduce area and cost by using only a single inductor compared to a multi-inductor multi-output dc-dc converter. In addition, a single inductor multi-output DC-DC converter may be required in a battery-powered electronic device such as a wearable device or a smart phone. Despite the advantages described above, a single inductor multi-output DC-DC converter has a problem that cross regulation between outputs occurs due to the use of a single inductor.

It is an object of the present invention to provide a single inductor multi-output DC-DC converter with reduced output-to-output interference and an operation method thereof.

A single inductor multi-output DC-DC converter according to an embodiment of the present invention includes an inductor that stores an input energy, a ground switch that provides a ground path of the inductor in response to a first signal, An output switch for outputting energy stored in the inductor in response to the third signals to the multiple output voltages, and an output switch for determining the interference between the multiple output voltages, And a switch controller for generating third to third signals.

A method of operating a single inductor multi-output DC-DC converter in accordance with an embodiment of the present invention includes the steps of: monitoring voltages at multiple outputs; determining whether voltages are outside a predetermined voltage range; Determining whether interference between multiple output voltages occurs, and controlling the pulse widths of the switches of the DC-DC converter.

The DC-DC converter according to the embodiment of the present invention can reduce the interference between the output voltages by measuring the interference between the output voltages.

1 is a block diagram illustrating an exemplary DC-DC converter according to an embodiment of the present invention.
FIG. 2 is a block diagram illustrating an exemplary switch controller of FIG. 1. Referring to FIG.
3 is a timing diagram illustrating an exemplary operation of the first hysteresis comparator shown in FIG.
4 is a block diagram illustrating an exemplary first hysteresis comparator of FIG. 2;
5 is a flow chart showing the operation of the voltage rise time controller shown in FIG.
FIG. 6 is a block diagram illustrating an exemplary pulse generator shown in FIG. 2. FIG.
FIGS. 7A and 7B are timing diagrams illustrating the operation of the pulse generator shown in FIG. 6; FIG.
FIG. 8 is a block diagram illustrating an exemplary ground switch controller shown in FIG. 2. FIG.
FIG. 9 is a block diagram illustrating an exemplary inductor switch controller shown in FIG. 2. FIG.
FIGS. 10A to 10C are block diagrams illustrating the first to third output switch controllers shown in FIG. 2. FIG.
11 is a flowchart showing an operation method of the DC-DC converter shown in FIG.
FIG. 12 is a flowchart for specifically explaining step S230 shown in FIG.
Figs. 13A and 13B are timing diagrams illustrating the operation of the DC-DC converter shown in Fig. 1. Fig.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: FIG. The embodiments according to the concept of the present invention can make various changes and can take various forms, so that the embodiments are illustrated in the drawings and described in detail herein. It should be understood, however, that it is not intended to limit the embodiments according to the concepts of the present invention to the particular forms disclosed, but includes all modifications, equivalents, or alternatives falling within the spirit and scope of the invention. Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the meaning of the context in the relevant art and, unless explicitly defined herein, are to be interpreted as ideal or overly formal Do not.

1 is a block diagram illustrating an exemplary DC-DC converter according to an embodiment of the present invention. 1, a DC-DC converter 1000 includes an inductor 1100, a ground switch 1200, an inductor switch 1300, output switches 1400 corresponding to multiple outputs, and a switch controller (1500). DC-DC converter 1000 can store energy through input VI and transfer energy to multiple outputs. In FIG. 1, multiple outputs can be modeled as capacitors (CO1, CO2, ..., COx) and current sources (IO1, IO2, ..., IOx).

The inductor 1100 may be coupled between the input terminal VI and the output switches 1400. When an external voltage is applied to the input terminal (VI), the current of the inductor (1100) increases and external energy can be stored. Due to the operation of the switches to be described later, the energy stored in the inductor 1100 can be transferred to multiple outputs.

The ground switch 1200 may be coupled between ground and the inductor 1100 to provide grounding of the inductor 1100. For this, the ground switch 1200 may use a single NMOS (N-Channel Metal Oxide Semiconductor). When the inductor 1100 stores energy, the ground switch 1200 is turned on under the control of the ground switch control signal GN (first signal) to provide a connection path between the inductor 1100 and ground do. The ground switch 1200 can prevent the energy stored in the inductor 1100 from being transmitted to multiple outputs.

The inductor switch 1300 may be connected in parallel with the inductor 1100. To this end, the inductor switch 1300 may use a single PMOS (P-Channel Metal Oxide Semiconductor). When the inductor switch 1300 is turned on in accordance with the control of the inductor switch control signal GF and the second signal, the inductor switch 1300 can equalize the voltage difference across the inductor 1100. [ Thus, the inductor switch 1300 can maintain the current of the inductor 1100 constant. Thus, the inductor switch 1300 can transmit multiple outputs and store the remaining energy in the inductor 1100 continuously. The inductor switch 1300 may be called a freewheel switch.

Output switches 1400 may be coupled between the inductor 1100 and the output. By means of the output switch control signals G1, G2, ..., Gx, the third signals, the output switches 1400 can provide a path between the inductor 1100 and the multiple outputs. To this end, each switch of the output switches 1400 may use a single PMOS.

The switch controller 1500 can generate control signals GN, GF, G1, G2, ..., Gx to control the ground switch 1200, the inductor switch 1300, and the output switches 1400 . For this purpose, the switch controller 1500 can receive the output voltages VO1, VO2, ..., VOx of the output.

The switch controller 1500 can receive an external clock CLK and a communication signal COM. The switch controller 1500 uses the clock signal CLK and the communication signal COM to control the reference voltage of each output, the upper limit voltage of each output, the lower limit voltage of each output, the occurrence of interference between each output, You can set the initial pulse width.

Here, the reference voltage is a target voltage of the output voltage. The upper limit voltage may mean a variable voltage magnitude that may be higher than the target voltage. The lower limit voltage may mean a fluctuating voltage magnitude that may be lower than the target voltage. The reference upper limit voltage may mean the reference voltage plus the upper limit voltage. The reference lower limit voltage may mean the reference voltage minus the lower limit voltage. Hereinafter, the range between the reference upper limit voltage and the reference lower limit voltage is referred to as a predetermined voltage range. That is, the dc-to-dc converter 1000 can drive multiple output voltages so as to fluctuate within a predetermined voltage range.

Hereinafter, the present invention will be described with respect to a case where the number of multiple outputs in a single inductor multi-output DC-DC converter is three. Thus, multiple output voltages may exist up to VO1, VO2, and VO3, and the control signals of output switches 1400 may be up to G1, G2, and G3.

FIG. 2 is a block diagram illustrating an exemplary switch controller of FIG. 1. Referring to FIG. Referring to FIG. 2, the switch controller 1500 includes a first hysteresis comparator 1510a, a second hysteresis comparator 1510b, a third hysteresis comparator 1510c, a voltage rise time controller 1520, a pulse generator 1530, a ground switch controller 1540, an inductor switch controller 1550, a first output switch controller 1560a, a second output switch controller 1560b, a third output switch controller 1560c, And a setting circuit 1570.

The first hysteresis comparator 1510a includes a first output voltage VO1, a reference voltage VREF1 generated by the setting circuit 1570, an upper limit voltage VH1 generated by the setting circuit 1570, 1570 may generate a hysteresis output HO1 by receiving the lower limit voltage VL1.

The hysteresis output HO1 of the first hysteresis comparator 1510a may become HIGH when the first output voltage VO1 is higher than or lower than the reference lower voltage VREF1-VL1, And may be low when the first output voltage VO1 is lower than the reference upper limit voltage VREF1 + VH1 and becomes higher. The phase of the hysteresis output (HO1) can be set reversely to the above.

The second hysteresis comparator 1510b has a second output voltage VO2, a reference voltage VREF2 generated by the setting circuit 1570, an upper limit voltage VH2 generated by the setting circuit 1570, And generates a hysteresis output HO2 by receiving the lower limit voltage VL2 generated by the lower limit voltage VL2. In addition to the above-described change of the input / output signals, the second hysteresis comparator 1510b performs the same operation as that of the first hysteresis comparator 1510a, and thus a description thereof will be omitted.

The third hysteresis comparator 1510c outputs the third output voltage VO3, the reference voltage VREF3 generated by the setting circuit 1570, the upper limit voltage VH3 generated by the setting circuit 1570, And generates a hysteresis output HO3 by receiving the lower limit voltage VL3 generated by the lower limit voltage VL3. In addition to the above-described change of the input / output signals, the third hysteresis comparator 1510c performs the same operation as the first hysteresis comparator 1510a, and thus a description thereof will be omitted.

3 is a timing diagram illustrating an exemplary operation of the first hysteresis comparator shown in FIG. 3, the horizontal axis represents time and the vertical axis represents voltage. The timing chart of FIG. 3 shows the first output voltage VO1 and the hysteresis output HO1 when the DC-DC converter 1000 normally drives the first output voltage VO1. In this case, referring to FIG. 3, the first output voltage VO1 may be varied only between the reference upper limit voltage VREF1 + VH1 and the reference lower limit voltage VREF-VL1.

At the time T1, the first output voltage VO1 is higher than the reference lower limit voltage VREF1-VL1, and is lowered. The first output voltage VO1 rises by the operation of the switch controller 1500 to be described later. The hysteresis output (HO1) may be changed from low to high at time T1.

At time T2, the first output voltage VO1 is lower than the reference upper limit voltage VREF1 + VH1, and becomes higher. By the operation of the switch controller 1500 to be described later, the first output voltage VO1 falls. The hysteresis output HO1 can be changed from high to low at time T2.

At the time T3, the first output voltage VO1 is higher than the reference lower limit voltage VREF1-VL1, and is lowered. The hysteresis output (HO1) can be changed from high to low at the time T3 as at the time T1.

4 is a block diagram illustrating an exemplary first hysteresis comparator of FIG. 2; 4, hysteresis comparator 1510a includes comparators 1511a and 1511b, delay circuits 1512a and 1512b, inverters 1513a and 1513b, and AND circuits 1514a and 1514b ) And an SR latch (SR latch) 1515.

The first comparator 1511a receives the first output voltage VO1 as a negative input and the reference lower voltage VREF1-VL1 as a positive input to compare the two. The comparator 1511a can compare the first output voltage VO1 with the fluctuable minimum voltages VREF1-VL1. When the first output voltage VO1 is higher than the reference lower voltage VREF1-VL1 and then becomes lower, the output of the first comparator 1511a may be changed from low to high. This operation can be regarded as an operation at the time point T1 in the operation of FIG.

The output of the first comparator 1511a may be directly input to the AND circuit 1514a and may be input to the AND circuit 1514a through the inverter 1513a via the delay circuit 1512a. When the first output voltage VO1 is higher than the reference lower voltage VREF1-VL1 and then becomes lower, the AND circuit 1514a outputs a set pulse of the EAL latch 1515 by the delay time of the delay circuit 1512a Lt; / RTI > The EAL latch 1515 may change the hysteresis output HOl from low to high due to the set pulse. This operation can be regarded as an operation at the time point T1 in the operation of FIG.

The second comparator 1511b receives the first output voltage VO1 as a positive input and the reference upper-limit voltage VREF1 + VH1 as a negative input, thereby comparing the two. The comparator 1511b can compare the first output voltage VO1 with the maximum fluctuable voltage VREF1 + VH1. When the first output voltage VO1 is lower than the reference upper voltage VREF1 + VH1 and becomes higher, the output of the second comparator 1511b may be changed from low to high. This operation can be regarded as an operation at the time point T2 in the operation of FIG.

The output of the second comparator 1511b may be directly input to the AND circuit 1514b and may be input to the AND circuit 1514b through the inverter 1513b via the delay circuit 1512b. When the first output voltage VO1 becomes lower than the reference upper limit voltage VREF1 + VH1 and becomes higher, the AND circuit 1514b outputs a reset pulse of the EAL latch 1515 by the delay time of the delay circuit 1512b Can be generated. The EAL latch 1515 may change the hysteresis output HOl from high to low due to the reset pulse. This operation can be regarded as an operation at the time point T2 in the operation of FIG.

The first and second delay circuits 1512a and 1512b can be configured by combining an even number of inverters so that the input phase is not changed. It is sufficient that the number of inverters can generate a set pulse and a reset pulse so that the EAL latch 1515 can change the phase of the current hysteresis output HO1.

The EAL latch 1515 may be configured with a combination of two inverted NOR circuits or a combination of two inverted NAND circuits. The EAL latch 1515 receives the output of the AND circuit 1514a as a set signal and the output of the AND circuit 1514b as a reset signal to generate the hysteresis output HO1.

Referring again to FIG. 2, the voltage rise time controller 1520 includes an output HO1 of the first hysteresis comparator 1510a, an output HO2 of the second hysteresis comparator 1510b, O2, O3, O12, O23, O13, and O123 can be output by taking the output HO3 of the comparator 1510c as an input.

5 is a flow chart showing the operation of the voltage rise time controller shown in FIG. 5, the voltage rise time controller 1520 performs a total of seven steps to output voltage rise signals O1, O2, O3, O12, O23, O13 and O123.

In step S110, the voltage rise time controller 1520 can determine whether the hysteresis output HO1 is equal to high. In steps S120 and S130, the voltage rise time controller 1520 can determine whether the hysteresis output HO2 is equal to high. In steps S140, S150, S160, and S170, the voltage rise time controller 1520 can determine whether the hysteresis output HO3 is equal to high.

When the hysteresis output HO1 is high, HO2 is high and HO3 is high, only the voltage rise signal O123 of the voltage rise signals O1, O2, O3, O12, O23, O13 and O123 becomes high . The remaining voltage raising signals may all be low.

When the hysteresis output HO1 is high, the hysteresis output HO2 is high and the hysteresis output HO3 is low, the voltage rising signals O1, O2, O3, O12, O23, O13, O123 Only the voltage rising signal O12 can be made high. The remaining voltage raising signals may all be low.

When the hysteresis output HO1 is high, the hysteresis output HO2 is low, and the hysteresis output HO3 is high, the voltage rising signals O1, O2, O3, O12, O23, Only the voltage rising signal O13 in the odd-numbered lines O123 and O123 may become high. The remaining voltage raising signals may all be low.

When the hysteresis output HO1 is high, the hysteresis output HO2 is low, and the hysteresis output HO3 is low, the voltage rise signals O1, O2, O3, O12, O23, Only the voltage rising signal O1 in the ON state can be made high. The remaining voltage raising signals may all be low.

When the hysteresis output HO1 is low, the hysteresis output HO2 is high and the hysteresis output HO3 is high, the voltage rise signals O1, O2, O3, O12, O23, Only the voltage rising signal O23 in the ON state can be made high. The remaining voltage raising signals may all be low.

When the hysteresis output HO1 is low, the hysteresis output HO2 is high and the hysteresis output HO3 is low, the voltage rise signals O1, O2, O3, O12, O23, Only the voltage rising signal O2 in the ON state can be made high. The remaining voltage raising signals may all be low.

When the hysteresis output HO1 is low, the hysteresis output HO2 is low, and the hysteresis output HO3 is high, the voltage rising signals O1, O2, O3, O12, O23, O13 , O123) can be made high. The remaining voltage raising signals may all be low.

When the hysteresis output HO1 is low, the hysteresis output HO2 is low, and the hysteresis output HO3 is low, the voltage rise signals O1, O2, O3, O12, O23, O13 , O123) may all be low.

The subscripts of the voltage rising signals O1, O2, O3, O12, O23, O13 and O123 may represent outputs requiring a voltage rise. For example, if the voltage raising signal O12 is high, it may indicate that a voltage rise is required at the first output and the second output. If the voltage raising signals (O1, O2, O3, O12, O23, O13, O123) are all low, both the first output, the second output and the third output may indicate that no voltage rise is required.

Referring again to FIG. 2, the pulse generator 1530 includes a plurality of output voltages VO1, VO2 and VO3, reference voltages VREF1, VREF2 and VREF3, an internal clock ICLK, interference determination information Rbdry, Initial pulse width information G1_INI, G2_INI, G3_INI of the switch control signals, initial pulse width information GN_INI of the ground switch control signal, and initial pulse width information GF_INI of the inductor switch control signal.

The pulse generator 1530 may generate the pulse signals P1_0, P1_1, P2_0, P2_1, P2_2, P3_0, P3_1, P3_2, P3_3 using the input information. The meaning of the first subscript and the second subscript of each pulse signal is given for example.

For example, it is assumed that only the first output requires a voltage rise. The first subscript of the pulse signal can refer to the number of outputs requiring a voltage rise. In this case, the pulse signals P1_0 and P1_1 can be activated by the pulse generator 1530. The pulse signal P1_0 can generate the ground switch control signal GN. The pulse signal P1_1 can generate the first output switch control signal G1. If a voltage rise is required for the second output instead of the first output, the pulse signal P1_1 can generate the second output switch control signal G2.

For example, it is assumed that the first output and the third outputs require a voltage rise. The first subscript of the pulse signal can refer to the number of outputs requiring a voltage rise. In this case, the pulse signals (P2_0, P2_1, P2_2) can be activated by the pulse generator 1530. The pulse signal P2_0 can generate the ground switch control signal GN. The pulse signal P2_1 can generate the first output switch control signal G1. The pulse signal P2_2 can generate the third output switch control signal G3.

For example, assume that the first output, the second output, and the third outputs require a voltage rise. The first subscript of the pulse signal can refer to the number of outputs requiring a voltage rise. In this case, the pulse signals P3_0, P3_1, P3_2, and P3_3 can be activated by the pulse generator 1530. The pulse signal P3_0 can generate the ground switch control signal GN. The pulse signal P3_1 can generate the first output switch control signal G1. The pulse signal P3_2 can generate the second output switch control signal G2. The pulse signal P3_3 can generate the third output switch control signal G3.

FIG. 6 is a block diagram illustrating an exemplary pulse generator shown in FIG. 2. FIG. Referring to FIG. 6, the pulse generator 1530 includes a first output voltage monitor 1531a, a second output voltage monitor 1531b, a third output voltage monitor 1531c, an interference determination circuit 1532, 1 switch 1533a, a second switch resistor 1533b, a third switch resistor 1533c, a ground switch resistor 1533d, an inductor switch resistor 1533e, a first output switch logic circuit The second output switch logic circuit 1534b, the third output switch logic circuit 1534c, the grounding switch logic circuit 1534d, the inductor switch logic circuit 1534e, the counter 1535, (1536).

The first output voltage monitor 1531a can generate the interference determination signal D1 by receiving the first output voltage VO1, the reference voltage VREF1, and the interference determination information Rbdry. The first output voltage monitor 1531a can perform Equations (1) and (2) below.

The first output voltage monitor 1531a may monitor the first output voltage VO1 and the reference voltage VREF1. If the absolute value of the difference between the first output voltage VO1 and the reference voltage VREF1 is small and the intermediate value M1 is smaller than 1, the first output voltage monitor 1531a sets the interference determination signal D1 to 1 . The first output voltage monitor 1531a may be transmitted to the interference determination circuit 1532 in order to determine the interference decision signal D1.

When the absolute value of the difference between the first output voltage VO1 and the reference voltage VREF1 is large and the median value M1 is greater than or equal to 1 and smaller than the interference determination information Rbdry, the first output voltage monitor 1531a Can set the interference decision signal D1 to 2. In this case, it can be determined that the interference is generated in the first output by the second output or the third output. The interference judgment circuit 1532 can judge the interference. The operation of the interference determination circuit 1532 will be described later.

When the absolute value of the difference between the first output voltage VO1 and the reference voltage VREF1 becomes larger than the above case and the intermediate value M1 is larger than the value obtained by adding 1 to the interference determination information Rbdry, The interference decision signal 1531a can set the interference decision signal D1 to 3. In this case, it can be judged that the first output is required to rise or fall due to an abrupt increase or decrease in current consumption rather than inter-output interference. The interference judgment circuit 1532 can judge the interference.

The second output voltage monitor 1531b may generate the interference determination signal D2 by receiving the second output voltage VO2, the reference voltage VREF2, and the interference determination information Rbdry. The second output voltage monitor 1531b may perform equations (1) and (2) described above in the same manner as the first output voltage monitor 1531a by replacing the second output voltage monitor 1531b with only a subscript in place of the subscript. A description thereof will be omitted.

The third output voltage monitor 1531c receives the third output voltage VO3, the reference voltage VREF3, and the interference determination information Rbdry to generate the interference determination signal D3. The third output voltage monitor 1531c may perform equations (1) and (2) described above in the same manner as the first output voltage monitor 1531a by replacing the third output voltage monitor 1531c with a triplet instead of a subscript. A description thereof will be omitted.

The interference determination circuit 1532 receives the interference determination signal D1 of the first output voltage monitor, the interference determination signal D2 of the second output voltage monitor, and the interference determination signal D3 of the third output voltage monitor, Output switch control signals Update information (G1_PUL, G2_PUL, G3_PUL) and pulse interval (? Dt).

The interference determination circuit 1532 determines whether any one of the interference determination signal D1 of the first output voltage monitor, the interference determination signal D2 of the second output voltage monitor, and the interference determination signal D3 of the third output voltage monitor is 2 , It can be determined that interference has occurred between multiple outputs. Generally, in order to cause inter-output interference, two or more outputs must fall outside a predetermined voltage range, so that any one of the interference determination signals may be 3 and the other interference determination signals may be 2.

The interference determination circuit 1532 determines whether any one of the interference determination signal D1 of the first output voltage monitor, the interference determination signal D2 of the second output voltage monitor, and the interference determination signal D3 of the third output voltage monitor is 2 It can be determined that there is no interference between multiple outputs.

The criterion that the interference judgment circuit 1532 judges that interference has occurred between the respective outputs may depend on the interference judgment information Rbdry. The interference determination information Rbdry may be determined by the number of outputs driven by the DC-DC converter 1000, the type of the output, the size of the inductor 1100, the property of the input stage VI, and the like. The DC-DC converter 1000 according to the present invention receives the external clock CLK and the communication signal COM, and the setting circuit 1570, which will be described later, can change the interference determination information Rbdry. Accordingly, even if the number of outputs and the type of output are changed by the DC-DC converter 1000, the output can be appropriately driven.

The first switch register 1533a can store the initial pulse width information G1_INI of the first output switch control signal and the output (G1_REG) of the logic circuit for the first output switch. The output (G1_REG) of the logic circuit for the first output switch may indicate the pulse width information of the first output switch control signal G1 at present. The second switch register 1533b, the third switch register 1533c, the ground switch register 1533d and the inductor switch register 1533e all perform the same function as the first switch register 1533a A description thereof will be omitted.

The first output switch logic circuit 1534a receives the pulse width information G1_PRE of the previous first output switch control signal, the first output switch control signal update information G1_PUL and the pulse interval Δdt, The pulse width information G1_REG of the output switch control signal can be generated.

The first output switch logic circuit 1534a can keep the previous pulse interval if the output switch control signal update information G1_PUL of the interference determination circuit 1532 becomes zero. This is because the present first output voltage VO1 is within a predetermined voltage range. The first output switch logic circuit 1534a can change the previous pulse interval if the output switch control signal update information G1_PUL of the interference determination circuit 1532 is not zero. This is because the present first output voltage VO1 is outside the predetermined voltage range.

The second output switch logic circuit 1534b receives the pulse width information G2_PRE of the previous second output switch control signal, the second output switch control signal update information G2_PUL and the pulse interval Δdt, The pulse width information G2_REG of the output switch control signal can be generated. The internal operation of the second output switch logic circuit 1534b is the same as that of the first output switch logic circuit 1534a, and a description thereof will be omitted.

The third output switch logic circuit 1534c receives the pulse width information G3_PRE of the previous third output switch control signal, the third output switch control signal update information G3_PUL and the pulse interval Δdt, The pulse width information G3_REG of the output switch control signal can be generated. The internal operation of the third output switch logic circuit 1534c is the same as that of the first output switch logic circuit 1534a, and a description thereof will be omitted.

The grounding switch logic circuit 1534d includes pulse width information GN_PRE of the previous ground switch control signal, pulse width information G1_REG of the first output switch control signal, pulse width information G2_REG of the second output switch control signal, The pulse width information GN_REG of the current ground switch control signal can be generated by receiving the pulse width information G3_REG of the third output switch control signal and the pulse interval dt.

The grounding switch logic circuit 1534d outputs pulse width information G1_REG of the first output switch control signal, pulse width information G2_REG of the second output switch control signal, and pulse width information G3_REG To store the energy in the inductor 1100. < RTI ID = 0.0 >

The inductor switch logic circuit 1534e includes pulse width information GF_PRE of the previous inductor switch control signal, pulse width information G1_REG of the first output switch control signal, pulse width information G2_REG of the second output switch control signal, The pulse width information GF_REG of the current inductor switch control signal is generated by receiving the pulse width information G3_REG of the third output switch control signal, the pulse width information GN_REG of the ground switch control signal, and the pulse interval dt. can do.

The inductor switch logic circuit 1534e includes pulse width information G1_REG of the first output switch control signal, pulse width information G2_REG of the second output switch control signal, and pulse width information G3_REG ), The energy supply time of all outputs can be calculated. The inductor switch logic circuit 1534e can calculate the time for storing energy in the inductor 1100 through the pulse width information GN_REG of the ground switch control signal. Through the times, the inductor switch logic circuit 1534e can calculate the time remaining for the transformer 1000 to transfer energy to multiple outputs.

The counter 1535 receives the internal clock ICLK and can count the internal clock ICLK to generate the counter output CN. The counter 1535 may communicate the counter output CN to the comparator 1536.

The comparator 1536 compares the pulse width information G1_REG of the first output switch control signal, the pulse width information G2_REG of the second output switch control signal, the pulse width information G3_REG of the third output switch control signal, P1_1, P2_0, P2_1, P2_2, P3_0, P3_1, P3_2, P3_2, P3_3, P3_3, P3_3, P3_3).

FIGS. 7A and 7B are timing diagrams illustrating the operation of the pulse generator shown in FIG. 6; FIG. 7A and 7B illustrate the operation of the pulse generator 1530 when a sudden rise occurs in the first output voltage VO1 and interference occurs in the second output voltage VO2 and the third output voltage VO3. As shown in Fig. In this case, the interference determination signal Dl may be 3, the interference determination signal D2 may be 2, and the interference determination signal D3 may be 2. Since the first output voltage VO1 requires a voltage drop and the second output voltage VO2 and the third output voltage VO3 require a voltage rise, the pulse generator 1530 generates the pulse signals P3_1, P3_2, P3_3).

Referring to FIG. 7A, it can be seen that the counter 1535 counts the internal clock ICLK with the lapse of time and raises the counter output CN. At the time T0, with the rise of the counter output CN, the pulse generator 1530 can start generating the pulse signal P3_1.

At the time T1, when the counter output CN reaches the pulse width information G1_REG of the first output switch control signal, the pulse generator 1530 stops generating the pulse signal P3_1 and outputs the next internal clock ICLK, The generation of the pulse signal P3_2 can be started.

At the time T2, when the counter output CN reaches the pulse width information G2_REG of the second output switch control signal, the pulse generator 1530 stops generating the pulse signal P3_2 and outputs the next internal clock ICLK, The generation of the pulse signal P3_3 can be started.

At the time T3, when the counter output CN reaches the pulse width information G3_REG of the third output switch control signal, the pulse generator 1530 can stop generating the pulse signal P3_3.

Referring to FIG. 7B, the pulse generator 1530 may adjust the pulse signals P3_1, P3_2, P3_3 to reduce the interference of the second output voltage VO2 and the third output voltage VO3. 6, pulse width information G1_REG of the first output switch control signal, pulse width information G2_REG of the second output switch control signal, and pulse width information G2_REG of the third output switch control signal 1530, It can be confirmed that the pulse width information G3_REG of FIG.

At the time T1, it can be seen that the pulse width of the pulse signal P3_1 is 2Δdt smaller than that of the pulse signal P3_1 described above in FIG. 7A. At the time T2, the pulse signal P3_2 can be confirmed to have increased in pulse width by 1? Dt as compared with the pulse signal P3_2 described in FIG. 7A. At the time T3, it can be seen that the pulse signal P3_3 has a pulse width increased by 1? Dt as compared to the pulse signal P3_3 described above with reference to FIG. 7A.

7A and 7B, when a sudden rise occurs in the first output voltage VO1 and interference occurs in the second output and the third output voltages VO2 and VO3, DC converter 1000 reduces the pulse width of the first output switch control signal G1 and increases the pulse width of the second output switch control signal G2 and the pulse width of the third output switch control signal G3 Thereby reducing interference between outputs.

2, the ground switch controller 1540 receives the pulse signals P1_0, P2_0 and P3_0 and the voltage rising signals O1, O2, O3, O12, O23, O13 and O123, And can generate the signal GN. The ground switch controller 1540 may require the pulse signals P1_0, P2_0 and P3_0 among the pulse signals P1_0, P1_1, P2_0, P2_1, P2_2, P3_0, P3_1, P3_2 and P3_3. This is because the grounding switch controller 1540 can be used when the output voltage is out of the predetermined voltage range, when the two output voltages are out of the predetermined voltage range, or when the three output voltages are out of the predetermined voltage range , And the time for storing energy in the inductor 1100 must be adjustable.

The ground switch controller 1540 can determine whether one output voltage is out of the predetermined voltage range through the voltage rising signals O1, O2, and O3. The voltage switch controller 1540 can determine whether the two output voltages are out of the predetermined voltage range through the voltage rise signals O12, O23, and O13. The voltage switch controller 1540 can determine whether the three output voltages are out of the predetermined voltage range through the voltage increase signal O123.

FIG. 8 is a block diagram illustrating an exemplary ground switch controller shown in FIG. 2. FIG. The ground switch controller 1540 may include a first circuit 1541, a second circuit 1542, a third circuit 1543, and an OR circuit 1544. If the number of outputs is increased to x rather than 3, the ground switch controller 1540 may require x logical AND circuits.

The first logic circuit 1541 may include three logical product circuits that logically multiply the voltage rise signals O1, O2 and O3 and the pulse signal P1_0. The output of the first logic circuit 1541 may mean the pulse width of the ground switch control signal GN when one output voltage is out of a predetermined voltage range.

The second logic circuit 1542 may include three logical product circuits that logically multiply each of the voltage rise signals O12, O23, and O13 and the pulse signal P2_0. The output of the second logic circuit 1542 may refer to the pulse width of the ground switch control signal GN if the two output voltages are outside the predetermined voltage range.

The third logic circuit 1543 may include one logical product circuit for performing an AND operation on the voltage rise signal O123 and the pulse signal P3_0. The output of the third logic circuit 1543 may refer to the pulse width of the ground switch control signal GN when the three output voltages are outside the predetermined voltage range.

The fourth logic circuit 1544 receives the outputs of the first logic circuit 1541, the second logic circuit 1542 and the third logic circuit 1543 and performs an OR operation on the outputs of the first logic circuit 1541, the second logic circuit 1542, Width can be generated.

Referring again to FIG. 2, the inductor switch controller 1550 receives the hysteresis outputs HO1, HO2, and HO3 to generate an inductor switch control signal GF. As described above, the hysteresis outputs HO1, HO2, and HO3 may indicate whether a voltage rise is needed for each output voltage. The inductor switch controller 1550 can store the energy remaining in the inductor 1100 through the inductor switch control signal GF since all output voltages are within a predetermined voltage range and no longer need to supply energy to the output .

FIG. 9 is a block diagram illustrating an exemplary inductor switch controller shown in FIG. 2. FIG. 9, the inductor switch controller 1550 may include an OR circuit. If the hysteresis outputs HO1, HO2, and HO3 are all low so that all output voltages are within a predetermined voltage range, the inductor switch controller 1550 can pull the inductor switch control signal GF low. The inductor switch controller 1550 turns on the inductor switch 1300 so that the energy stored in the inductor 1100 can be conserved.

The first output switch controller 1560a may receive the pulse signals P1_1, P2_1 and P3_1 and the voltage rise signals O1, O12, O13 and O123 to generate the first output switch control signal G1 . The first output switch controller 1560a may require pulse signals P1_1, P2_1 and P3_1 among the pulse signals P1_0, P1_1, P2_0, P2_1, P2_2, P3_0, P3_1, P3_2 and P3_3. This is because the first output switch controller 1560a must be able to adjust the time that energy is supplied to the first output when the first output voltage VO1 is out of the predetermined voltage range.

FIGS. 10A to 10C are block diagrams illustrating the first to third output switch controllers shown in FIG. 2. FIG. 10A, the first output switch controller 1560a includes a first logic circuit 1561a, a second logic circuit 1562a, a third logic circuit 1563a, a fourth logic circuit 1564a, or an inverter 1565a.

The first logic circuit 1561a may include an AND circuit for performing an AND operation on the voltage rising signal O1 and the pulse signal P1_1. The output of the first logic circuit 1561a may mean the pulse width of the first output switch control signal G1 when the first output voltage VO1 is out of a predetermined voltage range.

The second logic circuit 1562a may include an AND circuit for performing an AND operation on the voltage rising signals O12 and O13 and the pulse signal P2_1. The output of the second logic circuit 1562a is set so that when the first output voltage VO1 and the second output voltage VO2 are out of a predetermined voltage range or when the first output voltage VO1 and the third output voltage VO3 ) Is outside the predetermined voltage range, it may mean the pulse width of the first output switch control signal G1.

The third logic circuit 1563a may include an AND circuit for performing an AND operation on the voltage rise signal O123 and the pulse signal P3_1. The output of the third logic circuit 1563a is a first output switch control signal when the first output voltage VO1, the second output voltage VO2, and the third output voltage VO3 are out of a predetermined voltage range. May mean the pulse width of the pulse G1.

The fourth logic circuit 1564a receives the outputs of the first logic circuit 1561a, the second logic circuit 1562a, or the third logic circuit 1563a and performs an OR operation on the outputs to generate a first output switch control signal G1, Can be generated.

The inverter 1565a can change the phase of the output of the OR circuit 1564a to generate the pulse width of the first output switch control signal G1. The inverter 1565a may be used to determine a turn-on or turn-off phase according to the first output switch type. The inverter 1565a may not be used depending on the type of the first output switch.

10B, the second output switch controller 1560b receives the pulse signals P1_1, P2_2, P2_1 and P3_2 and the voltage rising signals O2, O12, O23 and O123, (G2). The second output switch controller 1560b may require pulse signals P1_1, P2_2, P2_1 and P3_2 among the pulse signals P1_0, P1_1, P2_0, P2_1, P2_2, P3_0, P3_1, P3_2 and P3_3. This is because the second output switch controller 1560b must be able to adjust the time that energy is supplied to the second output when the second output voltage VO2 is out of the predetermined voltage range. Hereinafter, the structure of the second output switch controller 1560b is the same as that of the first output switch controller 1560a, and a description thereof will be omitted.

10C, the third output switch controller 1560c receives the pulse signals P1_1, P2_2 and P3_3 and the voltage rising signals O3, O13, O23 and O123 and outputs the second output switch control signal G2, Lt; / RTI > The third output switch controller 1560c may require pulse signals P1_1, P2_2 and P3_3 among the pulse signals P1_0, P1_1, P2_0, P2_1, P2_2, P3_0, P3_1, P3_2 and P3_3. This is because the third output switch controller 1560c must be able to adjust the time that energy is supplied to the third output when the third output voltage VO3 is out of the predetermined voltage range. Hereinafter, the structure of the third output switch controller 1560c is the same as that of the first output switch controller 1560a, and a description thereof will be omitted.

2, the setting circuit 1570 sets the reference voltages VREF1, VREF2 and VREF3, the upper voltages VH1, VH2 and VH3, the lower voltage VL1, VL2 and VL3, the interference judgment information Rbdry, G2_INI and G3_INI of the output switch control signals, initial pulse width information GN_INI of the ground switch control signal, initial pulse width information GF_INI of the inductor switch control signal, and internal clock ICLK, Can be generated.

To generate the signals, the setting circuit 1570 may include a reference voltage generator, a register, and a clock generator. The setting circuit 1570 can generate the reference voltages VREF1, VREF2 and VREF3, the upper voltages VH1, VH2 and VH3 and the lower voltages VL1, VL2 and VL3 through the reference voltage generator, Can be adjusted. The reference voltage generator can use the Bandgap Reference structure. The setting circuit 1570 includes interference judgment information Rbdry, initial pulse width information G1_INI, G2_INI, G3_INI of the output switch control signals, initial pulse width information GN_INI of the ground switch control signal, It is possible to store the initial pulse width information GF_INI of the signal. The clock generator can generate an internal clock (ICLK).

The setting circuit 1570 generates the reference voltages VREF1, VREF2 and VREF3 and the upper voltages VH1, VH2 and VREF3 using the clock CLK or the communication signal COM applied from the outside of the DC- G2_INI, G3_INI) of the output switch control signals, the initial pulse width information GN_INI (G_INI, G2_INI, G3_INI) of the ground switch control signal, ) Or the initial pulse width information GF_INI of the inductor switch control signal. Instead of the internal clock ICLK generated by the clock generator, the setting circuit 1570 may set the external clock CLK to the internal clock ICLK. The setting circuit 1570 can enable the DC-DC converter 1000 to drive multiple outputs even when multiple outputs driven by the DC-DC converter 1000 are changed.

11 is a flowchart showing an operation method of the DC-DC converter shown in FIG. Referring to FIG. 11, the DC-DC converter 1000 can drive each of the outputs so that the respective output voltages can be varied within a predetermined voltage range.

In step S210, the DC-DC converter 1000 may monitor the voltages of multiple outputs. To this end, the switch controller 1500 may receive multiple output voltages VO1, VO2, ..., VOx. The comparators 1511a and 1511b in the first hysteresis comparator 1510a compare the first output voltage VO1 with the reference upper or first output voltage VO1 and the lower reference voltage Can be compared.

In step S220, the DC-DC converter 1000 may determine whether the voltages of the respective multiple outputs are within a predetermined voltage range. As described above in FIG. 3, the hysteresis comparators 1510a, 1510b, and 1510c can determine whether each output voltage is out of a predetermined voltage range.

In step S230, the DC-DC converter 1000 can determine whether interference occurs between the multiple outputs because some or all of the voltages of the multiple outputs are out of the predetermined voltage range. As described above with reference to FIG. 6, the interference determination circuit 1532 can determine whether any one of the interference determination signals D1, D2, and D3 exists, and determine whether inter-output interference has occurred.

In step S240, the DC-DC converter 1000 outputs the inductor switch control signal GF when some or all of the voltages of the multiple outputs are out of the predetermined voltage range, and interference occurs between the voltages of the multiple outputs. The ground switch control signal GN, the output switch control signals that caused the interference, and the previous pulse widths of the received output switch control signals. In step S240, the pulse width information (G1_REG, G2_REG, G3_REG, GN_REG, GF_REG) of the switch control signal of the pulse generator 1530 may be varied.

In step S250, the dc-to-dc converter 1000 outputs an inductor switch control signal (" 1 ") when some or all of the voltages of the multiple outputs are out of the predetermined voltage range and no interference occurs between the voltages of the multiple outputs GF), the ground switch control signal (GN), and control signals of the output switches outside the predetermined voltage range. In step S250, the pulse width information (G1_REG, G2_REG, G3_REG, GN_REG, GF_REG) of the switch control signal of the pulse generator 1530 may be varied.

In step S260, the DC-DC converter 1000 outputs the inductor switch control signal GF, the ground switch control signal GN, the output switch control signals G1 , ..., Gx). In step S260, the register information (G1_REG, G2_REG, G3_REG, GN_REG, GF_REG) of the pulse generator 1530 can be kept constant.

In step S270, it is determined whether the operation of the DC-DC converter 1000 is stopped. If the operation of the DC-DC converter 1000 is interrupted, the DC-DC converter 1000 may terminate driving the multiple output voltages. If the operation of the DC-DC converter 1000 is not interrupted, the DC-DC converter 1000 may perform the operation again from step S210. Thus, the DC-DC converter 1000 can cause the voltages of the multiple outputs to fluctuate only within a predetermined voltage range.

FIG. 12 is a flowchart for specifically explaining step S230 shown in FIG. Referring to FIG. 12, the DC-DC converter 1000 can determine the interference between multiple output voltages by digitizing the difference between each output voltage and the reference voltage.

In step S231, the DC-DC converter 1000 can calculate the difference between each output voltage and the reference voltage. As described above in FIG. 6, the output voltage monitors 1531a, 1531b 1531c may perform Equation 1 to produce intermediate values M1, M2, and M3.

In step S232, the DC-DC converter 1000 may convert the difference between each output voltage and the reference voltage into the interference determination signals D1, D2, ..., Dx. 6, the output voltage monitors 1531a, 1531b 1531c may perform Equation 2 to generate the interference determination signals D1, D2, and D3.

In step S233, the DC / DC converter 1000 can determine whether any one of the interference determination signals D1, D2, ..., and Dx exists, and determine whether inter-output interference has occurred.

 If any one of the interference determination signals D1, D2, ..., Dx is 2 in step S234, the DC-DC converter 1000 can determine that interference has occurred between the multiple output voltages.

If there is no 2 in any one of the interference determination signals D1, D2, ..., Dx in step S235, the DC-DC converter 1000 may determine that no interference has occurred between the multiple output voltages have.

Figs. 13A and 13B are timing diagrams illustrating the operation of the DC-DC converter shown in Fig. 1. Fig. Referring to FIG. 13A, due to the increase of the first output current IO1, the first output voltage VO1 is out of the predetermined voltage range, and the remaining output voltages are fluctuating in the predetermined voltage range. In this case, the DC-DC converter 1000 can confirm that interference does not occur in the remaining outputs except for the first output, and can drive the first output voltage VO1.

At the time T1, the first output voltage VO1 can raise the intermediate value M1 due to the increase of the first output current IO1. Since there is no interference in the remaining outputs, the median value M2 can remain less than one. At the time T2, due to the operation of the DC-DC converter 1000, the first output voltage VO1 can be varied within a predetermined voltage range.

13B, due to the increase of the first output current IO1, the first output voltage VO1 is out of the predetermined voltage range, and the second output voltage VO2 is out of the predetermined voltage range It was. In this case, the DC-DC converter 1000 can confirm that interference has occurred in the second output, and can drive the first output voltage VO1 and the second output voltage VO2.

At the time T1, the first output voltage VO1 can raise the intermediate value M1 due to the increase of the first output current IO1. At time T2, the second output voltage VO2 can raise the intermediate value M2 due to interference with the first output. At the time T3, due to the operation of the DC-DC converter 1000, the second output voltage VO2 can be varied within a predetermined voltage range. At the time T4, the operation of the DC-DC converter 1000 may cause the first output voltage VO1 to fluctuate within a predetermined voltage range.

The above-described contents of the present invention are only specific examples for carrying out the invention. The present invention will include not only concrete and practical means themselves, but also technical ideas which are abstract and conceptual ideas that can be utilized as future technologies.

1000: DC-DC converter
1100: Inductor
1200: Ground switch
1300: Inductor switch
1400: Output switches
1500: Switch controller

Claims (16)

An inductor for storing input energy;
A ground switch responsive to a first signal to provide a ground path for the inductor;
An inductor switch coupled in parallel with the inductor to maintain energy stored in the inductor in response to a second signal;
Output switches responsive to the third signals for outputting energy stored in the inductor to multiple output voltages; And
And a switch controller for determining the interference between the multiple output voltages and generating the first to third signals for reducing the interference,
The switch controller comprises:
Hysteresis comparators corresponding to the multiple output voltages comparing one of the multiple output voltages to a reference voltage;
A voltage rise time controller for controlling a rise time of the multiple output voltages;
A pulse generator for controlling the turn-on or turn-off time of the ground switch, the inductor switch, or the output switches;
A ground switch controller for controlling the ground switch;
An inductor switch controller for controlling the inductor switch;
Output switch controllers corresponding to the multiple output voltages controlling the output switches; And
Initial pulse width information of a control signal of the ground switch, initial pulse width information of a control signal of the inductor switch, initial pulse width information of control signals of the output switches, variable voltage information of the multiple output voltages And a setting circuit for setting the interference information between the multiple output voltages or a clock used by the switch controller. delete The method according to claim 1,
Wherein the setting circuit comprises:
A DC to DC converter for setting said information or said clock in response to an external clock and communication signal. The method according to claim 1,
Wherein the hysteresis comparator comprises:
A first comparator to compare any one of the multiple output voltages with a maximum changeable voltage;
A second comparator for comparing any one of the multiple output voltages with the variable minimum voltage;
A first delay circuit for delaying an output of the first comparator;
A second delay circuit for delaying an output of the second comparator;
A first inverter for inverting an output of the first delay circuit;
A second inverter for inverting an output of the second delay circuit;
A first logic circuit receiving an output of the first comparator and an output of the first inverter and performing an AND operation on the outputs;
A second logic circuit receiving the output of the second comparator and the output of the second inverter and performing an AND operation on the outputs; And
And an EAL latch receiving an output of the first logic circuit and an output of the second logic circuit. 5. The method of claim 4,
Wherein the first delay circuit or the second delay circuit comprises:
A DC-DC converter comprising an even number of inverters. The method according to claim 1,
Wherein the pulse generator comprises:
Output voltage monitors corresponding to the multiple output voltages monitoring any one of the multiple output voltages;
An interference determination circuit receiving the results of the monitors and determining interference between the multiple output voltages;
Registers for output switches corresponding to the multiple output voltages storing information of the output switch control signals;
An inductor switch register for storing information of the inductor switch control signal;
A ground switch register for storing information of the ground switch control signal;
Logic circuits for output switches corresponding to the multiple output voltages, receiving the results of the registers for the output switch and the result of the interference determination circuit and generating information of the output switch control signals;
A ground switch logic circuit receiving a result of the ground switch register as a result of the interference judgment circuit or the results of the output switch logic circuits corresponding to the multiple outputs and generating information of the ground switch control signal;
A result of the interference determination circuit, a result of the logic circuit for the ground switch, or the results of the logic circuits for the output switch corresponding to the multiple output voltages, as information of the inductor switch control signal, A logic circuit for an inductor switch for generating an inductor switch;
A counter for counting according to the clock; And
And a comparator for comparing the results of the counter and the results of the logic circuits. The method according to claim 6,
Wherein the output voltage monitor comprises:
And a DC-DC converter for calculating an absolute value of the multiple output voltages and the reference voltage difference and quantifying how much the absolute value is out of a predetermined voltage range. The method according to claim 6,
The interference determination circuit includes:
DC converter for determining whether the results of the output voltage monitors include < RTI ID = 0.0 > 2. < / RTI > The method according to claim 1,
The ground switch controller includes:
A first circuit for generating the ground switch control signal when any one of the multiple output voltages is out of a predetermined voltage range;
A second circuit for generating the ground switch control signal when a plurality of voltages of the multiple output voltages are out of the predetermined voltage range;
And a third circuit for generating the ground switch control signal when all of the multiple output voltages are out of the predetermined voltage range. The method according to claim 1,
The inductor switch controller includes:
And a circuit for generating a control signal that turns on the inductor switch using outputs of the hysteresis comparator when all of the multiple output voltages are within a predetermined voltage range. The method according to claim 1,
The output switch controller includes:
A control signal for turning on or off the output switch using the outputs of the voltage ramp-time controller and the outputs of the pulse generator when any one of the multiple output voltages is outside a predetermined voltage range DC converter comprising a circuit for generating a DC voltage. In a method of operating a DC-DC converter,
Monitoring multiple output voltages;
Determining whether the multiple output voltages are outside a predetermined voltage range;
Determining, by the switch controller, if the multiple output voltages are outside the predetermined voltage range, if interference between the multiple output voltages occurs;
Controlling the pulse widths of the control signals of the inductor switch, the grounding switch, the output switches causing the interference, and the output switches receiving the interference when the interference occurs,
Wherein determining if the interference occurs and controlling the pulse widths of the control signals comprises:
Comparing one of the multiple output voltages with a reference voltage;
Controlling a rise time of the multiple output voltages;
Controlling the turn-on or turn-off time of the inductor switch, the grounding switch, or the output switches; And
Initial pulse width information of a control signal of the ground switch, initial pulse width information of a control signal of the inductor switch, initial pulse width information of control signals of the output switches, variable voltage information of the multiple output voltages Or interference information between the multiple output voltages, or a clock used by the switch controller. 13. The method of claim 12,
Controlling the pulse widths of the control signals of the inductor switch, the grounding switch, and the output switches outside the predetermined voltage range when the multiple output voltages are outside the predetermined voltage range and the interference does not occur Lt; / RTI > 13. The method of claim 12,
Maintaining the pulse widths of the control signals of the inductor switch, the grounding switch, and the output switches when the voltages are within the predetermined voltage range. 13. The method of claim 12,
In the step of determining whether the interference occurs,
Calculating a difference between any one of the multiple output voltages and a reference voltage;
Quantifying how much the difference deviates from the predetermined voltage range;
Determine whether the values include 2;
And if the numbers include the 2, determine that the interference has occurred. 16. The method of claim 15,
And if the numbers do not include the 2, determine that the interference did not occur.

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