KR101976446B1 - Light emitting device and light emitting device package - Google Patents

Abstract

The light emitting device includes a nanostructure disposed on a substrate and a light emitting structure disposed on the nanostructure. The nanostructure includes a plurality of graphene patterns disposed on the substrate and a plurality of nanotextures disposed on the graphene pattern.

Description

TECHNICAL FIELD [0001] The present invention relates to a light emitting device and a light emitting device package,

An embodiment relates to a light emitting element.

An embodiment relates to a light emitting device package.

Researches on a light emitting device package having a light emitting element are actively underway.

The light emitting device is, for example, a semiconductor light emitting device or a semiconductor light emitting diode formed of a semiconductor material and converting electrical energy into light.

Semiconductor light emitting devices have advantages of low power consumption, semi-permanent lifetime, fast response speed, safety, and environmental friendliness compared with conventional light sources such as fluorescent lamps and incandescent lamps. Therefore, much research is underway to replace an existing light source with a semiconductor light emitting element.

Semiconductor light emitting devices are increasingly used as light sources for various lamps used in indoor and outdoor, lighting devices such as liquid crystal display devices, electric sign boards, and street lamps.

Embodiments provide a light emitting device capable of improving light emission efficiency by current spreading.

The embodiment provides a light emitting device capable of improving electrical characteristics and optical characteristics.

According to an embodiment, the light emitting element comprises: a substrate; A nanostructure disposed on the substrate; And a light emitting structure disposed on the nanostructure. Wherein the nanostructure comprises: a plurality of graphene patterns disposed on the substrate; And a plurality of nanotextures disposed on the graphene pattern.

According to an embodiment, the light emitting element includes an electrode layer; A light emitting structure disposed on the electrode layer; And a nanostructure disposed on the light emitting structure. Wherein the nanostructure comprises: a plurality of graphene patterns disposed on the substrate; And a plurality of nanotextures disposed on the graphene pattern.

According to an embodiment, a light emitting device package includes: a body; First and second lead electrodes disposed on the body; A light emitting element disposed on one of the body, the first and second lead electrodes; And a molding member surrounding the light emitting element.

An embodiment can grow a light emitting structure with excellent crystallinity without dislocations by disposing a nanostructure between the light emitting structure and the substrate that is smaller than the light emitting structure and has a lattice constant larger than that of the substrate. The light emitting structure thus grown can improve the light emitting efficiency by improving the electrical characteristics and the optical characteristics.

In the embodiment, by applying the nano structure to the horizontal light emitting device, the nanostructure can be used as the electron blocking layer to prevent the electrons of the semiconductor layer from being injected into the substrate, thereby improving the light emitting efficiency.

In this embodiment, by applying the nanostructure to the horizontal light emitting device, the nanostructure is used as the current spreading so that the current flows in the entire region between the nanostructure and the transparent conductive layer, so that light is generated in the entire region of the active layer, Can be improved.

By applying a nanostructure to a vertical type light emitting device, the current is allowed to flow to the entire region between the nanostructure and the electrode layer by utilizing the nanostructure as current spreading, so that light is generated in the entire region of the active layer, .

1 is a cross-sectional view illustrating a light emitting device according to a first embodiment.
2 is a plan view showing an example of a nanostructure.
3 is a plan view showing another example of the nanostructure.
4 is a plan view showing a light emitting device according to the second embodiment.
5 is a cross-sectional view of the light emitting device of FIG. 4 taken along line AA '.
6 is a cross-sectional view of the light emitting device of FIG. 4 taken along line BB '.
FIG. 7 is a view showing a current flow in the light emitting device of FIG. 4; FIG.
8 to 14 are process drawings for manufacturing the light emitting device according to the second embodiment.
15 is a cross-sectional view illustrating a light emitting device package according to an embodiment.

In describing an embodiment according to the invention, in the case of being described as being formed "above" or "below" each element, the upper (upper) or lower (lower) Directly contacted or formed such that one or more other components are disposed between the two components. Also, in the case of "upper (upper) or lower (lower)", it may include not only an upward direction but also a downward direction based on one component.

1 is a cross-sectional view illustrating a light emitting device according to a first embodiment.

1, a light emitting device 1 according to a first embodiment includes a substrate 10, a plurality of nanostructures 19, a light emitting structure 30, a transparent conductive layer 33, (35, 38), but this is not limiting.

The light emitting structure 30 includes a first conductive semiconductor layer 25, an active layer 27, and a second conductive semiconductor layer 29, but the present invention is not limited thereto.

The nanostructure 19 may include a grapheme pattern 13 and a plurality of nanotextures 16 but is not limited thereto.

The light emitting device 1 according to the embodiment may further include a buffer layer 22 disposed between the substrate 10 and the light emitting structure 30.

The light emitting device 1 according to the embodiment may further include another semiconductor layer (not shown) disposed below and / or above the light emitting structure 30. [

The light emitting device 1 according to the embodiment may further include an unshown semiconductor layer (not shown) disposed between the buffer layer 22 and the light emitting structure 30.

The substrate 10 easily grows the light emitting structure 30, but the present invention is not limited thereto.

In order to stably grow the light emitting structure 30, the substrate 10 may be formed of a material having a small difference in lattice constant from the light emitting structure 30.

The substrate 10 may be formed of at least one selected from the group consisting of sapphire (Al ₂ O ₃ ), SiC, Si, GaAs, GaN, ZnO, Si, GaP, InP and Ge.

The buffer layer (22) may be disposed between the substrate (10) and the light emitting structure (30). The buffer layer 22 may be formed to mitigate the lattice constant difference between the substrate 10 and the light emitting structure 30.

The buffer layer 22 and the light emitting structure 30 may be formed of a II-VI compound semiconductor material.

Even if the buffer layer 22 is formed to easily grow the light emitting structure 30, a lattice defect such as a dislocation due to a difference in lattice constant between the light emitting structure 30 and the substrate 10 Lt; / RTI > Such a dislocation may mean a boundary line formed in a direction perpendicular to the light emitting structure due to a lattice defect between the substrate and the light emitting structure. Such electric potential deteriorates the electrical and optical characteristics of the light emitting device and may not be the light emission itself.

In order to solve such a problem, in the first embodiment, a plurality of nanostructures 19 may be disposed between the substrate 10 and the buffer layer 22.

Although not shown, the nanostructure 19 may be disposed between the substrate 10 and the light emitting structure 30 when the buffer layer 22 is not used.

Each of the nanostructures 19 may include a graphene pattern 13 and a plurality of nanotextures 16 formed on the graphene pattern 13, but the present invention is not limited thereto.

Graphene can be formed by various process methods. For example, graphene can be formed by a chemical synthesis method through oxidation-reduction of graphite, a CVD growth method, an epitaxy synthesis method, or the like.

The graphene pattern 13 thus formed may be formed through the patterning process.

The graphene pattern 13 is the thinnest material among the known materials, and is the most flexible material as well as being able to conduct electricity or heat most of the time. The graphene pattern 13 is excellent in elasticity and can be stretched or bent, It can have a translucent function.

The plurality of graphene patterns 13 may be formed on the substrate 10.

The distance l between the graphen patterns 13 may be 0.1 탆 to 100 탆, but is not limited thereto. The distance l between the graphen patterns 13 may preferably be 10 to 50 mu m.

Therefore, the buffer layer 22 may be formed in contact with the substrate 10 through the gap between the graphen patterns 13.

The graphene pattern 13 may be formed on the substrate 10 beforehand.

Alternatively, the graphene pattern 13 may be formed directly on the substrate 10. In this case, a protective film is partially formed on the substrate 10, and a graphene film is formed on the substrate 10 using a chemical synthesis method, a CVD growth method, an epitaxial synthesis method, or the like, and then the protective film is removed A plurality of graphene patterns 13 may be formed on the substrate 10, but the present invention is not limited thereto.

A plurality of nanotextures 16 may be formed on each of the graphene patterns 13, but the present invention is not limited thereto.

A seed pattern for easily forming the nanotexture 16 to grow the nanotexture 16 partially on the graphene pattern 13 may be formed on the pattern 13, It is not limited.

The nanotexture 16 may be formed of zinc oxide (ZnO), but is not limited thereto.

The lattice constant of zinc oxide is approximately 3.25.

The lattice constant of sapphire used for the substrate 10 is approximately 4.78, and the lattice constant of GaN that can be used for the light emitting structure 30 is approximately 3.18.

Thus, since the lattice constant of zinc oxide is located between the lattice constant of sapphire and the lattice constant of GaN, GaN can grow well on sapphire without occurrence of dislocation due to zinc oxide.

The nanotexture 16 may be a plurality of nanorods, but is not limited thereto. The nanorods may be spaced apart from each other at regular intervals or spaced apart from each other at irregular intervals.

The nanorods may have a structure whose height is larger than the width, but the nanorod is not limited thereto.

For example, the width W of the nanotexture 16 may be between 5 nm and 500 nm, but is not limited thereto. The width W of the nanotexture 16 may preferably be between 50 nm and 200 nm.

For example, the height h of the nanotexture 16 may be 10 nm to 3 탆, but is not limited thereto. The height h of the nanotexture 16 may preferably be 500 nm to 1 탆.

The buffer layer 22 or the light emitting structure 30 is grown on the nanostructure 19 by setting the height h of the nanotexture 16 to be larger than the width W of the nanotexture 16. [ A Group II-VI compound semiconductor material such as GaN is grown mainly in the vertical direction between the nanotextures 16 and grown in the vertical direction and the horizontal direction on the nanotexture 16, And excellent crystallinity can be obtained, so that the electrical characteristics and optical characteristics of the light emitting device 1 can be improved.

For example, the thickness of the buffer layer 22 may be 20 nm to 50 nm, but the thickness is not limited thereto.

In this case, the height h of the nanotexture 16 may be larger than the thickness of the buffer layer 22. Thus, the top surface of the nanotexture 16 may be positioned higher than the top surface of the buffer layer 22. [ That is, the buffer layer 22 may be formed between the nanotextures 16. Accordingly, the light emitting structure 30 may be formed on the buffer layer 22 between the nanotextures 16 and on the nanotexture 16. [

If the thickness of the buffer layer 22 is greater than the height h of the nanotexture 16 the buffer layer 22 may be formed between the nanotextures 16 and over the nanotexture 16. [ .

Though the thickness of the first conductivity type semiconductor layer 25 of the light emitting structure 30 may be 2 탆 to 3 탆, it is not limited thereto.

If the light emitting structure 30 is directly formed on the nanostructure 19 without using the buffer layer 22, the light emitting structure 30 may be formed between the nanotextures 16 and the nanotexture 16, Can be formed.

The nanostructure 19 may have a shape as shown in FIGS. 2 and 3, but the present invention is not limited thereto.

2, the graphen pattern 13 may be formed in a circular shape. As shown in FIG. 3, the graphen pattern 13 may have a bar shape elongated in the longitudinal direction .

The graphene patterns 13 may be spaced apart from each other at regular intervals or at irregular intervals.

A buffer layer 22 may be formed on the nano structure 19. The buffer layer 22 may be formed of a II-VI compound semiconductor material. For example, the buffer layer 22 may be formed of one or a multi-layer structure of GaN, InN, AlGaN, and InGaN, but is not limited thereto.

1, the buffer layer 22 contacts the substrate 10 through the graphene patterns 13 of the nanostructure 19 and a plurality of nanotextures (not shown) of the nanostructure 19 16 in contact with the graphene pattern 13, and may be formed on the nanotext spread 16. This corresponds to the case where the thickness of the buffer layer 22 is larger than the height of the nanotexture 16. [

Although not shown, when the thickness of the buffer layer 22 is smaller than the height of the nanotexture 16, the buffer layer 22 is formed between the graphene patterns 13 of the nanostructure 19 And may be formed at a position lower than the upper surface of the nanotexture 16 between the plurality of nanotextures 16 of the nanostructure 19. [ In this case, the buffer layer 22 is not formed on the nanotexture 16. This is because the graphene pattern 13 seeds the substrate 10 rather than the nanotexture 16 seeding the buffer layer 22. That is, the buffer layer 22 grows in the vertical direction from the substrate 10 and grows vertically from the graphene pattern 13 between the nanotextures 16, So that the buffer layer 22 is not formed on the nanotexture 16.

1, if the thickness of the buffer layer 22 is greater than the height of the nanotexture 16, the buffer layer 22 is formed on the surface of the nanotexture 16, 13 in the vertical direction. As the nanotextures 16 are grown in both the vertical direction and the horizontal direction from above the upper surface of the nanotexture 16, the buffer layer 22 grown between the adjacent nanotextures 16 on the nanotexture 16 The buffer layer 22 may be formed on the nanotexture 16. In this case,

The growth principle of the buffer layer 22 on the nanostructure 19 may be equally applied to the case of growing the light emitting structure 30 on the nanostructure 19 instead of using the buffer layer 22. [

The light emitting structure 30 may be formed on the buffer layer 22 or the nanostructure 19. [

The light emitting structure 30 may include a first conductive semiconductor layer 25, an active layer 27, and a second conductive semiconductor layer 29, for example. The first conductive semiconductor layer 25 is formed on the buffer layer 22 or the nanostructure 19 and the active layer 27 is formed on the first conductive semiconductor layer 25, The second conductivity type semiconductor layer 29 may be formed on the active layer 27.

The first conductive semiconductor layer 25 may be, for example, an n-type semiconductor layer including an n-type dopant. The n-type semiconductor layer is made of a semiconductor material having a composition formula of In _x Al _y Ga _{1 -x- y} N (0? X? 1, 0? _Y? 1, 0? _X + y? 1) , GaN, AlGaN, InGaN, AlN, InN, and AlInN, and may be doped with an n-type dopant such as Si, Ge or Sn.

The active layer 27 may be formed on the first conductive semiconductor layer 25.

The active layer 27 is formed by coupling a first carrier, for example, electrons injected through the first conductive type semiconductor layer 25 and a second carrier, for example, a hole injected through the second conductive type semiconductor layer, And is a layer that emits light having a wavelength corresponding to a band gap difference of an energy band according to a material of the active layer 27.

The active layer 27 may include any one of a multiple quantum well structure (MQW), a quantum dot structure, and a quantum wire structure. The active layer 27 may be repeatedly formed with the periodicity of the well layer and the barrier layer.

For example, the period of the InGaN well layer / GaN barrier layer, the period of the InGaN well layer / AlGaN barrier layer, the period of the InGaN well layer / the InGaN barrier layer, and the like. The band gap of the barrier layer may be formed to be larger than the band gap of the well layer.

The second conductive semiconductor layer 29 may be formed on the active layer 27. The second conductive semiconductor layer 29 may be, for example, a p-type semiconductor layer including a p-type dopant. The p-type semiconductor layer is made of a semiconductor material having a composition formula of In _x Al _y Ga _{1 -x- y} N (0? X? 1, 0? _Y? 1, 0? _X + y? GaN, AlGaN, InGaN, AlN, InN, and AlInN, and may be doped with a p-type dopant such as Mg, Zn, Ca, Sr, or Ba.

A transparent conductive layer 33 may be formed on the second conductive semiconductor layer 29 and a second electrode 38 may be formed on a portion of the transparent conductive layer 33.

The first electrode 35 may be formed on a portion of the first conductivity type semiconductor layer 25 of the light emitting structure 30. For this, the second conductive type semiconductor layer 29 and the active layer 27 may be removed by mesa etching and a part of the upper surface of the first conductive type semiconductor layer 25 may be removed. The first electrode 35 may be formed on the first conductive type semiconductor layer 25 thus removed.

The second electrode 38 is formed on the top of the light emitting element 1 and the first electrode 35 is formed on the side surface of the light emitting element 1 so that the first and second electrodes 35, Since the current flows to the light emitting structure 30 corresponding to the shortest path between the first and second electrodes 35 and 38 when the power is applied to the active layer 27 of the light emitting structure 30, .

Therefore, by forming the transparent conductive layer 33 on the entire area of the second conductivity type semiconductor layer 29 between the second conductive type semiconductor layer 29 and the second electrode 38, A current is spread to the entire region of the transparent conductive layer 33 through the electrode 38 to flow a current between the entire region of the first electrode 35 and the transparent electrode layer 33, The light emission efficiency can be improved.

The first and second electrodes 35 and 38 may be formed of the same electrode material or different electrode materials.

The first and second electrodes 35 and 38 include opaque metal materials such as aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni), platinum (Pt) ), Tungsten (W), copper (Cu), and molybdenum (Mo), but is not limited thereto.

The transparent conductive layer 33 is formed of a conductive material having excellent light transmittance and electrical conductivity for transmitting light. For example, ITO, IZO (In-ZnO), GZO (Ga-ZnO), AZO (Al-Ga ZnO), IGZO (In-Ga ZnO), IrOx, RuOx, RuOx / ITO, Ni / IrOx / Au and Ni / IrOx / Au / ITO.

FIG. 4 is a plan view illustrating a light emitting device according to a second embodiment, FIG. 5 is a cross-sectional view taken along line AA 'of FIG. 4, and FIG. 6 is a cross- Fig.

Instead of the first and second electrodes 35 and 38 of the first embodiment, the nanostructure 19 may serve as an electrode in the second embodiment. Therefore, the nanostructure 19 and the electrode layer 50 can be arranged in a structure in which they are vertically overlapped with each other. In addition, in the second embodiment, the electrode layer 50 has a larger size than the active layer 27 of the light emitting structure 30 and has a reflection characteristic, so that the light generated in the active layer 27 is reflected forward The luminous efficiency can be improved.

4 to 6, the light emitting device 1A according to the second embodiment includes a supporting substrate 41, a bonding layer 43, an electrode layer 50, a channel layer 47, a light emitting structure 30, The nanostructure 19 and the protective layer 57. The nanostructure 19 may be formed of, for example,

The supporting substrate 41, the bonding layer 43, and the electrode layer 50 may form an electrode member for supplying power.

The supporting substrate 41 may have a function as an electrode as well as supporting a plurality of layers formed thereon. The support substrate 41 may supply power to the light emitting structure 30 together with the nanostructure 19. [

The support substrate 41 may be formed of a metal material or a semiconductor material, but the present invention is not limited thereto. The support substrate 41 may be formed of a material having high electrical conductivity and high thermal conductivity. The support substrate 41 may be formed of a metal such as Ti, Cr, Ni, Al, Pt, Au, W, , Copper alloy (Cu Alloy), molybdenum (Mo), and copper-tungsten (Cu-W). The supporting substrate may be a semiconductor material including at least one selected from the group consisting of Si, Ge, GaAs, GaN, ZnO, SiGe and SiC, for example.

The support substrate 41 may be plated and / or deposited under the light emitting structure 30, or may be attached in a sheet form, but the present invention is not limited thereto.

The bonding layer 43 may be formed on the supporting substrate 41. The bonding layer 43 is formed between the electrode layer 50 and the supporting substrate 41. The bonding layer 43 may serve as a medium for enhancing the adhesive force between the electrode layer 50 and the supporting substrate 41.

The bonding layer 43 may include a barrier metal or a bonding metal. The bonding layer 43 may be formed of a metal material having high bonding and thermal conductivity. The bonding layer 43 may include at least one selected from the group consisting of Ti, Au, Sn, Ni, Nb, Cr, Ga, In, Bi, Cu, Ag and Ta.

A barrier layer (not shown) may be formed on the bonding layer 43. The barrier layer is diffused into the electrode layer 50 or the light emitting structure 30 on which the bonding layer 43 and the support substrate 41 are formed and the characteristics of the light emitting device 1A Can be prevented from being lowered.

The barrier layer may comprise a single layer selected from the group consisting of Ni, Pt, Ti, W, V, Fe, and Mo, or a stack of two or more thereof.

The barrier layer may be formed to be in contact with the lower surface of the electrode layer 50.

The upper surface of the bonding layer 43 may have a groove formed so that the peripheral region extends to the upper direction, that is, the light emitting structure 30 with respect to the center region, but the present invention is not limited thereto. The electrode layer 50 may be formed on the groove or in contact with the central region of the upper surface of the bonding layer 43, but the present invention is not limited thereto.

Although not shown, the upper surface of the bonding layer 43 may be located on the same line in both the center region and the peripheral region.

In other words, the entire area of the upper surface of the bonding layer 43 may have a flat surface. In this case, the electrode layer 50 may be formed on the central region of the upper surface of the bonding layer 43, or may be formed on the entire region of the upper surface of the bonding layer 43.

In other words, the size of the electrode layer 50 may be smaller than the size of the bonding layer 43 or the size of the bonding layer 43.

The upper surface of the electrode layer 50 and the upper surface of the channel layer 47 may be formed on the same line.

The lower surface of the electrode layer 50 and the lower surface of the channel layer 47 may be formed at different positions. That is, the electrode layer 50 is formed on the central region of the bonding layer 43 where the groove of the bonding layer 43 is formed, and the channel layer 47 is formed on the peripheral region of the bonding layer 43 The lower surface of the electrode layer 50 may be formed at a position lower than the lower surface of the channel layer 47. [

5 and 6, a portion of the electrode layer 50 may be formed to overlap with the lower surface of the channel layer 47 in the vertical direction. In other words, the inner region of the channel layer 47 may extend inward beyond the end of the electrode layer 50.

 The electrode layer 50 reflects light incident from the light emitting structure 30, thereby improving light extraction efficiency.

The electrode layer 50 may be in ohmic contact with the light emitting structure 30 to allow a current to flow to the light emitting structure 30.

The electrode layer 50 may include a reflective layer formed to contact the upper surface of the bonding layer 43 and an ohmic contact layer formed between the upper surface of the reflective layer and the lower surface of the light emitting structure.

The electrode layer may be formed of a single layer in which a reflective material and an ohmic contact material are mixed. In this case, the electrode layer 50 need not be formed separately from the reflection layer and the ohmic contact layer.

At least one or more alloys selected from the group consisting of Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au and Hf are used as the reflective material. I never do that. The ohmic contact material may be a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc oxide (IZTO), indium aluminum zinc oxide (IAZO) gallium zinc oxide (IGTO), aluminum zinc oxide (AZO), antimony tin oxide (ATO), gallium zinc oxide (GZO), IrOx, RuOx, RuOx / ITO, Ni, Ag, Ni / IrOx / Au, and at least one selected from the group consisting of Ni / IrOx / Au / ITO may be used.

The electrode layer 50 may be composed of multiple layers including, for example, IZO / Ni, AZO / Ag, IZO / Ag / Ni, and AZO / Ag / Ni.

The electrode layer 50 may at least be in ohmic contact with the light emitting structure 30. Therefore, the current is smoothly supplied to the light emitting structure 30, which is in ohmic contact with the electrode layer 50, so that the light emitting efficiency can be improved.

The electrode layer 50 may be formed on the lower surface of the light emitting structure 30 and the channel layer 47. The electrode layer 50 may have a larger area than at least the light emitting structure 30, particularly, the active layer 27, in order to reflect all the light from the light emitting structure 30.

A channel layer 47 may be formed on the electrode layer 50. The channel layer 47 may be formed along the peripheral region of the second conductive semiconductor layer 29. The channel layer 47 may be formed around the edge region of the electrode layer 50. That is, the channel layer 47 may be formed in a peripheral region between the light emitting structure 30 and the electrode layer 50. In detail, the channel layer 47 may be formed at least partially in the electrode layer 50 and the light emitting structure 30. For example, a portion of the upper surface of the channel layer 47 is in contact with the second conductive type semiconductor layer 29, and a portion of the inner surface and the lower surface of the channel layer 47 is in contact with the electrode layer 50 But it is not limited thereto. Another region of the lower surface of the channel layer 47 may be formed in contact with the peripheral region of the upper surface of the bonding layer 43.

The channel layer 47 may prevent an electrical short between the side surface of the bonding layer 43 and the side surface of the light emitting structure 30 due to an external foreign substance. If the electrode layer 50 is formed on the entire region of the bonding layer 43 and the outer surface of the electrode layer 50 is exposed to the outside, the channel layer 47 may be formed on the side surface of the electrode layer 50, It is possible to prevent an electrical short between the side surfaces of the light emitting structure 30.

In addition, the channel layer 47 may include a laser scribing process for separating a plurality of chips into individual chip units by securing an area in contact with the light emitting structure 30, and a laser lift- It is possible to effectively prevent the light emitting structure 30 from being peeled off from the electrode layer 50 in the LLO process.

If the light emitting structure 30 is ever-etched during the chip separation process, the electrode layer 50 may be exposed. In this case, electrical shorting may occur between the electrode layer 50 and the active layer 27 of the light emitting structure 30 due to foreign substances or the like in the side region. The channel layer 47 may prevent the electrode layer 50 from being exposed by the ever-etching of the light emitting structure 30 during the chip separation process.

The channel layer 47 may include at least one selected from the group consisting of insulating materials such as SiO ₂ , SiO _x , SiO _x N _y , Si ₃ N ₄ , and Al ₂ O ₃ . The channel layer 47 may be formed of a metal material, but the present invention is not limited thereto.

The light emitting structure 30 may be formed on the electrode layer 50 and the channel layer 47.

The side surface of the light emitting structure 30 may be formed to be vertical or inclined by etching to divide a plurality of chips into individual chip units. For example, the side surface of the light emitting structure 30 may be formed by isolation etching.

The light emitting structure 30 may include a plurality of compound semiconductor materials of Group 2 to Group 6 elements.

The light emitting structure 30 includes a second conductive type semiconductor layer 29, an active layer 27 on the second conductive type semiconductor layer 29, and a first conductive type semiconductor layer 25 on the active layer 27, . ≪ / RTI >

In this case, the lower surface of the second conductive type semiconductor layer 29 may be formed to be in contact with the upper surface of the electrode layer 50 and the upper surface of the channel layer 47, but the present invention is not limited thereto.

In addition, the size of the active layer 27 may be smaller than the size of the electrode layer 50 in order to reflect all the light generated in the active layer 27.

The channel layer 47 may include a first channel region overlapping the second conductivity type semiconductor layer 29 in the vertical direction and a second channel region not overlapping the second conductivity type semiconductor layer 29 have.

The first channel region may extend inward from an end of the second conductivity type semiconductor layer 29 and may overlap the first conductivity type semiconductor layer 25 in a vertical direction.

The second channel region may extend outward from the first channel region to the end of the bonding layer 43.

The second conductive semiconductor layer 29 may be formed on the electrode layer 50 and the channel layer 47. The second conductive semiconductor layer 29 may be a p-type semiconductor layer including a p-type dopant. The second conductive semiconductor layer 29 may be formed of a compound semiconductor of Group 2 to Group 6 elements. The second conductive semiconductor layer 29 may include one selected from the group consisting of GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP and AlGaInP. The p-type dopant may be Mg, Zn, Ga, Sr, Ba, or the like. The first conductive semiconductor layer 25 may be formed as a single layer or a multilayer, but is not limited thereto.

The second conductive semiconductor layer 29 serves to supply a plurality of carriers, for example, holes to the active layer 27.

The active layer 27 may be formed on the second conductive semiconductor layer 29 and may include any one of a single quantum well structure, a multiple quantum well structure (MQW), a quantum dot structure, or a quantum wire structure. It is not limited.

The active layer 27 may be formed with a period of a well layer and a barrier layer using a compound semiconductor material of Group 2 to Group 6 elements. The compound semiconductor material for use as the active layer 27 may be GaN, InGaN, or AlGaN. Therefore, the active layer 27 may include, for example, the period of the InGaN well layer / GaN barrier layer, the period of the InGaN well layer / AlGaN barrier layer, the period of the InGaN well layer / InGaN barrier layer, I never do that.

The active layer 27 recombines the electrons supplied from the first conductivity type semiconductor layer 25 with the holes supplied from the second conductivity type semiconductor layer 29, It is possible to generate light of a wavelength corresponding to a bandgap determined by the material.

Although not shown, a conductive cladding layer may be formed on and / or below the active layer 27, and the conductive cladding layer may be formed of an AlGaN-based semiconductor. For example, a p-type cladding layer including a p-type dopant is formed between the second conductive semiconductor layer 29 and the active layer 27, and the active layer 27 and the first conductive semiconductor layer 25, an n-type cladding layer including an n-type dopant may be formed.

The conductive cladding layer serves as a guide for preventing a plurality of holes and a plurality of electrons supplied to the active layer 27 from moving to the first conductivity type semiconductor layer 25 and the second conductivity type semiconductor layer 29 do. Therefore, the holes and electrons supplied to the active layer 27 are recombined with each other by the conductive cladding layer, so that the luminous efficiency of the light emitting device can be improved.

The first conductive semiconductor layer 25 may be formed on the active layer 27. The first conductive semiconductor layer 25 may be an n-type semiconductor layer including an n-type dopant. The first conductive semiconductor layer 25 may be formed of a compound semiconductor of Group 2 to Group 6 elements. The first conductive semiconductor layer 25 may include one selected from the group consisting of GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP and AlGaInP. The n-type dopant may be Si, Ge, Sn, Se, Te, or the like. The first conductive semiconductor layer 25 may be formed as a single layer or a multilayer, but is not limited thereto.

The first conductivity type semiconductor layer 25, the active layer 27, and the second conductivity type semiconductor layer 29 may be grown in this order when the light emitting structure 30 is grown.

Referring to FIG. 5, a plurality of nanostructures 19 may be formed on the light emitting structure 30, specifically, the first conductive semiconductor layer 25.

4, the nanostructure 19 includes a plurality of graphene patterns 13, a plurality of nanotextures 16 formed on the respective graphene patterns 13, And a connecting portion 20 for connecting between the first and second connecting portions.

Since the graphene pattern 13 and the nanotexture 16 have already been described in detail in the first embodiment, a detailed description thereof will be omitted here.

The connecting portion 20 may also be formed of the same material as the graphene pattern 13, for example, graphite. Therefore, when forming the graphene pattern 13, the connection portion 20 may be formed at the same time.

The graphene pattern 13 may be connected to all adjacent graphene patterns 13 using the connecting portion 20.

The connection here may include an electrical connection as well as a physical connection.

The graphen pattern 13 may be connected to any one of the graphen patterns 13 when power is applied to the pattern of the graphen pattern 13 as the graphen patterns 13 are connected by the connecting portion 20. [ A current can flow through the connection portion 20 with a plurality of graphene patterns 13 adjacent thereto. In other words, current spreading can be generated from any one of the graphene patterns to a plurality of graphene patterns 13 adjacent thereto.

7, a plurality of graphene patterns 13 and connecting portions 20 are formed to correspond to all the regions of the electrode layer 50, so that the entire area of the electrode layer 50 and the entire surface of the nanostructure 50 The current flows in the plane direction between all the regions of the active layer 27 in the vertical direction, and the light emission efficiency can be improved by emitting light in the entire region of the active layer 27 of the light emitting structure 30.

A plurality of nanotextures 16 may be formed on the lower surface of the graphene pattern 13. That is, the nanotexture 16 may extend from the lower surface of the graphene pattern 13 into the first conductive semiconductor layer 25.

The nanotexture 16 may be formed of zinc oxide (ZnO), but is not limited thereto.

As described in the first embodiment, the nanotexture 16 can be grown to have a good crystallinity without causing dislocations in the light emitting structure 30.

The numerical range with respect to the nanostructure 19 may be the same as that described in the first embodiment, but it is not limited thereto.

The gap between the graphen patterns 13 may be 0.1 탆 to 100 탆, but is not limited thereto. The gap between the graphen patterns 13 may be 10 [mu] m to 50 [mu] m.

Accordingly, the first conductive semiconductor layer 25 may or may not be formed between the graphene patterns 13. For example, the first conductive semiconductor layer 25 may be extended to the same position as the upper surface of the graphene pattern 13 through the gap between the graphen patterns 13.

The nanotexture 16 may be a plurality of nanorods, but is not limited thereto. The nanorods may be spaced apart from each other at regular intervals or spaced apart from each other at irregular intervals.

The nanotexture 16 may have a structure having a height greater than a width, but the present invention is not limited thereto.

The height and width of the nanotexture 16 may be substantially the same as the nanotexture 16 of the first embodiment.

Although the nanostructure 19 is formed in the first conductive semiconductor layer 25 in FIGS. 5 and 6, the present invention is not limited thereto.

The nanostructure 19 may be formed in a buffer layer (not shown). In this case, a buffer layer may be formed on the first conductive semiconductor layer 25, and the nanostructure 19 may be formed on the buffer layer. That is, the nanotexture 16 may be formed from the lower surface of the graphene pattern 13 into the buffer layer.

When the height of the nanotexture 16 is greater than the thickness of the buffer layer, the nanotexture 16 may be formed inside the first conductive semiconductor layer 25 through the buffer layer. However, I never do that.

A protective layer 57 may be formed on the light emitting structure. For example, a protective layer 57 may be formed on at least a side surface of the light emitting structure 30. More specifically, the protective layer 57 is formed in a peripheral region of the upper surface of the first conductivity type semiconductor layer 25 at one end, and the side surface of the first conductivity type semiconductor layer 25, the active layer 27, And the other end of the second conductive semiconductor layer 29 may be formed on a part of the upper surface of the channel layer 47, but the present invention is not limited thereto.

The protective layer 57 may prevent an electrical short between the light emitting structure 30 and the supporting substrate 41 and protect the light emitting device 1A from external impact. The protective layer 57 may be formed of a material having excellent transparency and insulation. The protective layer 57 is, for example, SiO _2, SiO _x, SiO _x N _y, Si ₃ N _4, TiO _2, and may include one selected from the group consisting of Al ₂ O _3, but this is not limited Do not.

The passivation layer 57 may include the same material as the channel layer 47, but the present invention is not limited thereto.

In the light emitting device 1A of the second embodiment, the electrode is provided. However, since the graphene pattern 13 of the nanostructure 19 has a function as an electrode, the nanostructure 19 19 and the electrode layer 50 so that the light emitting device 1A can emit light.

In addition, since the nanostructure 19 is a graphene pattern 13 or zinc oxide is a transparent material, light generated in the light emitting structure 30 can be emitted upward through the nanostructure 19. In other words, since the light transmittance of the nanostructure 19 is very good, the light generated in the light emitting structure 30 can pass through the nanostructure 19 without loss.

The nanostructure 19 of the embodiment can be applied to the horizontal type light emitting device of the first embodiment and the vertical type light emitting device of the second embodiment as well as the flip type light emitting device. In the case of a flip-type light emitting device, the nanostructure 19 may have a reflective layer made of a metal material having excellent reflectance instead of the transparent conductive layer 33 shown in FIG. 1 (first embodiment). In this case, the light generated in the light emitting structure 30 may be reflected by the reflective layer and emitted to the outside through the substrate 10.

8 to 14 are process drawings for manufacturing the light emitting device according to the second embodiment.

Referring to FIG. 8, a nanostructure 19 may be formed on a growth substrate 100.

The growth substrate 100 is a substrate for growing the light emitting structure, and may be formed of a material suitable for semiconductor material growth, that is, a carrier wafer. In addition, the growth substrate 100 may be formed of a material having a similar lattice constant to the light emitting structure and having thermal stability, or may be a conductive substrate or an insulating substrate.

The growth substrate 100 may be formed of at least one selected from the group consisting of sapphire (Al ₂ O ₃ ), SiC, Si, GaAs, GaN, ZnO, Si, GaP, InP and Ge.

The nanostructure 19 may include a plurality of graphene patterns 13, a connecting portion 20, and a plurality of nanotextures 16.

The graphene pattern 13 and the connecting portion 20 may be formed at the same time.

The graphene pattern 13 and the connection portion 20 may be formed in advance and attached to the growth substrate 100.

Alternatively, a graphene film is formed on the growth substrate 100 using, for example, a chemical synthesis method, a CVD growth method, an epitaxial synthesis method, or the like, and the graphene film is patterned to form a plurality of graphene patterns 13, A plurality of connecting portions 20 connecting the connecting portions 13 may be formed.

Next, a plurality of nanotextures 16 may be formed on the graphene pattern 13 by using a deposition process or a growth process using zinc oxide on the growth substrate 100.

The nanotexture 16 may be formed using, for example, a CVD growth method or a sputtering method, but the present invention is not limited thereto.

The nanotexture 16 may be formed of zinc oxide (ZnO), but is not limited thereto.

Accordingly, the nanostructure 19 can be formed by the plurality of graphene patterns 13, the plurality of connection portions 20, and the plurality of nanotextures 16. [

9, a first conductivity type semiconductor layer 25, an active layer 27 and a second conductivity type semiconductor layer 29 are sequentially grown on the nano structure 19 to form a light emitting structure 30 .

The light emitting structure 30 may be formed using a metal organic chemical vapor deposition (MOCVD) method, a chemical vapor deposition (CVD) method, a plasma enhanced chemical vapor deposition (PECVD) method, a molecular beam epitaxy May be formed using a method such as molecular beam epitaxy (MBE) or hydride vapor phase epitaxy (HVPE), but the present invention is not limited thereto.

A buffer layer (not shown) may be formed between the light emitting structure 30 and the growth substrate 100 to mitigate the difference in lattice constant between the two. That is, the buffer layer may be grown on the nanostructure 19, and the light emitting structure 19 may be grown on the buffer layer.

The first conductive semiconductor layer 25 may be formed on the growth substrate 100 and the nanostructure 19. [ The first conductive semiconductor layer 25 may be an n-type semiconductor layer including an n-type dopant.

The first conductivity type semiconductor layer 25 is formed on the growth substrate 100 between the graphene patterns 13 of the nanostructure 19 and the nano structure of the nanostructure 19 16 on the graphene pattern 13.

The lattice constant of zinc oxide is about 3.25, the lattice constant of sapphire used in the growth substrate 100 is about 4.78, and the lattice constant of GaN that can be used for the first conductivity type semiconductor layer 25 is about 3.18 .

The first conductivity type semiconductor layer 25 and the nanostructures 19 are formed on the first conductive semiconductor layer 25 and the growth substrate 100, The first conductivity type semiconductor layer 25 can be grown well on the nanostructure 19 without dislocations.

The active layer 27 is formed on the first conductive semiconductor layer 25 and may include any one of a multiple quantum well structure (MQW), a quantum dot structure, and a quantum wire structure. However, the present invention is not limited thereto.

The active layer 27 recombines the electrons supplied from the first conductivity type semiconductor layer 25 and the holes supplied from the second conductivity type semiconductor layer 29, It is possible to generate light having a wavelength corresponding to the band gap determined by the material.

The second conductive semiconductor layer 29 may be formed on the active layer 27. The second conductive semiconductor layer 29 may be a p-type semiconductor layer including a p-type dopant.

Referring to FIG. 10, a channel layer 47 may be formed on the second conductive semiconductor layer 29.

The channel layer 47 may be formed on the second conductive semiconductor layer 29. For example, the channel layer 47 may be formed on the peripheral region of the second conductive semiconductor layer 29, but is not limited thereto.

Since the insulating material of the channel layer 47 has been described above, it will be omitted.

Referring to FIG. 11, an electrode layer 50, a bonding layer 43, and a supporting substrate 41 may be formed on the channel layer 47 and the second conductive semiconductor layer 29.

The electrode layer 50 may include an ohmic contact layer and a reflective layer sequentially stacked on the second conductive semiconductor layer 29.

The electrode layer 50 may include a single layer formed by mixing an ohmic contact material and a reflective material on the second conductive type semiconductor layer 29.

As the reflective material, at least one or more alloys selected from the group consisting of Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au and Hf are used. As the ohmic contact material, a conductive material and a metal material may be selectively used. The ohmic contact material may be at least one of indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc oxide (IZTO), indium aluminum zinc oxide (IAZO), indium gallium zinc oxide (IGZO) tin oxide, AZO (aluminum zinc oxide), ATO (antimony tin oxide), GZO (gallium zinc oxide), IrOx, RuOx, RuOx / ITO, Ni, Ag, Ni / IrOx / Au, At least one selected from the group consisting of ITO can be used.

The bonding layer 43 may be formed to enhance adhesion between the supporting substrate 41 and the electrode layer 50.

The bonding layer 43 may include at least one selected from the group consisting of Ti, Au, Sn, Ni, Nb, Cr, Ga, In, Bi, Cu, Ag and Ta.

The supporting substrate 41 may have a function as an electrode as well as supporting a plurality of layers formed thereon. The supporting substrate 41 may supply power to the light emitting structure 30 together with the electrodes.

The support substrate 41 may be formed of a metal such as Ti, Cr, Ni, Al, Pt, Au, W, , Molybdenum (Mo), and copper-tungsten (Cu-W).

The support substrate 41 may be plated and / or deposited on the light emitting structure 30, or may be attached in a sheet form, but the present invention is not limited thereto.

Referring to FIG. 12, after the growth substrate 100 is turned 180 °, the growth substrate 100 may be removed.

The growth substrate 100 may be removed by laser lift off (LLO), chemical lift off (CLO), physical polishing or the like, but the present invention is not limited thereto.

When the growth substrate 100 is removed through the laser lift-off method, a laser is intensively irradiated to the interface between the growth substrate 100 and the first conductivity type semiconductor layer 25, So that the substrate 100 can be separated from the nanostructure 19.

When the growth substrate 100 is removed through the chemical etching method, the growth substrate 100 may be removed by wet etching so that the first conductivity type semiconductor layer 25 is exposed.

When the growth substrate 100 is removed using the physical polishing method, the growth substrate 100 is physically polished directly to expose the first conductivity type semiconductor layer 25, It can be removed sequentially from the top.

In the second embodiment, a nanostructure 19 is formed between the light emitting structure 30 and the growth substrate 100. Since the bonding strength of the nanostructure 19 with the growth substrate 100 is relatively weak, The growth substrate 100 can be easily separated from the nanostructure 19 by irradiation. In other words, the nanostructure 19 can easily separate the growth substrate 100. Therefore, when the growth substrate 100 is not easily separated, the laser is irradiated for a long time, and cracks and other defects can be prevented from being generated in the light emitting structure 30 due to the impact of the laser power.

Referring to FIG. 13, a mesa etching may be performed so that a side surface of the light emitting structure 30 and a side surface of the channel layer 47 are obliquely exposed. A groove in which the light emitting structure 30 is not present may be formed on the channel layer 47 by the mesa etching. In other words, the second conductive type semiconductor layer 29, the active layer 27, and the first conductive type semiconductor layer 25 formed on the channel layer 47 are removed by the mesa etching to form a groove .

Since the channel layer 47 serves as a stopper, the first conductive semiconductor layer 25, the active layer 27, and the second conductive semiconductor layer 25 in the outer region of the groove are etched by the mesa etching, The electrode layer 50, the bonding layer 43 and the supporting substrate 41 under the channel layer 47 are not removed, although a part of the region of the layer 29 is removed.

Referring to FIG. 14, a protective layer 57 may be formed on the light emitting structure 30.

That is, the protective layer 57 is formed on the side surface of the first conductivity type semiconductor layer 25, the side surface of the first conductivity type semiconductor layer 25, A portion of the upper surface of the protective layer 57 may be formed to extend to the side of the second conductive semiconductor layer 29 and the side surface of the second conductive semiconductor layer 29.

The protective layer 57 may prevent electric short-circuit between the light emitting structure 30 and the supporting substrate 41. The protective layer 57 may be formed of a material having excellent transparency and insulation. The protective layer 57 is, for example, SiO _2, SiO _x, SiO _x N _y, Si ₃ N _4, TiO _2, and may include one selected from the group consisting of Al ₂ O _3, but this is not limited Do not.

The passivation layer 57 may include the same material as the channel layer 47.

15 is a cross-sectional view illustrating a light emitting device package according to an embodiment.

Referring to FIG. 15, a light emitting device package according to an embodiment includes a body 101, first and second lead electrodes 103 and 105 provided on the body 101, A light emitting element 1 according to the first and second embodiments, which is installed and is supplied with power from the first lead electrode 103 and the second lead electrode 105; And a molding member 113 for molding.

The body 101 may be formed of a silicon material, a synthetic resin material, or a metal material, and an inclined surface may be formed around the light emitting element 1.

The first lead electrode 103 and the second lead electrode 105 are electrically separated from each other and provide power to the light emitting element 1.

The first and second lead electrodes 103 and 105 may reflect light generated from the light emitting element 1 to increase the light efficiency and may heat the heat generated from the light emitting element 1 to the outside It may also serve as a discharge.

The light emitting device 1 may be mounted on any one of the first lead electrode 103, the second lead electrode 105 and the body 101. The first and second lead electrodes 103 and 105 may be formed by wire, die bonding, And may be electrically connected to the second lead electrodes 103 and 105, but the present invention is not limited thereto.

The light emitting device 1 is electrically connected to one of the first and second lead electrodes 103 and 105 through one wire 109. However, The light emitting element 1 may be electrically connected to the first and second lead electrodes 103 and 15 by using a plurality of wires and the light emitting element 1 may be electrically connected to the first and second leads 103 and 15 without using wires. And may be electrically connected to the electrodes 103 and 105.

The molding member 113 surrounds the light emitting element 1 to protect the light emitting element 1. [ In addition, the molding member 113 may include a phosphor to change the wavelength of the light emitted from the light emitting device 1.

The light emitting device package 200 according to the embodiment includes a COB (Chip On Board) type. The upper surface of the body 101 is flat, and a plurality of light emitting devices are installed in the body 101.

The light emitting device or the light emitting device package according to the embodiment can be applied to a light unit. The light unit can be applied to a display device and a lighting device such as a lighting lamp, a traffic light, a vehicle headlight, an electric signboard, and an indicator lamp.

10, 100: substrate
13: Graphene pattern
16: Nano-texture
19: Nano structures
20: Connection
22: buffer layer
25: First conductive type semiconductor layer
27:
29: second conductive type semiconductor layer
30: Light emitting structure
33: transparent conductive layer
35: first electrode
38: Second electrode
41: Support substrate
43: bonding layer
47: channel layer
50: electrode layer
57: Protective layer

Claims (19)

Board;
An electrode layer disposed on the substrate;
A light emitting structure having a second conductivity type semiconductor layer on the electrode layer, an active layer on the second conductivity type semiconductor layer, and a first conductivity type semiconductor layer on the active layer; And
A plurality of nanostructures on the first conductive semiconductor layer,
The nanostructure may be formed,
A plurality of graphene patterns spaced apart from each other on the first conductive type semiconductor layer; And
A plurality of nanotextures extending from the bottom surface of the graphene pattern into the first conductive type semiconductor layer and disposed in each of the plurality of graphene patterns; And
And a connection part formed on the graphene pattern and connecting the plurality of graphene patterns,
Wherein the nanostructure is vertically overlapped with the electrode layer. The method according to claim 1,
Wherein the graphene pattern and the connection portion are formed of the same material. 3. The method of claim 2,
Wherein the nanotexture is formed of a material different from the graphene pattern and the connecting portion. The method according to claim 1,
Wherein the nanotexture is in contact with the first conductive semiconductor layer. 5. The method of claim 4,
And a channel layer formed in a peripheral region between the light emitting structure and the electrode layer,
Wherein a part of the top surface of the channel layer is in contact with the second conductivity type semiconductor layer, and the inner surface and the bottom surface of the channel layer are in contact with the electrode layer. 6. The method according to claim 2 or 5,
And a part of the upper surface of the first conductivity type semiconductor layer is exposed to the outside. 6. The method according to any one of claims 1 to 5,
Wherein a width of the connection portion is narrower than a width of the graphene pattern. 6. The method according to any one of claims 1 to 5,
Wherein a height of the nanotexture is greater than a width of the nanotexture. 6. The method according to any one of claims 1 to 5,
And a protective layer is disposed on a side surface of the light emitting structure and a part of a top surface of the graphene pattern. delete delete delete delete delete delete delete delete delete delete

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