KR101944964B1 - Semiconductor memory device and memory system including the same - Google Patents

Semiconductor memory device and memory system including the same Download PDF

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Publication number
KR101944964B1
KR101944964B1 KR1020120038169A KR20120038169A KR101944964B1 KR 101944964 B1 KR101944964 B1 KR 101944964B1 KR 1020120038169 A KR1020120038169 A KR 1020120038169A KR 20120038169 A KR20120038169 A KR 20120038169A KR 101944964 B1 KR101944964 B1 KR 101944964B1
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KR
South Korea
Prior art keywords
clock
signal
pulse
memory
clock signal
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KR1020120038169A
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Korean (ko)
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KR20130083767A (en
Inventor
전영진
엄윤주
조영철
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삼성전자주식회사
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Priority to US61/586,301 priority
Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority claimed from US13/729,068 external-priority patent/US8934317B2/en
Publication of KR20130083767A publication Critical patent/KR20130083767A/en
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Publication of KR101944964B1 publication Critical patent/KR101944964B1/en

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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222Clock generating, synchronizing or distributing circuits within memory device
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/225Clock input buffers
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/06Address interface arrangements, e.g. address buffers

Abstract

The semiconductor memory device according to the technical idea of the present invention includes a clock input buffer which is turned on / off according to a clock enable signal and outputs a buffered clock signal by buffering a clock signal received from the outside, And the internal clock signal generating operation includes an internal clock generating unit that is started based on a chip select signal.

Description

Description SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM CONTAINING SEMICONDUCTOR MEMORY DEVICE

Technical aspects of the present invention relate to a semiconductor device, and more particularly, to a semiconductor memory device and a memory system including the semiconductor memory device.

In recent years, the capacity and speed of a semiconductor memory device used as a memory device in electronic systems have been increasing. DRAM, as an example of a semiconductor memory device, is widely used in computer systems as a personal computer or a server. One type of DRAM is a synchronous semiconductor memory device (SDRAM) that operates in synchronism with a clock signal of the system. As an example of a synchronous semiconductor memory device (SDRAM), in synchronization with rising and falling edges of a system clock signal There are double-data-rate (DDR) SDRAMs that carry data.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor memory device capable of reducing an unnecessary standby current in a power down mode.

Another object to be solved by the technical idea of the present invention is to provide a memory system capable of reducing unnecessary standby current in a power down mode for a memory device.

According to an aspect of the present invention, a semiconductor memory device includes a clock input buffer which is turned on / off according to a clock enable signal and outputs a buffered clock signal by buffering a clock signal received from the outside; And generating an internal clock signal based on the buffered clock signal, wherein the operation of generating the internal clock signal includes an internal clock generator starting based on a chip selection signal.

In an exemplary embodiment, the internal clock generator may generate the internal clock signal by starting dispensing operation for the buffered clock signal when the first pulse of the chip selection signal is input. The pulse width of the first pulse of the chip select signal may be greater than one clock period of the clock signal.

In one embodiment, the internal clock generator starts dividing operation on the buffered clock signal when the clock enable signal is activated and the first pulse of the chip selection signal is input to generate the internal clock signal .

In embodiments, the clock input buffer may buffer the clock signal when the clock enable signal is activated.

In some embodiments, the semiconductor memory device may further include a clock input buffer control unit for controlling on / off of the clock input buffer according to the clock enable signal. The semiconductor memory device may further include an internal clock generation control unit for controlling on / off of the internal clock generator according to the clock enable signal.

In embodiments, the semiconductor memory device may further comprise a command / address buffer for buffering a command / address to be synchronized with the internal clock signal. Wherein the chip select signal comprises a first pulse for initiating a dividing operation of the internal clock generator and a second pulse subsequent to the first pulse, wherein the command / And can receive the command / address when input. A second clock after an even number of clock cycles from a first clock of the clock signal corresponding to a time point at which the first pulse is generated may be included in an interval in which the second pulse is held.

According to an aspect of the present invention, there is provided a memory system including: a memory controller for generating a chip select signal including a first pulse, a clock signal, and a clock enable signal; And a memory device for starting an operation of generating an internal clock signal based on the clock signal when the clock enable signal is activated and the first pulse of the chip selection signal is input.

In one embodiment, the chip select signal may further include a second pulse subsequent to the first pulse, and in a period in which the second pulse is maintained, A second clock after an even number of clock cycles from the first clock may be included. The memory controller may further include a command / address providing unit that provides a command / address to the memory device to be synchronized with the second clock of the clock signal while the second pulse of the chip select signal is held.

The memory controller may further include a pulse width controller for controlling the pulse width of the first pulse of the chip selection signal to be larger than one clock period of the clock signal.

In embodiments, the memory device may further include: a clock input buffer that is turned on / off in accordance with the clock enable signal and outputs a buffered clock signal by buffering the clock signal; And an internal clock generator for generating the internal clock signal by dividing the buffered clock signal, wherein the dividing operation for the buffered clock signal is started based on the first pulse of the chip selection signal.

In the semiconductor memory device according to the technical idea of the present invention, the clock input buffer is turned on / off according to the clock enable signal so that the clock input buffer can be turned off in the power down mode by buffering the clock signal received from the outside. Also, when the clock input buffer is turned off, the internal clock generator may be turned off. Therefore, it is possible to prevent an unnecessary standby current from flowing in the clock input buffer and the internal clock generation unit in the power down mode.

Also, in the semiconductor device according to the technical idea of the present invention, the internal clock generator starts the dividing operation on the buffered clock signal based on the first pulse of the chip select signal to generate the internal clock signal, Even if the buffer and the internal clock generating unit are turned off, the internal clock signal can be stably generated when the power down mode ends.

In the semiconductor memory device according to the technical idea of the present invention, the command / address buffer receives the command based on the second pulse of the chip select signal, so that even if the clock input buffer and the internal clock generator are turned off in the power down mode, The command can be stably received.

1 is a block diagram illustrating a memory system in accordance with one embodiment of the present invention.
2 is a timing diagram showing a comparative example of the operation of the memory system of Fig.
3 is a block diagram illustrating an example of a memory controller included in FIG.
4 is a block diagram illustrating an example of a clock generator included in FIG.
5 is a timing diagram illustrating an example of operation of a memory system including a memory device including the memory controller of FIG. 3 and the clock generator of FIG.
6 is a circuit diagram showing an example of a clock generator of FIG.
7 is a circuit diagram showing an example of a CA buffer included in FIG.
8 is a circuit diagram showing an example of the data buffer included in FIG.
9 is a block diagram showing another example of the clock generator included in FIG.
10 is a circuit diagram showing an example of the clock generator of FIG.
11 is a block diagram showing another example of the memory controller included in Fig.
12 is a timing chart showing an example of the operation of the memory system including the memory controller of Fig.
13 is a block diagram illustrating an example of a memory device included in FIG.
14 is a block diagram illustrating a memory system in accordance with another embodiment of the present invention.
15 is a block diagram illustrating a memory system in accordance with another embodiment of the present invention.
16 is a block diagram illustrating a computing system in accordance with an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art. The present invention is capable of various modifications and various forms, and specific embodiments are illustrated and described in detail in the drawings. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for similar elements in describing each drawing. In the accompanying drawings, the dimensions of the structures are enlarged or reduced from the actual dimensions for the sake of clarity of the present invention.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In this application, the terms "comprises", "having", and the like are used to specify that a feature, a number, a step, an operation, an element, a part or a combination thereof is described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

Also, the terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms may be used for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

1 is a block diagram illustrating a memory system in accordance with one embodiment of the present invention.

Referring to Figure 1, the memory system 1 may include a memory controller 10 and a memory device 20.

The memory controller 10 may control the memory device 20 by providing data or control signals to the memory device 20. Specifically, the memory controller 10 receives the clock signal / inverted clock signal CK / CKB, the clock enable signal CKE, the chip selection signal CSB, the command / address CA, Vref CA, data DQ, and data reference voltage Vref DQ.

In another embodiment, the memory controller 10 may provide only the clock signal CK, not the clock signal / inverted clock signal (CK / CKB). In another embodiment, the memory controller 10 may not provide a command / address reference voltage Vref CA and a data reference voltage Vref DQ, and the command / address reference voltage Vref CA and data (Vref DQ) may be generated in the memory device 20. [

The memory device 20 may include a clock generator 21, a command / address buffer 22, and a data buffer 23. Although not shown, the memory device 20 may further include a memory cell array in which a plurality of memory cells are arranged. The clock generation unit 21 receives the clock signal / inverted clock signal CK / CKB, the clock enable signal CKE and the chip selection signal CSB from the memory controller 10 and outputs the internal clock signal ICK Can be generated.

2 is a timing diagram showing a comparative example of the operation of the memory system of Fig.

Referring to FIG. 2, the clock signal / inverted clock signal (CK / CKB) output from the memory controller 10 may be a signal having a first frequency. On the other hand, the internal clock signal ICK output from the clock generating unit 21 may be a signal having a second frequency lower than the first frequency. For example, the second frequency may be one-half of the first frequency.

For example, in the case of a high-speed operation of about 3.2 Gbps, it is difficult to achieve high mass productivity while adjusting the set up / hold margin between the command CMD and the clock signal CK . Therefore, the second frequency of the internal clock signal ICK of the memory device 20 is used by being lowered to 1/2 of the first frequency of the clock signal / inverted clock signal CK / CKB, (gear down mode). Since the second frequency of the internal clock signal ICK can be reduced to 1/2 of the first frequency of the clock signal / inverted clock signal CK / CKB by using the gear-down mode, the pulse width can be doubled, The setup / hold margin can be secured at the level of a 1.6 Gbps memory device.

In the gear-down mode, the memory controller 10 provides the memory device 20 with a clock signal / inverted clock signal (CK / CKB) having twice the frequency as the internal clock signal ICK. The memory controller 10 also outputs the command CMD to the memory device 20 in synchronization with the clock signal / inverted clock signal CK / CKB when the chip select signal CSB for the memory device 20 is activated. . However, the command / address buffer 22 included in the memory device 20 operates to be synchronized with the internal clock signal ICK.

Therefore, in order for the memory controller 10 to provide the command CMD in synchronization with the internal clock signal ICK, the even-numbered clock nCK + N * EVEN of the clock signal CK (where n and N are natural numbers , And EVEN is an even number, for example, 2) to the rising edge of the CMD. In this way, the memory controller 10 can provide the command CMD in accordance with the rising edge of the internal clock signal ICK, and the command / address buffer 22 outputs the command CMD to be synchronized with the internal clock signal ICK. As shown in FIG.

Therefore, even in the power down mode in which the clock enable signal CKE is deactivated and the power supply is cut off to the main configuration of the memory device 20, the clock generator 21 generates the clock signal / inverted clock signal CK / CKB) to generate the internal clock signal ICK. As a result, inevitable standby current flows in the power down mode of the memory device 20.

Referring again to FIG. 1, in this embodiment, the clock generator 21 can be turned on / off according to the clock enable signal CKE and generates the internal clock signal ICK based on the chip select signal CSB. It is possible to start the generating operation of FIG. Specifically, when the first pulse (P1, see FIG. 5) of the chip select signal CSB is activated, the clock generating section 21 can start the operation of generating the internal clock signal ICK. Accordingly, in the power down mode, the clock generation section 21 can be turned off, thereby reducing the standby current flowing in the clock generation section 21 in the power down mode. A detailed description of the operation of the clock generator 21 will be given later with reference to FIG.

The command / address buffer 22 can receive the command / address CA and the command / address reference voltage Vref CA from the memory controller 10 and output the internal command / address CAI. At this time, the command / address buffer 22 operates to be synchronized with the internal clock signal ICK and can be turned on / off according to the internal clock signal ICK. Thus, if the internal clock signal ICK is not generated in the power down mode, the command / address buffer 22 can also be turned off, thereby also reducing the quiescent current flowing in the command / address buffer 22 .

The data buffer 23 can receive the data DQ and the data reference voltage Vref DQ from the memory controller 10 and output the internal data DI. The data buffer 23 can receive the data DO read out from the memory device 20 and output it to the memory controller 10. [ At this time, the data buffer 23 operates to be synchronized with the internal clock signal ICK and can be turned on / off according to the internal clock signal ICK. Therefore, when the internal clock signal ICK is not generated in the power-down mode, the data buffer 23 can also be turned off, thereby reducing the standby current flowing in the data buffer 23.

3 is a block diagram illustrating an example of a memory controller included in FIG.

3, the memory controller 10a includes a clock generating unit 11, a clock enable generating unit 12, a chip selection signal generating unit 13, a command / address providing unit 14, a first reference voltage A data input / output unit 14, and a second reference voltage generation unit 16. The first and second reference voltage generation units 16 and 17 may be the same as those shown in FIG.

The clock generator 11 may generate a clock signal / inverted clock signal (CK / CKB) having a first frequency and provide it to the clock generator 21 included in the memory device 20. In another embodiment, the clock generating unit 11 may generate only the clock signal CK and provide it to the clock generating unit 21. The command / address CA output from the command / address providing unit 14 and the data DQ output from the data input / output unit 15 are supplied to the memory device 20 (not shown) so as to be synchronized with the clock signal / inverted clock signal CK / ). ≪ / RTI >

The clock enable generator 12 may generate the clock enable signal CKE and provide the generated clock enable signal CKE to the clock generator 21 included in the memory device 20. [ At this time, the clock enable signal CKE may be provided to the memory device 20 to indicate whether to enter the power down mode. For example, when the clock enable signal CKE is deactivated, the memory device 20 indicates a state of entering the power down mode, and when the clock enable signal CKE is activated, Mode can be displayed.

The chip selection signal generation unit 13 may generate a chip selection signal CSB and provide the chip selection signal CSB to the clock generation unit 21 included in the memory device 20. [ At this time, the chip select signal CSB may indicate a selection operation for the memory device 20. [ Specifically, the chip select signal CSB may include a first pulse P1 and a subsequent second pulse P2 (see FIG. 5).

When the first pulse P1 is activated, the memory device 20 can start the generation operation of the internal clock signal ICK. Therefore, the first pulse Pl of the chip select signal CSB can be used as a trigger signal for generation of the internal clock signal ICK. On the other hand, when the second pulse P2 is activated, the memory device 20 can receive the command / address CA. Therefore, the second pulse P2 of the chip select signal CSB can be used as a trigger signal for reception of the command / address CA.

The command / addressing unit 14 may provide the command / address to the command / address buffer 22 included in the memory device 20. [ The first reference voltage generator 15 may generate and provide a first reference voltage Vref CA, which is a command / address reference voltage, to the command / address buffer 22 included in the memory device 20.

The data input and output unit 16 can provide the write data DQ to the data buffer 23 included in the memory device 20 and output the read data DQ from the data buffer 23 included in the memory device 20. [ May be received. The second reference voltage generator 17 may generate and supply a second reference voltage Vref DQ, which is a data reference voltage, to the data buffer 23 included in the memory device 20.

4 is a block diagram illustrating an example of a clock generator included in FIG.

Referring to FIG. 4, the clock generator 21A may include a clock input buffer 211, a clock input buffer controller 212, and an internal clock generator 213.

The clock input buffer 211 can generate the buffered clock signal B_CK by buffering the clock signal / inverted clock signal CK / CKB received from the memory controller 10. At this time, the clock input buffer 211 can be turned on / off based on the clock enable signal CKE received from the memory controller 10. The clock input buffer 211 may receive only the clock signal CK from the memory controller 10 and may buffer the clock signal CK to generate the buffered clock signal B_CK have.

The clock input buffer control unit 212 can control on / off of the clock input buffer 211 according to the clock enable signal CKE received from the memory controller 10. [ For example, when the clock enable signal CKE is activated, the clock input buffer control unit 212 can control the clock input buffer 211 so that the clock input buffer 211 is turned on. On the other hand, when the clock enable signal CKE is inactivated, the clock input buffer control unit 212 can control the clock input buffer 211 such that the clock input buffer 211 is turned off. Accordingly, in the power-down mode in which the clock enable signal CKE is inactivated, the clock input buffer 211 does not operate, thereby reducing unnecessary standby current.

The internal clock generator 213 can generate the internal clock signal ICK by dividing the buffered clock signal B_CK. At this time, the dividing operation of the internal clock generating unit 213 with respect to the buffered clock signal B_CK may be started based on the chip select signal CSB. Specifically, when the first pulse P1 of the chip select signal CSB is input, the internal clock generator 213 starts the frequency dividing operation on the buffered clock signal B_CK to generate the buffered clock signal B_CK, Lt; RTI ID = 0.0 > ICK < / RTI >

More specifically, when the clock enable signal is activated and the first pulse P1 of the chip select signal CSB is input, the internal clock generating unit 213 starts the dividing operation on the buffered clock signal B_CK And generate the internal clock signal ICK from the buffered clock signal B_CK. Therefore, in the power down mode in which the clock enable signal CKE is inactivated, the internal clock generator 213 does not operate, and thus unnecessary standby current can be reduced.

In this embodiment, the internal clock generator 213 may generate the internal clock signal ICK having the second frequency by dividing the first frequency of the buffered clock signal B_CK by 1/2. However, the present invention is not limited to this, and the internal clock generator 213 divides the first frequency of the buffered clock signal B_CK by 1 / N to generate the internal clock signal ICK having the second frequency Where N is a natural number.

5 is a timing diagram illustrating an example of operation of a memory system including a memory device including the memory controller of FIG. 3 and the clock generator of FIG.

5, in the power down mode in which the clock enable signal CKE is inactivated, for example, when the logic level of the clock enable signal CKE is low, the clock input buffer 21 and the internal clock The generation section 22 may be turned off, and accordingly, the internal clock signal ICK may not be generated. Therefore, unnecessary standby current for generating the internal clock signal ICK in the power-down mode can be reduced.

When the clock enable signal CKE is activated and the logic level of the clock enable signal CKE transitions to " High " to escape from the power down mode, the clock input buffer 21 and the internal clock generation The portion 22 can be turned on so that the clock input buffer 21 can buffer the clock signal / inverted clock signal (CK / CKB).

When the clock enable signal CKE is activated and the first pulse P1 of the chip select signal CSB is activated, for example, when the logic level of the clock enable signal CKE is high and the chip select signal The internal clock generating unit 22 starts the dividing operation on the buffered clock signal B_CK and outputs the internal clock signal B_CK from the buffered clock signal B_CK, Signal (ICK). As described above, the first pulse P1 of the chip select signal CSB can be used as a trigger signal to start the dividing operation in the internal clock generating section 22. [

When the clock enable signal CKE is activated and the second pulse P2 of the chip select signal CSB is activated, for example, when the logic level of the clock enable signal CKE is & The command / address providing unit 15 can provide the command CMD to the command / address buffer 21 when the logical level of the second pulse P2 of the command / address buffer CSB is low. At this time, the second pulse P2 of the chip select signal CSB may be provided to include the even-numbered clock of the clock signal / the inverted clock signal CK / CKB.

More specifically, in the interval in which the second pulse P2 of the chip select signal CSB is held, the even number of clocks CK1 from the first clock CK1 of the clock signal CK corresponding to the time when the first pulse P1 is generated, And the second clock CK2 after the period has elapsed. At this time, when the first clock CK1 is nCK, the second clock CK2 may be nCK + N * EVEN (where n and N are natural numbers). Thus, when the second pulse P2 of the chip select signal CSB is activated, the command / address buffer 21 can receive the command CMD to be synchronized with the internal clock signal ICK.

According to the present embodiment, when the first pulse P1 of the chip select signal CSB is generated, the internal clock generator 213 can start the operation of generating the internal clock signal ICK. Further, when the second pulse P2 of the chip select signal CSB is generated, the command / address providing unit 15 can supply the command CMD so as to be synchronized with the second clock CK2 of the clock signal CK have. As a result, the command / address buffer 22 can receive the command CMD to be synchronized with the internal clock signal ICK.

Therefore, even if the clock input buffer 211 and the internal clock generator 213 are turned off in the power down mode and the clock input buffer 211 and the internal clock generator 213 are turned on when the power supply is released from the power down mode, The command / address buffer 22 can receive the command CMD to be synchronized with the internal clock signal ICK. As a result, the memory device 20 can operate stably even in the gear-down mode.

6 is a circuit diagram showing an example of a clock generator of FIG.

Referring to FIG. 6, the clock generator 21a may include a clock input buffer 211a, a clock input buffer controller 212a, and an internal clock generator 213a. Furthermore, the clock generating unit 21a may further include first and second inverters INV1 and INV2.

The clock input buffer 211a receives the clock signal CK through the first input terminal, receives the inverted clock signal CKB through the second input terminal, and outputs the buffered signal based on the differential signaling And can output the clock signal B_CK. At this time, the clock input buffer 211a can be turned on / off by a control operation of the clock input buffer control unit 212a.

The clock input buffer control unit 212a includes a first NMOS transistor MN1 having a gate to which the clock enable signal CKE is applied, a drain to be connected to the clock input buffer 211a, and a source to be connected to the ground terminal . In this manner, the clock input buffer control unit 212a can be implemented as a current source for the clock input buffer 211a.

Specifically, when the logic level of the clock enable signal CKE is high, the first NMOS transistor MN1 is turned on. Thus, the first NMOS transistor MN1 supplies the driving current of the clock input buffer 211a, so that the clock input buffer 211a is turned on. On the other hand, when the logic level of the clock enable signal CKE is 'low', the first NMOS transistor MN1 is turned off. Because the first NMOS transistor MN1 does not supply the driving current to the clock input buffer 211a, the clock input buffer 211a is turned off.

The internal clock generator 213a receives the output signal of the inverted output terminal QB through the set terminal S and receives the chip select signal CSB through the reset terminal R, And a flip-flop receiving the clock signal B_CK. Thus, the internal clock generator 213a can generate the internal clock signal ICK by dividing the buffered clock signal B_CK. In another embodiment, the reset terminal R may receive a control signal that is enabled when the first pulse Pl of the chip select signal CSB is applied.

7 is a circuit diagram showing an example of the command / address buffer included in FIG.

Referring to FIG. 7, the command / address buffer 22a may include an input buffer 221 and a controller 222.

The input buffer 221 receives the command / address CA from the memory controller 10 via the first input terminal and receives the command / address reference voltage Vref CA from the memory controller 10 via the second input terminal. And can output an internal command / address (CAI) based on the differential signaling scheme. In another embodiment, the command / address reference voltage Vref CA may be a reference voltage generated in a reference voltage generator (not shown) in the memory device 20.

The control unit 222 may include a second NMOS transistor MN2 having a gate receiving the internal clock signal ICK, a drain coupled to the input buffer 221, and a source coupled to the ground terminal. As such, the control unit 222 may be implemented in the form of a current source. Thus, if the internal clock signal ICK is not provided in the power down mode, the input buffer 221 is turned off. On the other hand, when the internal clock signal ICK is provided, the input buffer 221 can output an internal command / address (CAI) synchronized with the internal clock signal ICK.

8 is a circuit diagram showing an example of the data buffer included in FIG.

Referring to FIG. 8, the data buffer 23a may include an output buffer 231, a first controller 231, an input buffer 233, and a second controller 234.

The output buffer 231 can buffer the data DO read out from the memory device 20 and provide it to the memory controller 10. [ The output terminal of the output buffer 231 may be connected to the first input terminal of the input buffer 233.

The first control part 232 may include a third NMOS transistor MN3 having a gate to which the internal clock signal ICK is applied, a drain to be connected to the output buffer 231, and a source to be connected to the ground terminal. As such, the first controller 232 may be implemented in the form of a current source. Thus, if the internal clock signal ICK is not provided in the power-down mode, the output buffer 231 is turned off.

The input buffer 233 receives the data DQ supplied from the memory controller 10 through the first input terminal and receives the reference voltage Vref DQ for data provided from the memory controller 10 through the second input terminal, And can output the internal data DI based on the differential signaling scheme. In another embodiment, the reference voltage for data Vref DQ may be a reference voltage generated in a reference voltage generator (not shown) in memory device 20. [

The second control unit 234 may include a fourth NMOS transistor MN4 having a gate to which the internal clock signal ICK is applied, a drain to be connected to the input buffer 233, and a source to be connected to the ground terminal. As such, the second controller 234 may be implemented in the form of a current source. Thus, if the internal clock signal ICK is not provided in the power down mode, the input buffer 233 is off. On the other hand, when the internal clock signal ICK is provided, the input buffer 233 can output the internal data DI synchronized with the internal clock signal ICK.

9 is a block diagram showing another example of the clock generator included in FIG.

9, the clock generation unit 21B may include a clock input buffer 211, a clock input buffer control unit 212, an internal clock generation unit 213, and an internal clock generation control unit 214. Some of the components included in the clock generator 21B according to the present embodiment are substantially the same as the components included in the clock generator 21A in Fig. The same components are denoted by the same reference numerals, and the same components as those of the clock generator 21A of FIG. 4 are not repeatedly described. Hereinafter, the difference between the clock generating unit 21A of FIG. 4 and the clock generating unit 21B of the present embodiment will be described in detail.

The internal clock generation control unit 214 may control the internal clock generation unit 213 to turn on and off according to the clock enable signal CKE received from the memory controller 10. [ For example, when the clock enable signal CKE is activated, the internal clock generation control unit 214 may control the internal clock generation unit 213 so that the internal clock generation unit 213 is turned on. Meanwhile, when the clock enable signal CKE is inactivated, the internal clock generation control unit 214 may control the internal clock generation unit 213 so that the internal clock generation unit 213 is turned off. Accordingly, in the power down mode in which the clock enable signal CKE is inactivated, the internal clock generator 213 does not operate, thereby reducing unnecessary standby current.

10 is a circuit diagram showing an example of the clock generator of FIG.

10, the clock generation unit 21b may include a clock input buffer 211b, a clock input buffer control unit 212b, an internal clock generation unit 213b, and an internal clock generation control unit 214b. Furthermore, the clock generating unit 21b may further include first and second inverters INV1 and INV2.

The clock input buffer 211b receives the clock signal CK through the first input terminal, receives the inverted clock signal CKB through the second input terminal, and outputs the buffered clock signal B_CK Can be output. At this time, the clock input buffer 211b may be turned on / off by a control operation of the clock input buffer control unit 212b.

The clock input buffer control section 212b includes a fifth NMOS transistor MN5 having a gate to which the clock enable signal CKE is applied, a drain to be connected to the clock input buffer 211b, and a source to be connected to the ground terminal . As such, the clock input buffer control unit 212b can be implemented as a current source for the clock input buffer 211b.

The internal clock generator 213b receives the output signal of the inverted output terminal QB through the set terminal S and receives the chip select signal CSB through the reset terminal RS, And a flip-flop receiving the clock signal B_CK. Thus, the internal clock generator 213b can generate the internal clock signal ICK by dividing the buffered clock signal B_CK.

The internal clock generation control unit 214b includes a sixth NMOS transistor MN6 having a gate to which the clock enable signal CKE is applied, a drain to be connected to the internal clock generation unit 213b, and a source to be connected to the ground terminal. can do. As described above, the internal clock generation control unit 214b can be implemented as a current supply source for the internal clock generation unit 213b.

Specifically, when the logic level of the clock enable signal CKE is high, the sixth NMOS transistor MN6 is turned on. Thus, the sixth NMOS transistor MN6 supplies the driving current of the internal clock generator 213b, so that the internal clock generator 213b is turned on. On the other hand, when the logic level of the clock enable signal CKE is 'low', the sixth NMOS transistor MN6 is turned off. As a result, the sixth NMOS transistor MN6 does not supply the driving current of the internal clock generator 213b, so that the internal clock generator 213b is turned off.

11 is a block diagram showing another example of the memory controller included in Fig.

11, the memory controller 10b includes a clock generating unit 11, a clock enable generating unit 12, a chip selection signal generating unit 13, a command / address providing unit 14, a first reference voltage A data input / output unit 16, a second reference voltage generation unit 17, and a pulse width control unit 18. [0030] Some of the components included in the memory controller 10b according to the present embodiment are substantially the same as those included in the memory controller 10a of Fig. The same components are denoted by the same reference numerals, and the same components as those of the memory controller 10a of FIG. 3 are not repeatedly described. Hereinafter, the difference between the memory controller 10a of FIG. 3 and the memory controller 10b of the present embodiment will be described in detail.

12 is a timing chart showing an example of the operation of the memory system including the memory controller of Fig.

11 and 12, intersymbol interference (ISI) may occur when the first pulse P1 'of the chip select signal CSB is smaller than the pulse width of the other pulse. For example, the logic level of the chip select signal CSB is '1', '1', '0', '1', '1', the logic level '1' corresponds to a voltage level of 5V, It is assumed that level '0' corresponds to a voltage level of 0V. At this time, the voltage level of the logic level '0' may not be lowered to 0V due to the influence of the logic levels '1' in the succeeding logic level. This may be referred to as duty error amplification.

The pulse width controller 18 controls the pulse width of the chip selection signal CSB such that the pulse width of the first pulse P1 'of the chip selection signal CSB (see FIG. 13) is larger than one clock period of the clock signal / inverted clock signal CK / It is possible to control the pulse width of the first pulse P1 'of the first pulse signal CSB. More specifically, the pulse width control unit 18 can control the pulse width of the first pulse P1 'of the chip selection signal CSB by dividing the chip selection signal CSB.

In one embodiment, the pulse width control unit 18 can control the pulse width of the first pulse Pl 'of the chip selection signal CSB to be doubled. In other words, the pulse width control unit 18 controls the pulse width of the first pulse P1 'of the chip selection signal CSB so that the pulse width of the first pulse Pl' of the chip selection signal CSB corresponds to two clock periods of the clock signal CK. The pulse width of the pulse P1 'can be controlled. Thus, the logic level of the chip select signal CSB may be '1', '1', '0', '0', '1', '1'. At this time, a period in which the logic level is '0' can be sufficiently secured.

In this way, by controlling the pulse width of the first pulse P1 'of the chip selection signal CSB to be larger than one clock period of the clock signal CK, even if an error due to a variation in the clock signal CK occurs The interval during which the first pulse P1 'is held may include the rising edge of the clock signal CK. Therefore, the clock generating unit 21 can stably generate the internal clock signal ICK at the rising edge of the clock signal CK. Accordingly, the memory device 20 can operate more stably and improve the signal integrity in the memory device 20. [

In another embodiment, the pulse width control unit 18 can control the pulse width of the first pulse Pl 'of the chip selection signal CSB to be 4 or 8 times. In other words, the pulse width control unit 18 controls the pulse width of the chip selection signal CSB so that the pulse width of the first pulse Pl 'of the chip selection signal CSB corresponds to four clock periods or eight clock periods of the clock signal CK. Can control the pulse width of the first pulse P1 ' Thus, the logic level of the chip select signal CSB is 1, 1, 0, 0, 0, 0, 1, 1 or 1, 0 ',' 0 ',' 0 ',' 0 ',' 0 ',' 0 ',' 0 ',' 0 ',' 0 ',' 1 ' At this time, the memory device 20 can operate stably and the signal integrity can be improved in the memory device 20 since a period in which the logic level is '0' can be more sufficiently secured.

In the power down mode in which the clock enable signal CKE is inactivated, for example, the logic level of the clock enable signal CKE is low, the clock input buffer 21 and the internal clock generator 22 So that the internal clock signal ICK may not be generated. Therefore, unnecessary standby current for generating the internal clock signal ICK in the power-down mode can be reduced.

When the clock enable signal CKE is activated and the logic level of the clock enable signal CKE transitions to " High " to escape from the power down mode, the clock input buffer 21 and the internal clock generation The portion 22 can be turned on so that the clock input buffer 21 can buffer the clock signal / inverted clock signal (CK / CKB).

When the clock enable signal CKE is activated and the first pulse P1 'of the chip select signal CSB is activated, for example, when the logic level of the clock enable signal CKE is high and the chip select signal CSB is low, The internal clock generator 22 starts the dividing operation on the buffered clock signal B_CK and outputs the buffered clock signal B_CK from the buffered clock signal B_CK when the logic level of the first pulse Pl ' It is possible to generate the internal clock signal ICK. In this manner, the first pulse P1 'of the chip selection signal CSB can be used as a trigger signal to start the dividing operation in the internal clock generating section 22.

When the clock enable signal CKE is activated and the second pulse P2 of the chip select signal CSB is activated, for example, when the logic level of the clock enable signal CKE is & The command / address providing unit 15 can provide the command CMD to the command / address buffer 21 when the logical level of the second pulse P2 of the command / address buffer CSB is low. At this time, the second pulse P2 of the chip select signal CSB may be provided to include the even-numbered clock of the clock signal / the inverted clock signal CK / CKB.

More specifically, in the interval in which the second pulse P2 of the chip select signal CSB is held, the even number of clocks CK1 from the first clock CK1 of the clock signal CK corresponding to the time when the first pulse P1 is generated, And the second clock CK2 'after the period has elapsed. At this time, when the first clock CK1 is nCK, the second clock CK2 'may be nCK + N * EVEN (where n and N are natural numbers and EVEN is an even number, have). Thus, when the second pulse P2 of the chip select signal CSB is activated, the command / address buffer 21 can receive the command CMD to be synchronized with the internal clock signal ICK.

According to the present embodiment, when the first pulse Pl 'of the chip select signal CSB is generated, the internal clock generating unit 213 can start the operation of generating the internal clock signal ICK. When the second pulse P2 of the chip select signal CSB is generated, the command / address providing unit 15 provides the command CMD to be synchronized with the second clock CK2 'of the clock signal CK . As a result, the command / address buffer 22 can receive the command CMD to be synchronized with the internal clock signal ICK.

Therefore, even if the clock input buffer 211 and the internal clock generator 213 are turned off in the power down mode and the clock input buffer 211 and the internal clock generator 213 are turned on when the power supply is released from the power down mode, The command / address buffer 22 can receive the command CMD to be synchronized with the internal clock signal ICK. As a result, the memory device 20 can operate stably even in the gear-down mode.

13 is a block diagram illustrating an example of a memory device included in FIG.

13, the memory device 20A may include a clock generator 21, control logic 24, a row decoder 25, a memory cell array 26, and an input / output circuit 27.

The clock generating unit 21 may be implemented according to the embodiments described above with reference to FIGS. 1 to 13, and a detailed description thereof will be omitted. The control logic 24 may communicate with the row decoder 25 and the input / output circuit 27. In this embodiment, the control logic 24 may include the command / address buffer 22 and the data buffer 23 of FIG.

The row decoder 25 can communicate with the memory cell array 26 via a plurality of word lines WL. And may include a plurality of memory cells of the memory cell array 26. The input / output circuit 27 may include a column decoder, a sense amplifier, and a page buffer, which communicate with the memory cell array 26 through a plurality of bit lines BL.

14 is a block diagram illustrating a memory system in accordance with another embodiment of the present invention.

Referring to Fig. 14, the memory system 1 'may include a memory controller 10 and a memory module MM1. In Fig. 15, only one memory module (MM1) is shown for the sake of convenience, but the memory system 1 'may include two or more memory modules. The memory controller 10 and the memory module MM1 may be disposed on the motherboard in the memory system 1 '. Some of the components included in the memory system 1 'according to the present embodiment are substantially the same as the components included in the memory system 1 of Fig. The same components are denoted by the same reference numerals, and the same components as the memory system 1 of FIG. 1 are not repeatedly described. Hereinafter, the difference between the memory system 1 of FIG. 1 and the memory system 1 'of this embodiment will be described in detail.

The memory controller 10 supplies the clock signal / inverted clock signal CK / CKB, the clock enable signal CKE, the chip select signal CSB, the command / address CA and the data DQ to the signal line or system bus Lt; / RTI > In another embodiment, the memory controller 10 may further provide a command / address reference voltage Vref CA and a data reference voltage Vref DQ. The memory controller 10 may include the memory controller 10a of FIG. 3 or the memory controller 10b of FIG.

The plurality of memory devices MEM1, MEM2, ..., MEMn may be mounted on the memory module MM1, and each of the plurality of memory devices MEM1, MEM2, ..., And a clock generator 21 for providing a clock signal ICK. The clock generating unit 21 may be implemented according to the embodiments described above with reference to FIGS. 1 to 13, and a detailed description thereof will be omitted.

15 is a block diagram illustrating a memory system in accordance with another embodiment of the present invention.

Referring to Figure 15, the memory system 1 " may include a memory controller 10 and a memory module MM2. Although only one memory module MM2 is shown for convenience in Figure 16, May include two or more memory modules. Memory controller 10 and memory module MM2 may be located on a motherboard in memory system 1 ". Some of the components included in memory system 1 " 1 is substantially the same as the components included in the memory system 1 of Fig. The same components are denoted by the same reference numerals, and the same components as the memory system 1 of FIG. 1 are not repeatedly described. Hereinafter, the differences between the memory system 1 of Fig. 1 and the memory system 1 " according to the present embodiment will be described in detail.

The memory controller 10 supplies the clock signal / inverted clock signal CK / CKB, the clock enable signal CKE, the chip select signal CSB, the command / address CA and the data DQ to the signal line or system bus Lt; / RTI > In another embodiment, the memory controller 10 may further provide a command / address reference voltage Vref CA and a data reference voltage Vref DQ. The memory controller 10 may include the memory controller 10a of FIG. 3 or the memory controller 10b of FIG.

The memory module MM2 may include a plurality of memory devices MEM1, MEM2, ..., and MEMn and may include an internal clock signal common to the plurality of memory devices MEM1, MEM2, ..., And a clock generator 21 for providing a clock signal ICK. The clock generating unit 21 may be implemented according to the embodiments described above with reference to FIGS. 1 to 13, and a detailed description thereof will be omitted.

16 is a block diagram illustrating a computing system in accordance with an embodiment of the present invention.

16, a computing system 1000 may include a processor 1100, a memory device 1200, a storage device 1300, an input / output device 1400, and a power supply device 1500. 17, the computing system 1000 may further include ports capable of communicating with, or communicating with, video cards, sound cards, memory cards, USB devices, and the like .

The processor 1100 may perform certain calculations or tasks. According to an embodiment, the processor 1100 may be a micro-processor, a central processing unit (CPU). The processor 1100 is coupled to the memory device 1200, the storage device 1300, and the input / output device 1400 via a bus 1600, such as an address bus, a control bus, and a data bus, Lt; / RTI > In accordance with an embodiment, the processor 1100 may also be coupled to an expansion bus, such as a Peripheral Component Interconnect (PCI) bus.

Memory device 1200 may store data necessary for operation of computing system 1000. For example, the memory device 1200 may be implemented as a DRAM, a mobile DRAM, an SRAM, a PRAM, an FRAM, an RRAM, and / or an MRAM. have. The storage device 1300 may include a solid state drive, a hard disk drive, a CD-ROM, and the like.

The input / output device 1400 may include input means such as a keyboard, a keypad, a mouse and the like, and output means such as a printer, a display, and the like. Power supply 1500 may supply the operating voltage required for operation of computing system 1000.

In the above description, the clock generating unit 21 is included in the memory device 20, but the present invention is not limited thereto. The clock generator 21 may be included in a semiconductor device operating at a clock frequency different from an external clock frequency. In this case, the clock generating section 21 can be turned off in the power down mode for the semiconductor device, thereby reducing the standby current in the semiconductor device.

While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

1, 1 ', 1 ": memory system
10: Memory controller
20: Memory device
11: clock generator
12: clock enable generator
13: chip selection signal generation unit
14: Command /
15: a first reference voltage generating section
16: Data I /
17: a second reference voltage generator
18: Pulse width control section
21: clock generator
22: Command / address buffer
23: Data buffer

Claims (10)

  1. A clock input buffer which is turned on / off according to a clock enable signal and outputs a buffered clock signal by buffering a clock signal received from the outside;
    An internal clock generating unit for generating an internal clock signal based on the buffered clock signal, the internal clock signal generating operation being started based on a chip select signal; And
    And a command / address buffer for buffering a command / address to be synchronized with the internal clock signal,
    Wherein the chip select signal includes a first pulse for starting the dividing operation of the internal clock generator and a second pulse following the first pulse,
    And the command / address buffer receives the command / address when the second pulse of the chip selection signal is input.
  2. The method according to claim 1,
    Wherein the internal clock generator starts dividing operation on the buffered clock signal when the first pulse of the chip selection signal is input to generate the internal clock signal.
  3. 3. The method of claim 2,
    Wherein the pulse width of the first pulse of the chip select signal is greater than one clock period of the clock signal.
  4. The method according to claim 1,
    And a clock input buffer control unit for controlling on / off of the clock input buffer according to the clock enable signal.
  5. 5. The method of claim 4,
    And an internal clock generation control unit for controlling on / off of the internal clock generation unit according to the clock enable signal.
  6. delete
  7. The method according to claim 1,
    Wherein a second clock after an even number of clock cycles from a first clock of the clock signal corresponding to a time point at which the first pulse is generated is included in an interval in which the second pulse is held.
  8. A memory controller for generating a chip select signal, a clock signal and a clock enable signal including a first pulse and a second pulse following the first pulse; And
    And a memory device for initiating an operation of generating an internal clock signal based on the clock signal when the clock enable signal is activated and the first pulse of the chip select signal is input,
    Wherein the memory controller comprises a command / address provider for providing a command / address to the memory device while the second pulse is held.
  9. 9. The method of claim 8,
    A second clock after an even number of clock cycles from a first clock of the clock signal corresponding to a time when the first pulse is generated is included in an interval in which the second pulse is held,
    The command /
    And provides the command / address to the memory device to be synchronized to the second clock of the clock signal while the second pulse of the chip select signal is held.
  10. 9. The method of claim 8,
    The memory controller includes:
    Further comprising a pulse width control unit for controlling the pulse width of the first pulse of the chip selection signal to be larger than one clock period of the clock signal.
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