KR101795531B1 - Reconfiguable system on chip - Google Patents

Abstract

A reconfigurable system on chip is provided. A system on chip for processing and outputting an input sensor signal includes an external memory for receiving and storing program codes for system on chip driving stored in an external storage medium during a booting process; and a processing part including a plurality of tiny processors. Each of the tiny processor loads a program code corresponding to an address indicated by a CPU among the program codes stored in the external memory, processes a sensor signal according to a loaded program code, and outputs a sensor signal processed by another tiny processor defined in the loaded program code or a peripheral device. It is possible to easily cope with modification or change of an algorithm for processing the sensor signal.

Description

Reconfigurable system on chip < RTI ID = 0.0 >

The present invention relates to reconfigurable system-on-a-chip.

A system-on-chip (SoC) that processes sensor signals in a system such as Internet of Things (IoT) generally includes a processor such as a CPU (Central Processing Unit) and a DSP (Digital Signal Processor) Analyzes the input value, and applies a predetermined algorithm to output a desired value.

1 is a diagram schematically showing a configuration of a system-on-chip according to the prior art.

Referring to FIG. 1, a system-on-chip 100 according to the related art includes a CPU 110, a drive program of the CPU 110 among information stored in the external memory 130 On chip 100 from a storage medium (for example, an external flash memory) provided outside the system-on-chip 100, an internal memory 120 which is stored in the system- An input unit 140 for receiving a sensor signal from a sensor device external to the system-on-chip 100, and a software program to be ported to the CPU 110. The external memory 130 receives and stores necessary information, Hardware engine 150. Although not shown, an internal memory controller and an external memory controller for controlling the operation of each of the internal memory 120 and the external memory 130 and controlling each memory to function in cooperation with other components such as the CPU 110 are further included do.

The illustrated system-on-chip 100 implements a software program, which has been conventionally ported to the CPU 110 itself for processing and outputting sensor signals, as a hardware engine, so that a relatively low-cost CPU 110 can be used And can operate at a relatively low clock speed, thereby eliminating the need for a fine process and reducing power consumption.

However, the system-on-chip 100 having the hardware engine 150 is difficult to cope with when the algorithm for processing the sensor signal is modified or changed, and is designed to be limited to only one application field, There is a problem that it can not be used.

Korean Patent Publication No. 10-2013-0028505 (reconfigurable processor, code conversion device and method of reconfigurable processor)

According to the present invention, microcontroller units (MCU) of low-grade are operated individually according to a loaded program, but they are interlocked with each other in a pipeline structure, so that it is possible to easily cope with modification or change of an algorithm for sensor signal processing, And to provide a reconfigurable system-on-chip that enables high-end sensor signal processing with a low-cost system.

Other objects of the present invention will become readily apparent from the following description.

According to an aspect of the present invention, there is provided a system-on-chip for processing and outputting an input sensor signal, the system comprising: an external memory for receiving and storing a program code for system-on-chip driving stored in an external storage medium during a booting process; And a processing unit including a plurality of Tiny processors, wherein each Tiny processor loads the program code corresponding to the address indicated by the CPU among the program codes stored in the external memory, And outputs a sensor signal processed by another Tiny program or peripheral device defined in the loaded program code.

The plurality of Tiny processors may be ordered to process the sensor signals input by the respective loaded program codes into a pipeline structure.

Wherein each of the plurality of Tiny processors comprises: a command memory for storing a program code corresponding to an address indicated by a CPU; An input buffer receiving a sensor signal or a sensor signal processed by a preceding Tiny processor in a pipeline structure; A processor for processing the sensor signal input to the input buffer according to a program code stored in the command memory; An output buffer for outputting sensor signals processed by the processor to a Tiny processor or a peripheral device that trails in a pipeline structure; And a processing controller for controlling the processor to perform processing according to the program code stored in the command memory.

Each of the Tiny processors may be assigned a clock frequency such that the processing time according to the loaded program code is completed.

The external storage medium stores a memory map including program codes to be loaded into each Tiny processor in each of a plurality of application fields. In a booting process, a program code corresponding to an application field allocated to the system- Lt; / RTI >

Other aspects, features, and advantages will become apparent from the following drawings, claims, and detailed description of the invention.

According to the embodiment of the present invention, the low-level MCUs are individually operated according to the loaded programs, and are configured to interlock with each other in a pipeline structure, so that it is possible to easily cope with modification or change of the algorithm for sensor signal processing, It is possible to process high-level sensor signals with a low-cost system.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 schematically shows the configuration of a system-on-a-chip according to the prior art;
2 is a schematic diagram of a configuration of a system-on-chip according to an embodiment of the present invention.
3 schematically illustrates a configuration of a Tiny processor according to an embodiment of the present invention;
FIG. 4 schematically illustrates a configuration of a memory map according to an embodiment of the present invention; FIG.
5 illustrates a variety of pipeline processing structures of a Tiny processor in accordance with an embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The present invention is capable of various modifications and various embodiments, and specific embodiments are illustrated in the drawings and described in detail in the detailed description. It is to be understood, however, that the invention is not to be limited to the specific embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprises" or "having" and the like are used to specify that there is a feature, a number, a step, an operation, an element, a component or a combination thereof described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

It is to be understood that the components of the embodiments described with reference to the drawings are not limited to the embodiments and may be embodied in other embodiments without departing from the spirit of the invention. It is to be understood that although the description is omitted, multiple embodiments may be implemented again in one integrated embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.

FIG. 2 is a schematic diagram illustrating a configuration of a system-on-chip according to an embodiment of the present invention. FIG. 3 is a diagram schematically illustrating a configuration of a Tiny processor according to an embodiment of the present invention. FIG. 4 is a schematic diagram of a memory map according to an embodiment of the present invention. FIG. 5 is a view illustrating a variety of pipeline processing structures of a Tiny processor according to an embodiment of the present invention.

2, a system-on-a-chip 200 for receiving and processing sensor signals in a sensor device (for example, a thermal image sensor, a terahertz sensor, a camera sensor, etc.) includes a CPU 110, an external memory 130, An internal memory 120 in which program codes for driving the CPU 110 are stored and which is used as a data memory of the CPU 110 among the information (i.e., data, program code, etc.) An external memory 130 for receiving and storing information necessary for driving the system-on-chip 100 from a storage medium (for example, external flash memory), a memory 130 for receiving a sensor signal from a sensor device external to the system- An input unit 140, and a processing unit 210 configured with a plurality of Tiny processors 220 performing an operation specified according to the loaded program code. Although not shown, an external memory controller and an internal memory controller for controlling the operation of each of the internal memory 120 and the external memory 130 and controlling each memory to function in cooperation with other components such as the CPU 110 are further included .

Generally, the sensor signal processing in the system-on-chip 200 is performed by processes such as filtering, extraction, and algorithm-based calculation (for example, multiplication, addition, and shift operations).

The system on chip 100 according to the related art is implemented such that the program code is loaded from the external storage medium into the internal memory 120 or the external memory 130 and then the CPU 110 performs an operation according to the program code .

On the other hand, the system-on-chip 200 according to the present embodiment is loaded with program codes corresponding to processing contents assigned to each Tiny processor 220 provided in the processing unit 210 as described later, Each Tiny processor 220 is configured to perform pipeline processing. Even if the entire program code for driving the system-on-chip 200 is stored in the external memory 130, only the program code for driving the CPU 110 is stored in the internal memory 120, 120 may be replaced by a device having a smaller storage capacity.

The processing unit 210 is provided with a plurality of Tiny processors (TP) 220, which are low-end MCUs. Here, a low-end MCU may be a low-cost MCU product having a limited processing capability so that high-grade processing can not be performed even though it is possible to perform a simple simple operation such as multiplication or addition, or a long- It can mean a product.

Each Tiny processor 220 may include a command memory 310, a processing controller 320, an input buffer 330, a processor 340 and an output buffer 350 as illustrated in FIG.

In the command memory 310, a program code for an operation to be processed by the Tiny processor 220 is stored. The program code stored in the command memory 310 may be program code located at a specific address on the memory map among the program codes stored in the external memory 130. The program code stored in the command memory 310 may be stored in the command memory 310 And can be controlled by the CPU 110. At this time, the program codes stored in the command memory 310 of each Tiny processor 220 may be different depending on which application field the system-on-chip 200 is to process.

FIG. 4 illustrates a memory map including program codes of various application fields stored in an external storage medium. However, the memory map stored in the external memory 130 during the booting process is not necessary for driving the system-on-chip 200 Some of the memory maps may be stored. The memory map stored in the external memory 130 may be different depending on which application field the system-on-chip 200 is designated to function in.

The processing controller 320 stores the program code designated by the control of the CPU 110 in the external memory 130 in the command memory 310 and the processor 340 reads the program code corresponding to the program code stored in the command memory 310 And controls the processing operation to proceed.

For example, the processing controller 320 controls how the processor 340 processes (e.g., 16-bit multiply, add, shift, and so on) the data input to the input buffer 330, 340 are output to the subsequent components (e.g., other Tiny processors or peripherals, etc.) through the output buffer 350.

Whether or not each of the Tyne processor 220 receives data from a component, performs a process on the input data, and outputs the processed result data to a component is determined by a program code stored in the command memory 310 .

Since it is prescribed in advance as a program code which process each tinier processor 220 performs and which component to output the processed result data to, as shown in Figs. 5A and 5B, Various pipeline structures can be formed. The configuration of various types of pipeline structures can be changed using, for example, a MUX pre-installed in the processing unit 210, and the path configuration can be changed by, for example, So that the constituent elements for outputting the resultant data can be made by the specified program code.

At this time, each Tiny processor 220 that performs the pipeline processing may operate by receiving clocks of different frequencies under the control of the clock controller 230 according to the total bandwidth.

Generally, pipeline processing means that one clock is one stage, and the time taken in one stage is determined as the delay of the stage having the maximum delay during each pipeline processing.

Accordingly, when a plurality of Tiny processors 220 perform respective allocated processes, some of the Tiny processors 220 may have a small amount of computation, It may take.

However, since the processing time of each Tiny processor 220 must be set to be the same for pipeline processing, a fast clock frequency is allocated to some Tiny processor 220 and a slow clock frequency is allocated to another Tiny processor 220 It becomes possible.

In this manner, the processing for causing each of the Tiny processors 220 to be assigned an appropriate clock frequency is performed by the clock controller 230, and there is also a feature that the low power system-on-chip 200 can be implemented by this processing. Of course, in the case where a long time is required for a specific operation process, it is of course possible that the corresponding operation process is divided and performed by a plurality of Tiny processors 220.

Also, although the program code is loaded into each of the Tiny processors 220 included in the processing unit 210, all of the program codes may not be limited to performing processing such as an operation.

For example, if the processing unit 210 is provided with five Tiny processors 220, but only the operation of four Tiny processors 220 is required to process the sensor signals, the other Tiny processor 220 Only a process of outputting input data to a subsequent component without calculation may be performed (see TP-8 in FIG. 5 (a)).

Of course, if the other Tiny processor 220 does not need any operation processing, the resultant data processed by the last Tiny processor 220 that has performed the specified processing is transferred to the next predetermined component It is obvious that the output can be directly output.

As described above, the system-on-chip 200 according to the present embodiment pipelines the Tiny processors 220, which are low-level MCUs, to operate in conjunction with each other, and each Tiny processor 220 has a pre- But performs an operation according to the program code stored in the command memory 310 in the external memory 130 by the CPU 110 in the booting process.

Therefore, depending on which program code is stored in each Tiny processor 220, the system-on-chip 200 may perform an MP3 function and an image processing function. When the image processing function is performed, it may be applied to various application fields such as a thermal image processing, an ultrasonic analysis processing, and a terra bit. In this way, each user can configure and modify the memory map in various ways, so that the system-on-chip 200 according to the present embodiment can be utilized in various applications.

As illustrated in FIG. 4, a memory map stored in an external storage medium may store programs for a plurality of application fields. The program codes for the respective application fields may be provided to the respective system-on-chip 200 and may be respectively driven. Alternatively, one system-on-chip 200 may be operated in various application fields.

Therefore, assuming that the system-on-chip 200 according to the present embodiment is implemented as an image signal processor (ISP), the thermal image ISP, Ultrasonic ISP, terabit ISP, and so on. This feature can provide diversity that can be applied to various sensor devices in the field of Internet (IoT, Internet of Thigs).

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. It will be understood that the present invention can be changed.

100, 200: System On Chip (SoC) 110: CPU
120: internal memory 130: external memory
140: Input unit 150: Hardware engine
210: processing unit 220: Tiny processor
310: Command memory 320: Process controller
330: input buffer 340: processor
350: Output buffer

Claims (3)

A system-on-chip which processes and outputs an input sensor signal,
An external memory for receiving and storing a program code for driving a system-on-chip stored in an external storage medium during a booting process; And
A processing unit including a plurality of Tiny processors,
Each Tiny processor loads a program code corresponding to the address indicated by the CPU among the program codes stored in the external memory, processes the sensor signal according to the loaded program code, Outputting a sensor signal processed by a program or a peripheral device,
Wherein the plurality of Tiny processors are each arranged to process the sensor signal input by the loaded program code into a pipeline structure,
Wherein each of the Tiny processors is assigned a clock frequency such that the processing time according to each loaded program code is matched with a clock frequency.
The method according to claim 1,
Wherein each of the plurality of Tiny processors comprises:
A command memory for storing a program code corresponding to the address designated by the CPU;
An input buffer receiving a sensor signal or a sensor signal processed by a preceding Tiny processor in a pipeline structure;
A processor for processing the sensor signal input to the input buffer according to a program code stored in the command memory;
An output buffer for outputting sensor signals processed by the processor to a Tiny processor or a peripheral device that trails in a pipeline structure; And
And a processing controller for controlling the processor to perform processing according to the program code stored in the command memory.
The method according to claim 1,
The external storage medium stores a memory map including program codes to be loaded into each Tiny processor in each of a plurality of application fields. In a booting process, a program code corresponding to an application field allocated to the system- Gt; chip. ≪ / RTI >

Images