KR101773192B1 - Liquid Crystal Display Device - Google Patents

Abstract

Embodiments of the present invention provide a method of driving a plasma display panel, comprising: driving units driven by a clock frequency source; And a liquid crystal panel module driven by the driving units to display an image.

Description

[0001] The present invention relates to a liquid crystal display device,

An embodiment of the present invention relates to a liquid crystal display device.

As the information technology is developed, the market of display devices, which is a connection medium between users and information, is getting larger. Accordingly, a flat panel display (FPD) such as a liquid crystal display (LCD), an organic light emitting diode (OLED), and a plasma display panel (PDP) Usage is increasing. Among them, liquid crystal display devices capable of realizing high resolution and capable of not only miniaturization but also enlargement are widely used.

In a liquid crystal display device, a data driver and a gate driver are driven by a data signal and a control signal supplied from a timing controller. When a data signal, a gate signal, and the like are supplied from the data driver and the gate driver to the liquid crystal panel, an electric field corresponding to the difference from the common voltage is formed.

The liquid crystal panel includes a transistor substrate on which a transistor, a storage capacitor, a pixel electrode, and the like are formed, and a liquid crystal layer disposed between the color filter substrate and the color filter substrate on which the color filter and the black matrix are formed. The liquid crystal panel displays an image in such a manner as to adjust the direction of the arrangement of the electric field liquid crystal layer formed by the pixel electrode and the common electrode formed on the transistor substrate or the color filter substrate to cause a change in the amount of light provided from the backlight unit.

In order to perform such a driving, a liquid crystal display device includes driving units formed of a plurality of integrated circuits (ICs). Here, each IC includes an internal oscillator that generates a clock frequency for its own purpose. The driving unit including the internal frequency oscillator may include a power source driving unit, an LED driving unit, and a timing control unit.

If a structure including an internal frequency oscillator is used for each of the driving units as in the conventional liquid crystal display device, unstable driving may be generated due to occurrence of output timing deviation between the driving units due to the use of a plurality of frequency oscillators, Which may lead to an increase in cost and an increase in cost.

According to an embodiment of the present invention for solving the problems of the background art described above, the frequency oscillators included in the driving units are integrated into one, and the use of a single clock frequency prevents or improves the output timing deviation between the driving units, And to provide a liquid crystal display device capable of reducing power consumption and cost.

According to an aspect of the present invention, there is provided an apparatus for driving a plasma display panel, comprising: driving units driven by a clock frequency source; And a liquid crystal panel module driven by the driving units to display an image.

The driving units include a frequency oscillator for outputting one clock frequency, a power supply driving unit for dividing and driving one clock frequency outputted from the frequency oscillator, an one-chip driving unit driven by one clock frequency outputted from the frequency oscillator, And an LED driver for dividing and driving one clock frequency output from the oscillator.

The frequency oscillator may be included in the power source driving unit.

The frequency oscillator may be included in the LED driver.

The one-chip driver may include a timing controller and a data driver.

At least one of the power driver and the LED driver may be divided into one clock frequency output from the frequency oscillator by a clock divider using a counter.

The liquid crystal panel module may include a liquid crystal panel driven by a driving signal output from the one-chip driving unit to display an image, and an LED backlight unit for providing light to the liquid crystal panel.

The frequency oscillator can output the clock frequency of the device requiring the highest clock frequency among the driving units.

The embodiment of the present invention can integrate the frequency oscillators included in the driving units and prevent or improve the occurrence of output timing deviation between the driving units by using a single clock frequency to stabilize the driving and reduce power consumption and cost There is an effect of providing a liquid crystal display device.

1 is a block diagram of a liquid crystal display according to an embodiment of the present invention;
2 is a block diagram of a gate driver;
3 is a block diagram of a data driver;
4 is a view illustrating driving units of a liquid crystal display according to a first embodiment of the present invention.
5 is a simulation result of frequency division using a clock frequency outputted from one frequency oscillator.
6 illustrates driving units of a liquid crystal display according to a second embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of a liquid crystal display according to an embodiment of the present invention, FIG. 2 is a block diagram of a gate driver, and FIG. 3 is a block diagram of a data driver.

1 to 3, a liquid crystal display according to an exemplary embodiment of the present invention includes a timing controller T-Con, a power source driver PWR-IC, a data driver SD-IC, a gate driver GD-IC, a liquid crystal panel (PNL), an LED driver (LD-IC), and a backlight unit (BLU).

The timing controller T-Con receives a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal Data Enable, and a data signal DATA from the outside. The timing controller T-Con uses a timing signal such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync and a data enable signal DE to drive the data driver SD-IC and the gate driver GD-IC). The timing control unit T-Con can count the data enable signal DE in one horizontal period to determine the frame period, so that the externally supplied vertical synchronizing signal Vsync and the horizontal synchronizing signal Hsync can be omitted have. Typical control signals generated by the timing controller T-Con include control signals for controlling the operation timings of the gate timing control signal GDC and the data driver SD-IC for controlling the operation timing of the gate driver GD- And a data timing control signal DDC for controlling the timing. The gate timing control signal GDC includes a gate start pulse GSP, a gate shift clock GSC and a gate output enable signal GOE. The gate start pulse GSP is supplied to a gate drive IC (Integrated Circuit) generating the first gate signal. The gate shift clock GSC is a clock signal commonly input to the gate drive ICs, and is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output of the gate drive ICs. The data timing control signal DDC includes source start pulses (Source, Start Pulse, SSP), Source Sampling Clock (SSC), Source Output Enable (SOE), and the like. The source start pulse SSP controls the data sampling start timing of the data driver SD-IC. The source sampling clock SSC is a clock signal for controlling the sampling operation of data in the data driver (SD-IC) based on the rising or falling edge. The source output enable signal SOE controls the output of the data driver SD-IC. On the other hand, the source start pulse SSP supplied to the data driver SD-IC may be omitted depending on the data transfer method.

The power supply unit PWR-IC adjusts a voltage supplied from the system board to generate a driving voltage and supplies the generated driving voltage to the timing controller T-Con, the data driver SD-IC, the gate driver SDRV, Panel (PNL). The power driver PWR-IC generates the common voltage Vcom as well as the gamma voltages GMA0 to GMAn and supplies it to the data driver SD-IC and the liquid crystal panel PNL.

The liquid crystal panel (PNL) includes subpixels arranged in a matrix including a liquid crystal layer positioned between a transistor substrate (hereinafter abbreviated as TFT substrate) and a color filter substrate. A data line, a gate line, a TFT, a storage capacitor and the like are formed on the TFT substrate, and a black matrix, a color filter and the like are formed on the color filter substrate. One subpixel SP is defined by the intersecting data line DL1 and the gate line SL1. The subpixel SP includes a TFT driven by a gate signal supplied through a gate line SL1, a storage capacitor Cst for storing a data signal supplied through the data line DL1 as a data voltage, a storage capacitor Cst And a liquid crystal cell Clc driven by the data voltage stored in the liquid crystal cell Clc. The liquid crystal cell Clc is driven by the data voltage supplied to the pixel electrode 1 and the common voltage VCOM supplied to the common electrode 2. [ The common electrode is formed on a color filter substrate in a vertical field driving method such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode, and a horizontal electric field such as IPS (In Plane Switching) mode and FFS (Fringe Field Switching) Is formed on the TFT substrate together with the pixel electrode in the driving method. A polarizing plate is attached to the TFT substrate of the liquid crystal panel (PNL) and the color filter substrate, and an alignment film for setting a pre-tilt angle of the liquid crystal is formed. The liquid crystal mode of the liquid crystal panel PNL can be implemented in any liquid crystal mode as well as the TN mode, VA mode, IPS mode, and FFS mode described above.

The backlight unit (BLU) provides light to the liquid crystal panel (PNL). The backlight unit BLU includes a light source circuit portion including a direct current power source, LEDs, transistors and a drive control unit, and an optical mechanism including a cover bottom, a light guide plate, and an optical sheet. The backlight unit (BLU) may be variously configured as an edge type, a dual type, a direct type, and the like. In the edge type, the LEDs are arranged in a line (or string) shape on one side of the liquid crystal panel PNL. In the dual type, LEDs are arranged in a line (or string) form on both sides of a liquid crystal panel (PNL). In the direct type, LEDs are arranged in the form of a block or a matrix in the lower part of the liquid crystal panel (PNL).

The LED driving unit (LD-IC) drives the LEDs included in the backlight unit (BLU). The LED driver (LD-IC) can drive the LEDs included in the backlight unit (BLU) using a pulse width signal (PWM), but is not limited thereto.

In response to the gate timing control signal GDC supplied from the timing control unit T-Con, the gate driving unit GD-IC supplies a gate driving voltage Vdd capable of operating the transistors of the subpixels SP included in the liquid crystal panel PNL. The gate signal is sequentially generated while the level of the signal is shifted by the swing width of the gate signal. The gate driver GD-IC supplies the gate signal generated through the gate lines SL1 to SLm to the subpixels SP included in the liquid crystal panel PNL. The gate driver (GD-IC) is composed of gate drive ICs as shown in FIG. Each of the gate drive ICs includes a shift register 61, a level shifter 63, a plurality of AND gates 62 connected between the shift register 61 and the level shifter 63, And an inverter 64 for inverting the gate output enable signal GOE. The shift register 61 shifts the gate start pulse GSP sequentially in accordance with the gate shift clock GSC using a plurality of D flip-flops depending thereon. The AND gates 62 logically multiply the output signal of the shift register 61 and the inverted signal of the gate output enable signal GOE to generate an output. The inverter 64 inverts the gate output enable signal GOE and supplies it to the AND gates 62. The level shifter 63 shifts the output voltage swing width of the AND gate 62 to the swing width of the gate voltage at which the transistors included in the liquid crystal panel PNL can operate. The gate signal output from the level shifter 63 is sequentially supplied to the gate lines SL1 to SLm.

The data driver SD-IC samples and latches the data signal DATA supplied from the timing controller T-Con in response to the data timing control signal DDC supplied from the timing controller T-Con, System data. The data driver (SD-IC) converts the data signal (DATA) to a gamma reference voltage when converting into data of a parallel data system. The data driver SD-IC supplies the data signal DATA, which has been converted through the data lines DL1 to DLn, to the sub-pixels SP included in the liquid crystal panel PNL. 3, the data driver SD-IC includes a shift register 51, a data register 52, a first latch 53, a second latch 54, a converter 55, an output circuit 56) and the like. The shift register 51 shifts the source sampling clock SSC supplied from the timing controller T-Con. The shift register 51 transfers the carry signal CAR to the shift register of the next source drive IC in the neighboring stage. The data register 52 temporarily stores the data signal DATA supplied from the timing controller T-Con and supplies it to the first latch 53. The first latch 53 samples and latches the data signal DATA serially input according to the clocks sequentially supplied from the shift register 51, and then simultaneously outputs the latched data. The second latch 54 latches the data supplied from the first latch 53 and then latches the latched data in synchronization with the second latch 54 of the other source drive ICs in response to the source output enable signal SOE Simultaneously output. The conversion unit 55 converts the digital data signal DATA supplied from the second latch 54 in response to the polarity control signal POL and the horizontal output inversion signal HINV to a positive gamma voltage or a negative gamma voltage And converts it into an analog type data voltage. The output section 56 includes a buffer for minimizing signal attenuation of the data voltage output to the data lines D1 to Dm. The charge sharing section 57 supplies the charge sharing voltage or the common voltage Vcom to the data lines DL1 to DLn during the charge sharing period according to the source output enable signal SOE.

In the liquid crystal display according to the embodiment of the present invention described above, the driving units (PWR-IC, T-Con, SD-IC, LD-IC) driving the liquid crystal panel PNL are driven by one clock frequency source do.

Hereinafter, a liquid crystal display device according to an embodiment of the present invention will be described in more detail.

≪ Embodiment 1 >

FIG. 4 is a view illustrating driving units of a liquid crystal display according to a first embodiment of the present invention, and FIG. 5 is a result of frequency division simulation using a clock frequency output from one frequency oscillator.

As shown in FIG. 4, the power source driver PWR-IC includes an internal frequency oscillator (IOSC), a first divider DIV1, and a power control logic PCL. The internal frequency oscillator IOSC included in the power supply driving unit PWR-IC outputs one clock frequency clk. The first divider DIV1 divides the clock frequency clk output from the internal frequency oscillator IOSC and supplies the divided clock frequency to the power control logic PCL. The first divider DIV1 of the power drive unit PWR-IC may use a clock divider using a counter to divide the clock frequency clk output from the internal frequency oscillator IOSC, but is not limited thereto.

The internal frequency oscillator IOSC of the power drive unit PWR-IC is set to the clock frequency of the driving unit that requires the highest clock frequency among the driving units PWR-IC, T-Con, SD-IC and LD- do.

The clock frequency clk output from the internal frequency oscillator IOSC of the power source driver PWR-IC is supplied to the LED driver (LD-IC) as well as the one-chip driver T-SD-IC. The one-chip driver T-SD-IC and the LED driver LD-IC are driven by the clock frequency clk output from the internal frequency oscillator IOSC of the power driver PWR-IC. Here, the one-chip driver (T-SD-IC) is an example in which the timing controller (T-Con) and the data driver (SD-IC) shown in FIG. 1 are formed as a single chip.

The LED driver (LD-IC) requires a clock frequency lower than the clock frequency clk output from the internal frequency oscillator (IOSC) of the power driver (PWR-IC). Accordingly, the LED driving unit LD-IC divides the clock frequency clk outputted from the internal frequency oscillator IOSC of the power source driving unit PWR-IC using the second divider DIV2 and outputs the divided clock frequency LED control logic (LDCL). The second divider DIV2 of the LED driving unit LD-IC may use a clock divider using a counter to divide the clock frequency clk output from the internal frequency oscillator IOSC, but is not limited thereto.

As described above, the first embodiment of the present invention generates one high clock frequency clk using the internal frequency oscillator IOSC of the power source driving unit PWR-IC and generates the high clock frequency clk, Can be used in a clock frequency band suitable for each driving unit.

In an example of the embodiment, when the timing controller T-Con requests a clock frequency of 20 MHz, the LED driver LD-IC requests a clock frequency of 1 MHz, and the power driver PWR- The simulation of dispensing for the devices requiring the < Desc / Clms Page number 7 >

In the simulation of FIG. 5, since the timing control section (T-Con) among the driving sections (PWR-IC, T-Con, SD-IC and LD- The frequency oscillator (IOSC) is set to generate a clock frequency of 20MHz. A first divider DIV1 is formed in the power supply driving unit PWR-IC so that a clock frequency of 20 MHz can be divided into 1.2 MHz. A clock of 20 MHz is provided in the LED driving unit (LD-IC) A second frequency divider DIV2 is formed so that the frequency can be divided by 1 MHz.

As a result, the 20 MHz clock frequency (refer to the top timing diagram) output from the internal frequency oscillator (IOSC) of the power source driver (PWR-IC) is 1 MHz (see the timing chart of the interruption) and 1.2 MHz ) Clock frequency.

According to the simulation of Fig. 5, the liquid crystal display device of the first embodiment divides one high clock frequency source in accordance with the purpose of the plurality of drivers (PWR-IC, T-Con, SD-IC and LD-IC) It was confirmed that it can be used.

≪ Embodiment 2 >

6 is a view illustrating driving units of a liquid crystal display according to a second embodiment of the present invention.

As shown in FIG. 6, the LED driver (LD-IC) includes an internal frequency oscillator (IOSC), a second frequency divider (DIV2), and an LED control logic (LDCL). The internal frequency oscillator IOSC included in the LED driving unit (LD-IC) outputs one clock frequency clk. The second divider DIV2 divides the clock frequency clk output from the internal frequency oscillator IOSC and supplies the divided clock frequency to the LED control logic LDCL. The second divider DIV2 of the LED driving unit LD-IC may use a clock divider using a counter to divide the clock frequency clk output from the internal frequency oscillator IOSC, but is not limited thereto.

The internal frequency oscillator (IOSC) of the LED driving unit (LD-IC) is set to the clock frequency of the driving unit which requires the highest clock frequency among the driving units (PWR-IC, T-Con, SD-IC and LD- do.

The clock frequency clk output from the internal frequency oscillator IOSC of the LED driving unit LD-IC is supplied to the power source driving unit PWR-IC as well as the one-chip driving unit T-SD-IC. The one-chip driver T-SD-IC and the power driver PWR-IC are driven by the clock frequency clk output from the internal frequency oscillator IOSC of the LED driver LD-IC. Here, the one-chip driver (T-SD-IC) is an example in which the timing controller (T-Con) and the data driver (SD-IC) shown in FIG. 1 are formed as a single chip.

The power driver (PWR-IC) requires a clock frequency lower than the clock frequency clk output from the internal frequency oscillator (IOSC) of the LED driver (LD-IC). Accordingly, the power source driver PWR-IC divides the clock frequency clk output from the internal frequency oscillator IOSC of the LED driver LD-IC using the first divider DIV1, Power supply control logic (PCL). The first divider DIV1 of the power source driver PWR-IC uses a clock divider using a counter to divide the clock frequency clk output from the internal frequency oscillator IOSC of the LED driver LD-IC But is not limited thereto.

As described above, the second embodiment of the present invention uses the internal frequency oscillator (IOSC) of the LED driver (LD-IC) to generate one high clock frequency (clk) and generates the generated high clock frequency (clk) Can be used in a clock frequency band suitable for each driving unit.

As in the first and second embodiments, when a single high clock frequency source is used in accordance with the purpose and used, it is possible to prevent or improve the occurrence of output timing deviation between the driving units compared with the case where the driving units having different frequency oscillators are used . In addition, since the occurrence of output timing deviation can be prevented or improved, the driving can be stabilized, and only one frequency oscillator can be provided. Thus, power consumption and cost can be reduced considerably.

As described above, the embodiment of the present invention integrates the frequency oscillators included in the driving units and prevents or improves the output timing deviation between the driving units by using a single clock frequency, thereby stabilizing the driving and reducing power consumption and cost There is an effect of providing a liquid crystal display device.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the following claims rather than the detailed description. Also, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

T-Con: Timing control part PWR-IC: Power supply part
SD-IC: Data driver GD-IC: Gate driver
PNL: liquid crystal panel LD-IC: LED driver
BLU: backlight unit IOSC: frequency oscillator
DIV1: first divider DIV2: second divider

Claims (8)

Drivers driven by one clock frequency source; And
And a liquid crystal panel module driven by the driving units to display an image,
The driving units include:
A frequency oscillator for outputting one clock frequency,
A power source driving unit for dividing and driving one clock frequency outputted from the frequency oscillator;
A one-chip driver driven by one clock frequency output from the frequency oscillator;
And an LED driving unit for dividing and driving one clock frequency outputted from the frequency oscillator. delete The method according to claim 1,
The frequency oscillator includes:
And the power supply driving unit. The method according to claim 1,
The frequency oscillator includes:
And the LED driving unit. The method according to claim 1,
The one-
A liquid crystal display comprising a timing controller and a data driver. The method according to claim 1,
Wherein at least one of the power source driver and the LED driver includes:
Wherein one clock frequency output from the frequency oscillator is divided by a clock divider using a counter. The method according to claim 1,
In the liquid crystal panel module,
A liquid crystal panel driven by the driving signal output from the one-chip driving unit to display an image;
And an LED backlight unit for providing light to the liquid crystal panel. The method according to claim 1,
The frequency oscillator includes:
And outputs a clock frequency of a device requesting the highest clock frequency among the driving units.

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