KR101761948B1

KR101761948B1 - Transistor switch and rf switch

Info

Publication number: KR101761948B1
Application number: KR1020120157889A
Authority: KR
Inventors: 박상욱; 박성환
Original assignee: 삼성전기주식회사
Priority date: 2012-12-31
Filing date: 2012-12-31
Publication date: 2017-07-26
Also published as: KR20140087510A

Abstract

The present invention relates to a transistor switch and an RF switch. According to one embodiment of the present invention, an SOI transistor; And an auxiliary transistor having one end connected to the gate of the SOI transistor and the other end connected to the body of the SOI transistor to operate complementarily with the SOI transistor. An RF switch is also proposed.

Description

[0001] TRANSISTOR SWITCH AND RF SWITCH [

The present invention relates to a transistor switch and an RF switch. And more particularly to an improved transistor switch and an RF switch with an SOI transistor.

With the development of wireless communication technology, frequency bands to be supported by one mobile device are increasing. In accordance with these trends, the importance of RF front-end for processing signals in various frequency bands is emphasized. In particular, the RF switch is located on an important signal path between the antenna and the RF chip. In this case, the insertion loss of the switch must be excellent in order to reduce the signal loss, and excellent linearity is required in order to minimize the interference between the various frequency bands.

RF switches such as SPDTs are being implemented not only as semiconductor devices with RF performance like GaAs but also as field effect transistors (FET) using SOI process due to the development of silicon process.

A conventional RF switch is schematically shown in Fig. 3, when a positive voltage is applied to the power source V1, the first SOI transistor switch 10a connected in series to the antenna ANT and the first RF stage RF1 is turned on. At this time, 0 or negative voltage is applied to the power source V2 And the third SOI transistor switch 10c connected with shunt is turned off. At this time, the path from the antenna ANT to the first RF stage RF1 is turned ON. Conversely, when a positive or negative voltage is applied to the power source V1 and a positive voltage of at least the threshold voltage Vth is applied to the power source V2, the first SOI transistor switch 10a is turned off and the third SOI transistor switch 10c is turned- And the path from the antenna ANT to the first RF stage RF1 is turned off. At this time, the bodies of the first to fourth SOI transistors 10a to 10d are normally grounded.

In the case of the NMOSFET shown in FIG. 3, when the body is floating or connected to the ground and the switch is left in the off state for a long time, a certain bias condition, for example, when the source and gate become negative voltages, A hole of positive charge may accumulate below the layer. This results in several unwanted negative characteristics. For example, the equivalent capacitance C _off in the switch-off state is increased, and the characteristics of the linearity item such as the harmonic characteristic and the intermodulation characteristic are deteriorated.

On the other hand, in Japanese Patent Application Laid-Open Publication No. 10-2000-0035019, the charge of the body is connected to ground by using a transistor, but in this case also, a specific bias condition, for example, a gate bias is a negative voltage The discharge effect of the charge accumulated in the body drops.

Korean Patent Publication No. 10-2003-0095402 (published on December 18, 2003) Korean Patent Publication No. 10-2000-0035019 (published on June 26, 2000)

In order to solve the above problem, a technique of improving the linearity by connecting the auxiliary transistor to the body and gate of the SOI transistor to remove the charges accumulated in the bipolar transistor is proposed.

In order to solve the above-mentioned problems, according to a first embodiment of the present invention, there is provided a semiconductor device comprising: an SOI transistor; And an auxiliary transistor having one end connected to the gate of the SOI transistor and the other end connected to the body of the SOI transistor to operate complementarily with the SOI transistor.

At this time, in one example, the auxiliary transistor may make the gate and the body of the SOI transistor equal in the OFF operation of the SOI transistor to remove the charge charged in the body of the SOI transistor which is turned off.

Further, in one example, the SOI transistor is an SOI NMOS transistor, and the auxiliary transistor is an NMOS transistor and operates in accordance with a power supply signal that is complementary to the gate power supply signal of the SOI NOMS transistor.

Next, in order to solve the above-mentioned problem, according to a second embodiment of the present invention, a first SOI transistor and a first SOI transistor, which are disposed between the antenna and the first RF stage, A first transistor switch including a first auxiliary transistor connected to the body of the transistor and operated in complementary relation with the first SOI transistor; A second SOI transistor disposed between the antenna and the second RF stage, and a second SOI transistor having one end connected to the gate of the second SOI transistor and the other end connected to the body of the second SOI transistor, And a second transistor switch including an auxiliary transistor and operating in a complementary manner with the first transistor switch.

In this case, in one example, a third SOI transistor having one end connected to a node between the first transistor switch and the first RF stage and grounded at the other end, and a third end connected to the gate of the third SOI transistor, A first shunt switch including a third auxiliary transistor connected to the other end of the body and operated in complementary relation with a third SOI transistor, the first shunt switch being complementary to the first transistor switch; And a fourth SOI transistor having one end connected to the node between the second transistor switch and the second RF stage and grounded at the other end, and the other end connected to the gate of the fourth SOI transistor and the other end connected to the body of the fourth SOI transistor And a second shunt switch including a fourth auxiliary transistor that operates complementarily with the fourth SOI transistor and operates in a complementary manner with the second transistor switch.

Also, according to one example, each of the auxiliary transistors may be configured to equalize the gate and body of each SOI transistor connected to the gate and body of each of the auxiliary transistors, thereby removing the charges charged to the body of each SOI transistor turned off can do.

At this time, in another example, each of the SOI transistors is an SOI NMOS transistor, each of the auxiliary transistors is an NMOS transistor, and the gate and the body are connected to the respective auxiliary transistors, .

According to the embodiment of the present invention, the auxiliary transistor can be connected to the body and the gate of the SOI transistor to effectively remove the charge accumulated in the via, thereby improving the linearity of the switch.

It is apparent that various effects not directly referred to in accordance with various embodiments of the present invention can be derived by those of ordinary skill in the art from the various configurations according to the embodiments of the present invention.

1 is a circuit diagram schematically illustrating a transistor switch according to one embodiment of the present invention.
2 is a circuit diagram schematically showing an RF switch according to one embodiment of the present invention.
3 is a circuit diagram schematically showing a conventional RF switch.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing the configuration of a first embodiment of the present invention; Fig. In the description, the same reference numerals denote the same components, and a detailed description may be omitted for the sake of understanding of the present invention to those skilled in the art.

As used herein, unless an element is referred to as being 'direct' in connection, combination, or placement with other elements, it is to be understood that not only are there forms of being 'directly connected, They may also be present in the form of being connected, bonded or disposed.

It should be noted that, even though a singular expression is described in this specification, it can be used as a concept representing the entire constitution unless it is contrary to, or obviously different from, or inconsistent with the concept of the invention. It is to be understood that the phrases "including", "having", "having", "comprising", etc. in this specification are intended to be additionally or interchangeable with one or more other elements or combinations thereof.

First, a transistor switch according to a first embodiment of the present invention will be described in detail with reference to the drawings. Here, reference numerals not shown in the drawings to be referred to may be reference numerals in other drawings showing the same configuration.

1 is a circuit diagram schematically illustrating a transistor switch according to one embodiment of the present invention.

Referring to FIG. 1, a transistor switch according to one example comprises an SOI transistor 10 and an auxiliary transistor 30.

The SOI transistor 10 refers to a silicon-on-insulator field effect transistor. The SOI transistor 10 forms a field effect transistor structure on, for example, silicon-insulator-silicon.

For example, the SOI transistor 10 may be an SOI NMOS transistor. In case of SOI NMOS transistor, when the body is processed in a floating state or connected to ground (GND) for a long period of time, a certain bias condition, for example, when source and gate become negative voltage, Holes of the positive charge are accumulated in the holes. This causes unwanted negative characteristics. For example, when the off-state equivalent capacitance C _off is increased and used, for example, as an RF switch, the linearity may deteriorate, such as a harmonic characteristic or an intermodulation characteristic.

Therefore, it is necessary to remove the charge accumulated in the off-body of the SOI transistor 10.

At this time, one end of the auxiliary transistor 30 is connected to the gate of the SOI transistor 10, and the other end is connected to the body of the SOI transistor 10. For example, the drain of the auxiliary transistor 30 may be connected to the gate of the SOI transistor 10, and the source of the auxiliary transistor 30 may be connected to the body of the SOI transistor 10. At this time, the auxiliary transistor 30 operates in a complementary manner with the SOI transistor 10.

At this time, the auxiliary transistor 30 operates in a complementary manner with the SOI transistor 10, one end of the auxiliary transistor 30 is connected to the gate of the SOI transistor 10, and the other end is connected to the body of the SOI transistor 10 , The auxiliary transistor 30 is turned on when the SOI transistor 10 is turned off, and the gate and the body of the SOI transistor 10 are made to be equipotential. As a result, the charges accumulated in the body of the SOI transistor 10 are removed and no charge is accumulated in the SOI transistor 10.

For example, the auxiliary transistor 30 may be an NMOS transistor. At this time, the NMOS transistor operates according to, for example, a power supply signal complementary to the gate power supply signal of the SOI NOMS transistor.

Next, an RF switch according to a second embodiment of the present invention will be described in detail with reference to the drawings. At this time, the transistor switch according to the first embodiment described above and FIG. 1 will be referred to, and thus redundant explanations can be omitted.

2 is a circuit diagram schematically showing an RF switch according to one example of the present invention.

Referring to FIG. 2, an RF switch according to one example includes a first transistor switch and a second transistor switch that is complementary to the first transistor switch. For example, the RF switch is a single pole drop throw (SPDT) switch.

At this time, the first transistor switch is connected at one end to the gates of the first SOI transistor 10a and the first SOI transistor 10a disposed between the antenna and the first RF stage RF1, And a first auxiliary transistor 30a whose other end is connected to the body. At this time, the first auxiliary transistor 30a operates in a complementary manner with the first SOI transistor 10a. That is, the first auxiliary transistor 30a is turned on when the first SOI transistor 10a is turned off. For example, the first RF stage RF1 may be a transmitting stage and the second RF stage RF2 may be a receiving single stage.

At this time, the first auxiliary transistor 30a may make the gate and the body of the first SOI transistor 10a equipotential in the OFF operation of the first SOI transistor 10a. Thus, the charges charged in the body of the first SOI transistor 10a turned off can be removed.

The second transistor switch has one end connected to the gate of the second SOI transistor 10b and the second SOI transistor 10b disposed between the antenna and the second RF stage RF2, And a second auxiliary transistor 30b whose other end is connected to the body. At this time, the second auxiliary transistor 30b operates in a complementary manner with the second SOI transistor 10b. Further, the second transistor switch operates complementarily with the first transistor switch.

The first transistor switch and the second transistor switch operate in a complementary manner so that the second auxiliary transistor 30b and the first SOI transistor 10a are turned off while the second SOI transistor 10b is turned on, 30a are turned on. Accordingly, a transmission path is formed between the antenna and the second RF stage RF2, and the path between the antenna and the first RF stage RF1 is cut off. Conversely, the first auxiliary transistor 30a and the second SOI transistor 10b are turned off during the ON operation of the first SOI transistor 10a and the second auxiliary transistor 30b, so that the impedance between the antenna and the first RF stage RF1 And the path between the antenna and the second RF stage RF2 is cut off.

At this time, the second auxiliary transistor 30b can make the gate and the body of the second SOI transistor 10b equal to each other in the OFF operation of the second SOI transistor 10b, ) Can be removed.

Further, with reference to Fig. 2, further discussion will be given. In one example, the RF switch may further include a first shunt switch and a second shunt switch. The first and second shunt switches are intended to improve the isolation characteristics of the RF switch.

The first shunt switch includes a third SOI transistor 10c and a third auxiliary transistor 30c. At this time, the first shunt switch operates complementarily with the first transistor switch. One end of the third SOI transistor 10c is connected to the node between the first transistor switch and the first RF stage RF1, specifically between the first SOI transistor 10a and the first RF stage RF1. The other end of the third SOI transistor 10c is grounded. On the other hand, one end of the third auxiliary transistor 30c is connected to the gate of the third SOI transistor 10c and the other end is connected to the body of the third SOI transistor 10c. At this time, the third auxiliary transistor 30c operates in a complementary manner with the third SOI transistor 10c.

At this time, the third auxiliary transistor 30c can make the gate and the body of the third SOI transistor 10c equal in the OFF operation of the third SOI transistor 10c, and accordingly, the third SOI transistor 10c ) Can be removed.

Next, the second shunt switch includes a fourth SOI transistor 10d and a fourth auxiliary transistor 30d. At this time, the second shunt switch operates in a complementary manner with the second transistor switch. One end of the fourth SOI transistor 10d is connected to a node between the second transistor switch and the second RF stage RF2, specifically between the second SOI transistor 10b and the second RF stage RF2. The other end of the fourth SOI transistor 10d is grounded. On the other hand, one end of the fourth auxiliary transistor 30d is connected to the gate of the fourth SOI transistor 10d and the other end is connected to the body of the fourth SOI transistor 10d. At this time, the fourth auxiliary transistor 30d operates in a complementary manner with the fourth SOI transistor 10d.

The first shunt switch operates complementarily with the first transistor switch, and the second shunt switch operates complementarily with the second transistor switch, so that the isolation characteristics are improved. That is, the first shunt switch, specifically the third SOI transistor 10c, is turned off during the ON operation of the first transistor switch, specifically the first SOI transistor 10a, A transmission path is formed. At this time, the second transistor switch and the second SOI transistor 10b are turned off, and the second shunt switch, specifically, the fourth SOI transistor 10d is turned on, and the path between the antenna and the first RF stage RF1 Even if a part of the second transistor switch in which the flowing high frequency signal is turned off passes through the ground by the second shunt switch, the isolation characteristic is improved. The opposite can be understood in the same way.

The fourth auxiliary transistor 30d operates in a complementary manner to the fourth SOI transistor 10d so that the fourth auxiliary transistor 30d is turned off when the fourth SOI transistor 10d is turned off, The gate and the body of the fourth SOI transistor 10d can be made equipotential, so that the charges charged in the body of the turned off fourth SOI transistor 10d can be removed.

For example, in one example, the first to fourth SOI transistors 10d may be SOI NMOS transistors. Also, the first to fourth auxiliary transistors 30d may be NMOS transistors. At this time, each of the first to fourth auxiliary transistors 30d is turned on in response to a power supply signal complementary to the gate power supply signal of each SOI transistor 10 connected to the gate and the body of each of the first to fourth auxiliary transistors 30d . For example, in the first transistor switch, when the first SOI transistor 10a operates in accordance with the gate power supply signal V1, the first auxiliary transistor 30a operates in accordance with the power supply signal V2, which is complementary to the power supply signal V1. 2, for example, the power supply signal V1 is a high signal and the power supply signal V2 is a low signal.

The foregoing embodiments and accompanying drawings are not intended to limit the scope of the present invention but to illustrate the present invention in order to facilitate understanding of the present invention by those skilled in the art. Embodiments in accordance with various combinations of the above-described configurations can also be implemented by those skilled in the art from the foregoing detailed description. Accordingly, various embodiments of the present invention may be embodied in various forms without departing from the essential characteristics thereof, and the scope of the present invention should be construed in accordance with the invention as set forth in the appended claims. Alternatives, and equivalents by those skilled in the art.

10: SOI transistor 10a: first SOI transistor
10b: second SOI transistor 10c: third SOI transistor
10d: fourth SOI transistor 30: auxiliary transistor
30a: first auxiliary transistor 30b: second auxiliary transistor
30c: third auxiliary transistor 30d: fourth auxiliary transistor

Claims

An SOI transistor disposed between the antenna and the RF stage and operated as a switch; And
The other end of the SOI transistor is connected to the gate of the SOI transistor and the other end is connected to the body of the SOI transistor so that the gate and the body of the SOI transistor are turned on when the SOI transistor is turned off, An auxiliary transistor for removing charges charged in the auxiliary transistor;
/ RTI >

delete

The method according to claim 1,
The SOI transistor is an SOI NMOS transistor,
Wherein the auxiliary transistor is an NMOS transistor and operates according to a power supply signal that is complementary to a gate power supply signal of the SOI NMOS transistor.

A first SOI transistor disposed between the antenna and the first RF stage and a first end connected to a gate of the first SOI transistor and having a second end connected to a body of the first SOI transistor to be complementary to the first SOI transistor A first transistor switch including a first auxiliary transistor; And
A second SOI transistor disposed between the antenna and the second RF stage and one end connected to the gate of the second SOI transistor and the other end connected to the body of the second SOI transistor to perform a complementary operation with the second SOI transistor And a second transistor switch including a second auxiliary transistor, the second transistor switch being complementary to the first transistor switch.

The method of claim 4,
A third SOI transistor having one end connected to the node between the first transistor switch and the first RF stage and grounded at the other end, and a third end connected to the gate of the third SOI transistor, A first shunt switch including a third auxiliary transistor connected to the third SOI transistor and operating in a complementary manner with the third SOI transistor, the first shunt switch being complementary to the first transistor switch; And
A fourth SOI transistor having one end connected to a node between the second transistor switch and the second RF stage and grounded at the other end, and a second end connected to the gate of the fourth SOI transistor, And a fourth shunt switch coupled to the fourth shunt resistor and operative to complement the fourth SOI transistor, the second shunt switch being complementary to the second transistor switch.

The method according to claim 4 or 5,
Each of the auxiliary transistors may be configured to equalize the gate and the body when each SOI transistor connected to the gate and the body is turned off in each of the auxiliary transistors to remove charges charged in the body of each SOI transistor that is turned off RF switch.

The method of claim 6,
Each of the SOI transistors is an SOI NMOS transistor,
Wherein each of the auxiliary transistors is an NMOS transistor and operates in accordance with a power supply signal that is complementary to a gate power supply signal of each SOI transistor whose gate and body are connected to each of the auxiliary transistors.