KR101690053B1 - Semiconductor wafer membrane having multiple hardness and semiconductor wafer polishing apparatus using the membrane - Google Patents

Semiconductor wafer membrane having multiple hardness and semiconductor wafer polishing apparatus using the membrane Download PDF

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Publication number
KR101690053B1
KR101690053B1 KR1020150150612A KR20150150612A KR101690053B1 KR 101690053 B1 KR101690053 B1 KR 101690053B1 KR 1020150150612 A KR1020150150612 A KR 1020150150612A KR 20150150612 A KR20150150612 A KR 20150150612A KR 101690053 B1 KR101690053 B1 KR 101690053B1
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South Korea
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semiconductor wafer
polishing
hardness
bottom portion
thin film
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KR1020150150612A
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Korean (ko)
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정진관
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주식회사 엠오에스
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/11—Lapping tools
    • B24B37/20—Lapping pads for working plane surfaces
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/27—Work carriers
    • B24B37/30—Work carriers for single side lapping of plane surfaces
    • B24B37/32—Retaining rings
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09D—COATING COMPOSITIONS, e.g. PAINTS, VARNISHES OR LACQUERS; FILLING PASTES; CHEMICAL PAINT OR INK REMOVERS; INKS; CORRECTING FLUIDS; WOODSTAINS; PASTES OR SOLIDS FOR COLOURING OR PRINTING; USE OF MATERIALS THEREFOR
    • C09D165/00—Coating compositions based on macromolecular compounds obtained by reactions forming a carbon-to-carbon link in the main chain; Coating compositions based on derivatives of such polymers
    • C09D165/04—Polyxylylenes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/203—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy using physical deposition, e.g. vacuum deposition, sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67092—Apparatus for mechanical treatment

Abstract

The present invention relates to a thin film for polishing a semiconductor wafer having multiple hardnesses and a semiconductor wafer polishing apparatus using the thin film, 1. A semiconductor wafer polishing thin film provided on a pressing portion of a semiconductor wafer polishing apparatus for polishing a wafer and contacting an upper portion of the semiconductor wafer comprises a bottom portion formed of a material having a first hardness and formed in a circular plane shape, And an edge portion formed of a material having a second hardness higher than that of the bottom portion and extended and formed to surround the bottom portion.
Accordingly, the thin film for polishing can be formed to have multiple hardness, so that occurrence of slip or release can be minimized.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film for polishing a semiconductor wafer having multiple hardnesses and a semiconductor wafer polishing apparatus using the thin film. 2. Description of the Related Art [0002]

TECHNICAL FIELD [0001] The present invention relates to a thin film for polishing a semiconductor wafer having multiple hardnesses, and a semiconductor wafer polishing apparatus using the same, and more particularly, to a technique for forming a thin film for polishing using a material having different hardnesses for different areas.

The chemical mechanical polishing (CMP) device is a device that removes the height difference between the cell area and the peripheral circuit area due to the unevenness of the wafer surface generated by repeatedly performing masking, etching, and wiring processes during semiconductor device fabrication To improve the surface roughness of the wafer due to contact / wiring film separation for circuit formation and high integration of the device, and the like.

In such a CMP apparatus, the carrier head presses the semiconductor wafer in a state in which the polishing surface of the semiconductor wafer faces the polishing pad before and after the polishing step to perform the polishing process, and at the same time, And then indirectly vacuum-adsorbed and moved to the next step while being gripped. In this case, the performance of the membrane, which is a thin film for polishing, plays a relatively important role.

Korean Patent No. 10-1175472 (registered on Aug. 13, 2012) discloses a method for manufacturing a flexible thin film for a chemical mechanical polishing head and a flexible thin film for a chemical mechanical polishing head manufactured by the method. Coating the polymer coating layer on the flexible thin film substrate, and thermally curing the polymer coating layer.

However, in the case of the conventional thin film for abrasion, there is a great difference in the slip and release occurrence rates of the semiconductor wafer depending on the coating state of the surface layer. Particularly, in the chemical mechanical polishing process, there is a problem that the yield of the semiconductor wafer is reduced due to the slipping of the semiconductor wafer or the release phenomenon upon transfer to the next process. Further, there is a problem that a leakage phenomenon occurs depending on the pressure and hardness applied to the thin film for abrasion.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems occurring in the prior art, and it is an object of the present invention to provide a semiconductor wafer having a multi-hardness capable of minimizing the occurrence of slippage and release, And a semiconductor wafer polishing apparatus using the same.

A semiconductor wafer polishing apparatus according to an embodiment of the present invention is provided with a pressing portion of a semiconductor wafer polishing apparatus for polishing the semiconductor wafer by a polishing pad which is positioned below the semiconductor wafer and fixed by a retainer ring, A thin film for polishing a semiconductor wafer is formed of a material having a first hardness and includes a bottom portion formed in a circular plane shape and a material having a second hardness higher than that of the bottom portion, .

The bottom portion is formed of a material having a hardness of 50 degrees and the edge portion is formed of a material having a hardness of 70 degrees. The bottom portion and the edge portion are integrally formed, and the bottom portion has a hardness of 50 to 55 degrees. The edge portion may exhibit a hardness of 60 to 65 degrees.

The edge portion of the retainer ring may have an inclination angle of 45 degrees with respect to the plane of the bottom portion. The edge portion of the retainer ring may have a width of 1: And may be formed to have a tilt angle of 45 degrees with the pad for use.

The coating layer may be formed by vacuum depositing poly-para-xylylene on the outer surface of the bottom portion. The polyparaxylene may be represented by the following Chemical Formula 1, and may have a vaporization temperature of 180 ° C And is vacuum-deposited to a thickness of 0.3 to 1 占 퐉 on the outer surface of the bottom at a pressure of 10 to 50 mTorr by heating to 670 占 폚 to form the coating layer.

[Chemical Formula 1]

Figure 112015105053419-pat00001

In the general formula (1), n represents a non-zero integer.

According to another aspect of the present invention, there is provided a semiconductor wafer polishing apparatus using a thin film for polishing a semiconductor wafer having a multi-hardness, comprising: a main body; a driving unit connected to the main body for rotation; A bottom portion which is attached to the pressing portion and which is formed on the upper portion of the semiconductor wafer and is formed of a material having a first hardness and which is formed in a circular planar shape and a second hardness portion having a hardness higher than that of the bottom portion And a polishing pad formed on an outer side of the polishing thin film and connected to the main body, the polishing pad being positioned at a lower portion of the semiconductor wafer, And an edge portion of the retainer ring is formed inwardly of the retainer ring so as to be inclined at a predetermined angle with the polishing pad .

Accordingly, the thin film for polishing can be formed to have multiple hardness, minimizing the occurrence of slip or release, and maximizing the planarization of the edge portion of the semiconductor wafer.

1 is a configuration diagram of a thin film for polishing a semiconductor wafer having multiple hardness according to an embodiment of the present invention;
Fig. 2 is an exemplary view for explaining the position of a zone on a forming plate for forming a thin film for polishing a semiconductor wafer having multiple hardnesses according to Fig. 1; Fig.
3 is a cross-sectional view of a coating layer of a thin film for polishing semiconductor wafers having multi-hardness according to Fig. 1,
4 is a configuration diagram of a semiconductor wafer polishing apparatus using a thin film for polishing a semiconductor wafer having multiple hardness according to another embodiment of the present invention;
FIG. 5 is a graph showing the degree of planarization of a semiconductor wafer during polishing by the polishing apparatus according to FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The terms used are terms selected in consideration of the functions in the embodiments, and the meaning of the terms may vary depending on the user, the intention or the precedent of the operator, and the like. Therefore, the meaning of the terms used in the following embodiments is defined according to the definition when specifically defined in this specification, and unless otherwise defined, it should be interpreted in a sense generally recognized by those skilled in the art.

Fig. 1 is a view showing the structure of a thin film for polishing a semiconductor wafer having multiple hardnesses according to an embodiment of the present invention, Fig. 2 is a view showing the position of a zone on a forming plate for forming a thin film for polishing semiconductor wafers having multi- FIG. 3 is a cross-sectional view of a coating layer of a thin film for polishing a semiconductor wafer having multiple hardnesses according to FIG. 1; FIG.

Referring to FIG. 1, a thin film 100 for polishing a semiconductor wafer having a multi-hardness according to an embodiment of the present invention includes a polishing pad for polishing a semiconductor wafer by an abrasive pad which is positioned below the semiconductor wafer and fixed by a retainer ring And is provided at the pressing portion of the semiconductor wafer polishing apparatus to come into contact with the upper portion of the semiconductor wafer.

More specifically, the semiconductor wafer polishing thin film 100 having multiple hardnesses includes a bottom portion 110 and an edge portion 120. The bottom portion 110 is a member having a circular shape, and is formed of an elastic flexible material. The bottom 110 is used for chemical mechanical polishing (CMP) and is in contact with one side of the semiconductor wafer. The bottom portion 110 may be formed of a material having a first hardness. For example, the bottom portion 110 has a hardness of 50 degrees, a tensile strength of 70 to 120 kgf / cm2, a elongation of 350 to 550%, a modulus of 20 to 28 kgf / .

The edge portion 120 is a ring-shaped partition wall extending and extending around the bottom portion 110. The edge portion 120 may be formed of a material having a second hardness. For example, the edge portion 120 may have a hardness of 70 degrees, a tensile strength of 70 to 120 kgf / cm2, a elongation of 350 to 550%, a modulus of 20 to 28 kgf / . Further, it is preferable that the bottom portion 110 and the edge portion 120 are dried at 80 DEG C for 120 minutes.

As shown in Fig. 2, there are a plurality of zones on the forming plate 200 for forming a thin film for polishing semiconductor wafers having multiple hardnesses. The forming plate 200 has a center zone 201, a first outer zone 202, a second outer zone 203, and a third outer zone 204. A material having a first hardness is injected into the center zone 201 on the forming plate 200 to form a bottom portion 110 and a material having a second hardness is injected into the third outer zone 204 to form the edge portions 120 ). For example, a material having a hardness of 50 degrees may be injected into the center zone 201, and a material having a hardness of 70 degrees may be formed in the third outer zone 204. In this case, the bottom portion 110 and the edge portion 120 are integrally molded so that the bottom portion 110 exhibits a hardness of 50 to 55 degrees and the edge portion 120 exhibits a hardness of 60 to 65 degrees.

One 2 3 4 5 6 7 8 9 10 11 12 Average Third Outer Zone 63.1 62.2 61.7 62.7 60.8 63 62.2 61.3 60.6 61.7 63.2 63.4 62.16 Second Outer Zone 57.5 57.5 57.4 57.4 54.6 54.2 54.2 54.2 53.5 53.9 53.6 54.4 55.20
First outer zone
54.5 55.7 55.9 55.6 54 53.7 53.3 53.6 53.2 53.6 53.9 53.5 54.21 53.5 54.6 54.6 54.4 53.1 53 52.9 53.4 52.8 52.7 53.1 52.9 53.42 52.6 53.3 53.1 53.2 52.5 52.5 52.6 52.8 52.2 52.3 52.7 52.4 52.68 52.2 52 51.5 51.5 51.2 51.6 52.1 52.2 51.7 51.7 51.7 51.6 51.75

Center zone

51.5 52.2 52.1 51.6 51.6 51.3 52 52 51.9 51.5 51.9 51.6 51.77 52.1 51.9 51.8 51.6 51.5 51.1 51.8 51.9 52.3 51.5 52.8 51.3 51.80 52 52.3 51.6 51.6 51.2 51.2 51.9 51.9 52 51.3 52.4 51.5 51.74 51.7 51.8 52.2 51.5 51.9 51.2 51.8 51.6 52.2 51.3 52.2 51.4 51.73 51.5 51.9 52.1 51.5 51.6 51.1 51.2 51.5 51.9 51.4 52.3 51.4 51.62

As shown in Table 1, the edge portion 120 corresponding to the third outer zone 204 exhibits a hardness of 62.16 degrees similar to a hardness of 70 degrees (actual hardness 63 to 64 degrees). The bottom portion 110 corresponding to the center zone 201, the first outer zone 202 and the second outer zone 203 has a hardness similar to that of the hardness of 50 degrees (real hardness of 51 to 52 degrees).

Hardness 50 Hardness 70 ΔP Center zone First outer zone Second Outer Zone Third Outer Zone ΔP Center zone First outer zone Second Outer Zone Third Outer Zone ± 80 hPa - - No Leak No Leak ± 80 hPa - - - - ± 40 hPa No Leak No Leak No Leak No Leak ± 40 hPa - - - - ± 20 hPa No Leak No Leak No Leak No Leak ± 20 hPa No Leak No Leak Leak No Leak

As shown in Table 2, when the thin film 100 for polishing a semiconductor wafer having multiple hardness was tested for leaks, LEAK occurred in the second outer zone at a hardness of 70. However, at a hardness of 50, .

The bottom portion 110 corresponding to the center zone 201, the first outer zone 202 and the second outer zone 203 is formed of a material having a hardness of 50 and the bottom portion 110 corresponding to the third outer zone 204 Even if the edge portion 120 is formed of a material having a hardness of 70, LEAK is not generated.

The outer surface of the contact portion between the bottom portion 110 and the edge portion 120 may be inclined at a predetermined angle. That is, it may be formed upward from the bottom portion 110 to the edge portion 120. In this case, it is preferable that a portion where the bottom portion 110 and the edge portion 120 abut each other is formed to have an inclination of 21 degrees to 50 degrees from the bottom surface of the bottom portion 110. More specifically, the width a of the inclined plane is 1 to 4 mm, the height b of the inclined plane is 1 to 4 mm, the ratio of the width a of the inclined plane to the height b of the inclined plane is 1: 1 But it is not necessarily limited thereto.

On the other hand, the thin film 100 for polishing semiconductor wafers having multi-hardness of the present invention is used for a polishing apparatus (not shown), and the inner side of a retainer ring (not shown) of the polishing apparatus has a polishing pad It may be formed to be inclined at an angle. More specifically, the retainer ring may be formed such that the inner portion thereof is inclined at an angle of 1 to 50 degrees with respect to the polishing pad.

The thin film 100 for polishing a semiconductor wafer having a multi-hardness according to another embodiment of the present invention may further include a coating layer 130. The coating layer 130 is formed by vacuum-depositing poly-para-xylylene on the outer surface of the bottom portion 110. That is, the polyparaxylene is vaporized into a gaseous state and chemically fixed to the outer surface of the bottom portion 110. In this case, the coating layer 130 can be formed using polyparaxylyene represented by the following Chemical Formula 1.

Figure 112015105053419-pat00002

In the general formula (1), n represents a non-zero integer, and preferably n is an integer of 1 to 100.

The polyparaxylene forming the coating layer 130 has a vaporization temperature of 180 ° C. and is heated to 670 ° C. and vacuum-deposited at a pressure of 10 to 50 mTorr to form an outer surface of the bottom portion 110 having a thickness of 0.3 to 1 μm .

Example

In order to determine the coating performance according to the pressurizing condition, the polyparaxylene represented by Chemical Formula 1 was formed at a vaporization temperature of 180 ° C, a heating temperature of 670 ° C, and a coating thickness of 0.3 to 3 μm, The slip occurrence rate and the release occurrence rate were tested as shown in Table 1 for 50 samples.
Vacuum degree
transparency
Leveling
Coating thickness Slip occurrence Release occurred Number of tests Incidence rate Number of tests Incidence rate One 100 mTorr Translucent no good 1 to 3 μm 50 4% 50 12% 2 10 to 50 mTorr Transparency good 0.3 to 1 탆 50 0% 50 0% 3 0.1 mTorr Transparency no good 0.3 to 3 탆 50 2% 50 10%

As shown in Table 3, in the case of Experiment 1, transparency is lowered, leveling is poor, and slip and release are maximized when the vacuum degree of the coating chamber is 100 mTorr or more. In Experiment 2, the best results were obtained in transparency, leveling, slip and release when the degree of vacuum was 10 to 50 mTorr. In Experiment 3, the leveling, sleeping, and releasing performance were lower when the vibration level was less than 0.1 mTorr. Therefore, it can be seen that the degree of vacuum in the case of 10 to 50 mTorr is the optimum coating condition as in Experimental Example 2. 3 shows a cross-section of a coating layer produced under the same conditions as in Experimental Example 2. Fig.

4 is a configuration diagram of a semiconductor wafer polishing apparatus using a thin film for polishing a semiconductor wafer having multiple hardness according to another embodiment of the present invention.

4, a semiconductor wafer polishing apparatus 400 using a thin film for polishing a semiconductor wafer having a multi-hardness according to another embodiment of the present invention includes a main body 410, a driving unit 420, a pressing unit 430, A polishing thin film 440, and a retainer ring 450.

The main body 410 is a member constituting the body of the semiconductor wafer polishing apparatus 400. A driving unit 420 and a retainer ring 450, which will be described later, are connected to the body 410. The main body 410 may include a control circuit (not shown) that can control the rotational speed of the driving unit 420 or the pressure of the pressing unit 430, which will be described later. In addition, the body portion 410 includes a general configuration used in a conventional chemical mechanical polishing apparatus.

The driving part 420 is connected to the lower part of the body part 410 and is rotatably driven. More specifically, the driving unit 420 serves to rotate the semiconductor wafer 500 using the polishing thin film 440 attached to the pressing unit 430 by rotating the pressing unit 430 to be described later. The control speed of the driving unit 420 may vary depending on the setting of the user.

The pressing portion 430 is connected to the driving portion 420 and presses a plurality of pressing chambers (not shown) downward. Specifically, the pressing portion 430 allows the polishing thin film 440 to efficiently press the semiconductor wafer 500 by using a plurality of pressing chambers on the polishing thin film 440 attached to the outer surface. The pressure of the pressurizing unit 430 may vary depending on the setting of the user.

The polishing thin film 440 includes a bottom portion 441 and an edge portion 120. The bottom portion 441 is a member having a circular shape and is formed of an elastic flexible material. The bottom portion 441 is used for chemical mechanical polishing (CMP) and contacts one surface of the semiconductor wafer. The bottom portion 441 may be formed of a material having a first hardness. For example, the bottom portion 441 has a hardness of 50 degrees, a tensile strength of 70 to 120 kgf / cm2, a elongation of 350 to 550%, a modulus of 20 to 28 kgf / .

The edge portion 442 is a ring-shaped partition wall extending around the bottom portion 441. The edge portion 442 may be formed of a material having a second hardness. For example, the edge portion 442 may have a hardness of 70 degrees, a tensile strength of 70 to 120 kgf / cm2, a elongation of 350 to 550%, a modulus of 20 to 28 kgf / . It is preferable that the bottom portion 441 and the edge portion 442 are dried at 80 DEG C for 120 minutes.

As shown in Fig. 2, there are a plurality of zones on the forming plate 200 for forming a thin film for polishing semiconductor wafers having multiple hardnesses. The forming plate 200 has a center zone 201, a first outer zone 202, a second outer zone 203, and a third outer zone 204. A material having a first hardness is injected into the center zone 201 on the forming plate 200 to form a bottom portion 441 and a material having a second hardness is injected into the third outer zone 204 to form an edge portion 442 ). For example, a material having a hardness of 50 degrees may be injected into the center zone 201, and a material having a hardness of 70 degrees may be formed in the third outer zone 204. In this case, the bottom portion 441 and the edge portion 442 are integrally molded so that the bottom portion 441 shows a hardness of 50 to 55 degrees and the edge portion 442 shows a hardness of 60 to 65 degrees.

The retainer ring 450 is connected to the body 410 and is formed on the outer side of the polishing film 440. The retainer ring 450 presses and fixes the polishing pad 600 located under the semiconductor wafer 500. That is, the semiconductor wafer 500 is moved by the polishing thin film 440 attached to the pressing portion 430 while being rubbed and polished by the polishing pad 600 formed at the lower portion.

Further, the retainer ring 450 includes a steel portion 451 and a resin portion 452. The steel portion 451 corresponds to a framework that forms the shape of the retainer ring 450. The steel portion 451 may be formed such that the inner side is inclined at a predetermined angle from the bottom surface. More specifically, the inner side portion of the steel portion 451 may be formed so that the bottom surface and the inner angle are inclined at 1 to 50 degrees. In this case, it is preferable that the width a 'of the flat end portion and the width b' of the sloping portion in the vertical cross section of the steel portion 451 are 12 mm, for example, The ratio of the width a 'to the width b' of the inclined portion is preferably 1: 1.

The resin portion 452 is a member of a resin material that surrounds the steel portion 451. The resin part 452 is formed by surrounding the steel part 451 so that the inclined part of the steel part 451 is filled with the resin so that the inclined part is not exposed from the outside.

FIG. 5 is a graph showing the degree of planarization of a semiconductor wafer during polishing by the polishing apparatus according to FIG.

Referring to FIG. 5, the horizontal axis of the graph represents the radius (mm) of the semiconductor, and the vertical axis of the graph represents the flatness of the semiconductor. (a) shows a case where the inclination angle of the abrasive thin film is 45 degrees, the ratio of the width (a) of the inclined plane to the height (b) of the inclined plane is 1: 1, and the inclination angle of the retainer ring 450 is 45 degrees . (b) shows a case where the inclination angle of the abrasive thin film is 2 to 20 degrees and the inclined angle of the retainer ring 450 is absent. (c) shows a case where the inclination angle of the abrasive thin film is less than 0 to 2 degrees.

As shown in Fig. 4, in the case of (a) using the inclination angle of the abrasive thin film 440 and the retainer ring 450, the portion of the semiconductor wafer 500 which is equal to or lower than the reference flatness k of the semiconductor wafer 500 is 1.8 mm, (K) of the semiconductor wafer 500 is 2.5 mm, and in the case of (c), the portion of the semiconductor wafer 500 which is equal to or lower than the reference flatness k of the semiconductor wafer 500 is 5.0 mm. As described above, when the inclined angle of the polishing film and the retainer ring 450 is used, the area available for polishing the semiconductor wafer 500 is remarkably increased.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, Therefore, the present invention should be construed as a description of the claims which are intended to cover obvious variations that can be derived from the described embodiments.

100: Polishing thin film
110:
120: edge portion
130: Coating layer
200: forming plate
201: Center Zone
202: 1st Outer Zone
203: second outer zone
204: Third Outer Zone
400: semiconductor wafer polishing apparatus
410:
420:
430:
440: Root for polishing
441:
442:
450: retainer ring
451: Steel part
452:
500: semiconductor wafer
600: abrasive pad

Claims (5)

There is provided a semiconductor wafer polishing thin film provided on a pressing portion of a semiconductor wafer polishing apparatus for polishing the semiconductor wafer by a polishing pad which is positioned below a semiconductor wafer and fixed by a retainer ring, ,
A bottom portion formed of a material having a first hardness and formed in a circular planar shape; And an edge portion formed of a material having a second hardness higher than that of the bottom portion and extending and extending around the bottom portion,
The bottom and the edge,
70 to have a tensile strength of 120kgf / cm 2, with a elongation of 350 to 550%, 20 to be formed to have a modulus of 28kgf / cm 2, the bottom portion and the edge portion abutting part from the plane wherein the bottom portion The ratio of the width of the inclined surface to the height of the inclined surface is 1: 1, and the retainer ring is formed so as to have an angle of inclination of 45 degrees with the polishing pad inward. Abrasive thin film. The method according to claim 1,
Wherein the bottom portion is formed of a material having a hardness of 50 degrees and the edge portion is formed of a material having a hardness of 70 degrees and the bottom portion and the edge portion are integrally molded so that the bottom portion exhibits a hardness of 50 to 55 degrees, Wherein the portion has a hardness of 60 to 65 degrees. delete 3. The method according to claim 1 or 2,
Further comprising a coating layer formed by vacuum-depositing poly-para-xylylene on the outer surface of the bottom portion,
The polyparaxylylene,
And has a vaporization temperature of 180 캜 and is heated to 670 캜 and vacuum deposited to a thickness of 0.3 to 1 탆 on the outer surface of the bottom at a pressure of 10 to 50 mTorr to form the coating layer A thin film for polishing semiconductor wafers having multiple hardness:
[Chemical Formula 1]
Figure 112016076001410-pat00003

In the general formula (1), n represents a non-zero integer. A body portion;
A driving unit connected to the main body and rotationally driven;
A pressing part connected to the driving part and pressing the pressing part downward;
A bottom portion which is attached to the pressing portion and which is formed on a top surface of the semiconductor wafer and which is formed of a material having a first hardness and is formed into a circular planar shape and a material having a second hardness higher than that of the bottom portion, A polishing thin film including an edge portion extending and extending around the bottom portion; And
And a retainer ring connected to the main body and formed on an outer side of the thin film for polishing to press a polishing pad located under the semiconductor wafer,
Wherein the edge portion of the retainer ring is formed inwardly inclined at a predetermined angle with the polishing pad,
The bottom and the edge,
70 to have a tensile strength of 120kgf / cm 2, with a elongation of 350 to 550%, 20 to be formed to have a modulus of 28kgf / cm 2, the bottom portion and the edge portion abutting part from the plane wherein the bottom portion The ratio of the width of the inclined surface to the height of the inclined surface is 1: 1, and the retainer ring is formed so as to have an angle of inclination of 45 degrees with the polishing pad inward. A semiconductor wafer polishing apparatus using a polishing thin film.
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WO2019191660A1 (en) * 2018-03-30 2019-10-03 Saint-Gobain Abrasives, Inc. Bonded abrasive article including a coating
CN111469044A (en) * 2020-05-18 2020-07-31 中国科学院微电子研究所 Diaphragm plate, grinding head and chemical mechanical grinding device
US11059147B2 (en) 2018-03-30 2021-07-13 Saint-Gobain Abrasives, Inc./Saint-Gobain Abrasifs Abrasive article including a coating
KR102504029B1 (en) 2022-02-24 2023-02-28 세정로봇 주식회사 Multi wafer transfer machine for cmp process

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WO2019191660A1 (en) * 2018-03-30 2019-10-03 Saint-Gobain Abrasives, Inc. Bonded abrasive article including a coating
US10933508B2 (en) 2018-03-30 2021-03-02 Saint-Gobain Abrasives, Inc./Saint-Gobain Abrasifs Bonded abrasive article including a coating
US11059147B2 (en) 2018-03-30 2021-07-13 Saint-Gobain Abrasives, Inc./Saint-Gobain Abrasifs Abrasive article including a coating
CN111469044A (en) * 2020-05-18 2020-07-31 中国科学院微电子研究所 Diaphragm plate, grinding head and chemical mechanical grinding device
KR102504029B1 (en) 2022-02-24 2023-02-28 세정로봇 주식회사 Multi wafer transfer machine for cmp process

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