KR101685652B1 - Semiconductor Packages and Stack Structures of the Same and Methods of Fabricating the Same - Google Patents

Semiconductor Packages and Stack Structures of the Same and Methods of Fabricating the Same Download PDF

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Publication number
KR101685652B1
KR101685652B1 KR1020100052827A KR20100052827A KR101685652B1 KR 101685652 B1 KR101685652 B1 KR 101685652B1 KR 1020100052827 A KR1020100052827 A KR 1020100052827A KR 20100052827 A KR20100052827 A KR 20100052827A KR 101685652 B1 KR101685652 B1 KR 101685652B1
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South Korea
Prior art keywords
package
connection portion
semiconductor
package substrate
chip
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KR1020100052827A
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Korean (ko)
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KR20110069681A (en
Inventor
권흥규
나민옥
박성우
박지현
박수민
Original Assignee
삼성전자주식회사
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Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority to US12/910,415 priority Critical patent/US8508954B2/en
Priority to CN2010105942754A priority patent/CN102104035A/en
Publication of KR20110069681A publication Critical patent/KR20110069681A/en
Priority to US13/934,942 priority patent/US9042115B2/en
Priority to US14/693,352 priority patent/US20150228627A1/en
Priority to US15/241,452 priority patent/US9978721B2/en
Application granted granted Critical
Publication of KR101685652B1 publication Critical patent/KR101685652B1/en
Priority to US15/971,600 priority patent/US10403606B2/en
Priority to US16/448,392 priority patent/US10593652B2/en

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Abstract

Semiconductor modules and electronic systems including stacked structures of semiconductor packages and their fabrication methods, stacked structures of semiconductor packages are described. The laminated structure of the semiconductor packages according to the technical idea of the present invention includes a lower semiconductor package including a lower package substrate and a lower semiconductor chip disposed on the upper portion of the lower package substrate, An upper semiconductor package including an upper semiconductor chip, and an inter-package connection portion for electrically connecting the lower package substrate and the upper package substrate, wherein the inter-package connection portion has a first vertical height And an upper connection portion having a second vertical height greater than the first vertical height formed at a lower portion of the upper package substrate.

Description

Semiconductor Packages, Stack Structures of the Same and Methods of Fabricating the Same < RTI ID = 0.0 >

The present invention relates to semiconductor packages and electronic systems including semiconductor packages, stacked structures of semiconductor packages and their fabrication methods, and stacked structures of the semiconductor packages.

A method of stacking packaged semiconductor chips as a method for diversifying functions of semiconductor devices has been proposed.

A problem to be solved by the present invention is to provide a semiconductor package.

Another object to be solved by the present invention is to provide a laminated structure of semiconductor packages.

Still another object of the present invention is to provide a method of manufacturing a laminated structure of semiconductor packages.

Another object of the present invention is to provide a semiconductor module including a laminated structure of semiconductor packages.

Another object of the present invention is to provide an electronic system including a laminated structure of semiconductor packages.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other matters not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a semiconductor package comprising a package substrate, a semiconductor chip disposed on an upper surface of the package substrate, a first semiconductor chip disposed between the upper surface of the package substrate and a lower surface of the semiconductor chip, A molding material formed on an upper surface of the package substrate and covering a side surface of the semiconductor chip and covering a part of the first conductors; Holes extending vertically through the molding material to expose a surface of the first conductors, wherein a portion from a surface of the package substrate to an upper portion of the first conductors is defined as a first vertical height, Wherein the second vertical height is defined as a second vertical height from the first vertical height to the upper surface of the molding material, Big.

According to an aspect of the present invention, there is provided a semiconductor package stack structure including a lower semiconductor package including a lower package substrate and a lower semiconductor chip disposed on an upper portion of the lower package substrate, an upper package substrate, An upper semiconductor package including an upper semiconductor chip disposed on an upper portion of the upper package substrate, and an inter-package connection portion electrically connecting the lower package substrate and the upper package substrate, wherein the inter- A lower connection portion having a first vertical height formed on the upper package substrate, and an upper connection portion having a second vertical height larger than the first vertical height formed on a lower portion of the upper package substrate.

According to an aspect of the present invention, there is provided a semiconductor package stack structure including a lower semiconductor package including a lower package substrate and a lower semiconductor chip disposed on an upper portion of the lower package substrate, an upper package substrate, An upper semiconductor package including an upper semiconductor chip disposed on an upper portion of the upper package substrate, and an inter-package connection portion electrically connecting the lower package substrate and the upper package substrate, wherein the inter- A lower connection portion formed on the upper surface; A mesa-shaped intermediate connection portion formed on the upper portion of the lower connection portion; And upper connection portions formed on the lower surfaces of the upper and upper package substrates of the mesa-shaped intermediate connection portion.

According to another aspect of the present invention, there is provided a method of fabricating a stacked structure of semiconductor packages, comprising: preparing an upper semiconductor package having an upper semiconductor chip mounted on an upper surface of an upper package substrate; Forming a lower semiconductor package having a lower semiconductor chip mounted on an upper surface thereof and forming an inter-package connection portion electrically connecting the upper semiconductor package and the lower semiconductor package, A lower connection portion having a first vertical height is formed on an upper surface of a lower package substrate and an upper connection portion having a second vertical height larger than the first vertical height is formed on a lower surface of the upper package substrate, And connecting the upper connection.

The details of other embodiments are included in the detailed description and drawings.

As described above, the stacked structure of the semiconductor packages according to the technical idea of the present invention can include the inter-package connections formed stably even when the mutual spacing of the inter-package connections is very narrow. That is, according to the technical idea of the present invention, even if the mutual spacing between the packages is gradually narrowed, the lamination structure of the next generation semiconductor packages will not be a big problem. The method of fabricating the stacked structure of semiconductor packages according to the technical idea of the present invention can be realized without great technical difficulties. The electronic system according to the technical idea of the present invention is smaller in size and has more excellent performance.

1A and 1B are plan views schematically illustrating lower semiconductor packages in package lamination structures according to the technical idea of the present invention.
2A to 2H are longitudinal sectional views conceptually showing laminated structures of semiconductor packages according to the technical idea of the present invention.
3A and 3B are longitudinal cross-sectional views conceptually showing laminated structures of semiconductor packages including chip connection portions according to the technical idea of the present invention.
FIG. 4 is a conceptual illustration of another application example of lamination structures of semiconductor packages according to the technical idea of the present invention.
5A to 5D are longitudinal cross-sectional views conceptually showing chip connecting portions and their connecting structures according to the technical idea of the present invention.
6A to 6D are longitudinal cross-sectional views conceptually showing chip connecting portions and their connection structures according to the technical idea of the present invention.
FIGS. 7A to 7D are longitudinal cross-sectional views conceptually showing hypothetical shapes of various connections of package laminate structures according to the technical idea of the present invention.
8A to 8I are conceptual diagrams showing actual shapes of various connection portions of package lamination structures according to the technical idea of the present invention.
FIGS. 9A to 9I are conceptual diagrams showing the shapes of various connection portions and via holes of the package laminate structures according to the technical idea of the present invention.
10A to 10F are longitudinal cross-sectional views illustrating a method of forming a top package in a method of forming a laminated structure of semiconductor packages according to the technical idea of the present invention.
11A to 11L are longitudinal cross-sectional views for conceptually illustrating a method of forming stacked structures of semiconductor packages according to the technical idea of the present invention.
12A and 12B are conceptual diagrams of semiconductor modules including a stacked structure of semiconductor packages according to various embodiments of the technical concept of the present invention.
13 is a conceptual illustration of an electronic system including a stacked structure of semiconductor packages according to various embodiments of the technical concept of the present invention.

Brief Description of the Drawings The advantages and features of the present invention, and how to achieve them, will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. The dimensions and relative sizes of layers and regions in the figures may be exaggerated for clarity of illustration. Like reference numerals refer to like elements throughout the specification.

Embodiments described herein will be described with reference to plan views and cross-sectional views, which are ideal schematics of the present invention. Thus, the shape of the illustrations may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include changes in the shapes that are generated according to the manufacturing process. Thus, the regions illustrated in the figures have conceptual properties, and the shapes of the regions illustrated in the figures are intended to illustrate specific forms of regions of the elements and are not intended to limit the scope of the invention.

In the present specification, some components, particularly various connection parts, are shown in an imaginary shape to facilitate understanding of the technical idea of the present invention. However, some practical shapes will also be explained. In this specification, the components described as being formed of a solder material can be interpreted to mean that they can be formed using a soldering process.

1A and 1B are plan views schematically illustrating lower semiconductor packages in package lamination structures according to the technical idea of the present invention. 1A, the lower semiconductor package 115L includes a lower package substrate 110L, a lower semiconductor chip 115L disposed on the lower package substrate 110L, and a lower semiconductor chip 115L on the periphery of the lower semiconductor chip 115L. And a plurality of package-to-package connections 150 arranged therein. Referring to FIG. 1B, the lower semiconductor package 215L includes a lower package substrate 215L, a lower semiconductor chip 215L disposed on the lower package substrate 215L and including a plurality of chip connection portions 285, And a plurality of inter-package connections 250 disposed around the lower semiconductor chip 215L. The lower semiconductor packages 105L and 205L shown in Figs. 1A and 1B will be described in more detail.

2A to 2H are longitudinal sectional views conceptually showing laminated structures of semiconductor packages according to the technical idea of the present invention. 2A, a laminated structure 100A of semiconductor packages includes a lower semiconductor package 105L, an upper semiconductor package 105U, and an inter-package connection 105B electrically connecting the lower and upper semiconductor packages 105L and 105U. And inter-package connectors 150a. A portion of the inter-package connection portions 150a may be formed as a part of the lower semiconductor package 105L. Another part of the inter-package connections 150a may be formed as a part of the upper semiconductor package 105U.

The lower semiconductor package 105L includes a lower package substrate 110L, a lower semiconductor chip 115L formed on the upper surface of the lower package substrate 110L, conductive chip bumps 120 and a lower molding material 130L, And conductive solder balls 125 formed on the lower surface of the lower package substrate 110L. The lower semiconductor package 105L may be flip chip technology. The lower package substrate 110L may be a package substrate, for example, a printed circuit board, a ceramic substrate, or the like.

The lower semiconductor chip 115L may be a logic device such as a microprocessor. The lower semiconductor chip 115L may be disposed on one side of the lower package substrate 110L. The lower semiconductor chip 115L is electrically connected to the solder balls 125 formed on the lower surface of the lower semiconductor substrate 105L through the conductive chip bumps 120 formed on the upper surface of the lower semiconductor substrate 105L . That is, the lower semiconductor chip 115L may include a flip-chip connection structure having a grid array or the like.

The conductive chip bumps 120 may be disposed between the lower package substrate 110L and the lower semiconductor chip 115L. The conductive chip bumps 120 may electrically connect the lower package substrate 110L and the lower semiconductor chip 115L. The conductive chip bumps 120 may include solder material. Therefore, it can be formed by a soldering process.

The solder balls 125 may be a component for electrically connecting the package laminate structure 100a to a module board or a main circuit board.

The lower molding material 130L may be formed so as to surround the perimeter of the acupuncture bumps 120. An adhesive may be formed around the chip bumps 120, that is, between the lower semiconductor chip 115L and the lower package substrate 110L. The lower molding material 130L may be formed to surround a side surface of the lower semiconductor chip 115L. Specifically, the lower semiconductor chip 115L is adhered to the upper surface of the lower semiconductor substrate 105L using the adhesive, and the periphery of the lower semiconductor chip 115L can be surrounded by the lower molding material 130L have. In the present description, it is described that the adhesive is included in the lower molding material 130L. In addition, the lower molding material 130L may be formed to surround the side surfaces of the inter-package connection portions 150a. The upper surface of the lower semiconductor chip 115L may not be covered with the lower molding material 130L. That is, the upper surface of the lower semiconductor chip 115L may be exposed. In addition, the upper surface of the lower molding material 130L may be similar or substantially identical to the upper surface of the lower semiconductor chip 115L. When the upper surface of the lower semiconductor chip 115L is exposed to the outside, the structural, electrical, and physical characteristics of the lower semiconductor package 105L can be improved. For example, since the thickness of the lower semiconductor package 105L is reduced first, the heat radiation characteristic is improved and the package laminate structure 100a is also thinned. In addition, since the resistance to the high-temperature process is improved, the resistance to bending or twisting is also improved, so that the flatness of the lower package substrate 105L and the lower semiconductor chip 115L can be improved. In addition, since it is possible to apply a physical pressure directly to one surface of the lower semiconductor chip 115L without passing through the molding material, the grid array technology, the multilayer molding technique, and the like can be stably applied. When the thickness of the lower molding material 130L is lowered, the overall height of the inter-package connection portions 150a may be lowered. Since the package-to-package connections 150a may be formed using a soldering process, the overall height of the package-to-package connections 150a may be reduced, . The structures formed by the soldering process are ideally spherical. The reduction in the maximum horizontal width of the inter-package connections 150a can be understood to mean that the size of the volume of the inter-package connections 150a can be reduced. That is, it is possible to reduce the interval or the pitch of the inter-package connections 150a. Accordingly, when the thickness of the lower molding material 130L is reduced, the inter-package connection portions 150a can be formed finer and more precisely. One of the challenges of current and next-generation semiconductor package stacking technology is to implement the fine pitch of the connections between packages. Therefore, according to the technical idea of the present invention, the semiconductor package lamination structure 100a having finer and more sophisticated package-to-package connections 150a can be formed.

The upper semiconductor package 105U includes an upper package substrate 110U and an upper semiconductor chip 115U. The upper package substrate 110U may be a package substrate, for example, a printed circuit board, a ceramic substrate, or the like.

The upper semiconductor chip 115U may be a memory device such as a DRAM or a flash. The upper semiconductor chip 115U may have a horizontal width or an area larger than the lower semiconductor chip 115L. When the upper semiconductor chip 115U is wider in the horizontal direction than the lower semiconductor chip 115L, the area occupied by the inter-package connection portions 150a is widened, Can be formed smaller. The greater the area occupied by the inter-package connections 150a is, the more inter-package connections 150a can be formed. Alternatively, when the number of the inter-package connections 150a is the same, the stacked structure 100a of the semiconductor packages can be made smaller. The upper semiconductor chip 115U may be disposed on the upper surface of the upper package substrate 110U. The upper semiconductor chip 115U may be electrically connected to the upper package substrate 110U through bonding pads 135, bonding wires 140, and wire pads 145. [

The bonding pads 135 may be formed on the upper surface of the upper semiconductor chip 115U. The wire pads 145 may be formed on the upper surface of the upper package substrate 110U. The bonding wires 140 may electrically connect the bonding pads 135 and the wire pads 145 to each other.

The upper semiconductor chip 115U may be covered with the upper molding material 130U. The upper package substrate 110U can be understood from the description of the lower package substrate 110L unless otherwise described.

The inter-package connections 150a may physically or electrically connect one surface of the lower package substrate 105L and the other surface of the upper package substrate 105U. The inter-package connection portions 150a include lower connection portions 160a and upper connection portions 180a. The lower and upper connection portions 160a and 180a may be formed of a solder material. The inter-package connections 150a will be described in more detail below.

In addition, the upper semiconductor chip 115U may have a larger horizontal width than the lower semiconductor chip 115L. In the technical aspect of the present invention, the inter-package connection portions 150a are formed on the upper or upper surface of the lower package substrate 110L. This is the same surface as the surface on which the lower semiconductor chip 115L is formed. On the other hand, the inter-package connection portions 150a are formed on the lower or lower surface of the upper package substrate 110U. The upper semiconductor chip 115U is not formed. Accordingly, the inter-package connection portions 150a may be influenced by the size of the lower semiconductor chip 115L. The stacked structure 100a of the semiconductor packages has an area standard defined by a semiconductor standard protocol or the like. Therefore, when the lower semiconductor chip 115L is larger than the upper semiconductor chip 115U, the space constraints that the package-to-package connection portions 150a can be formed are increased, and the efficiency is lowered. However, according to the technical idea of the present invention, when the upper semiconductor chip 115U is larger than the lower semiconductor chip 115L, the spatial restriction is less and the efficiency is also improved. Therefore, it is included in the technical idea of the present invention that the upper semiconductor chip 115U is larger than the lower semiconductor chip 115L.

Referring to FIG. 2B, the laminated structure 100b of semiconductor packages includes a lower semiconductor package 105L, an upper semiconductor package 105U, and an inter-package connection 105B electrically connecting the lower and upper semiconductor packages 105L and 105U. (150b). The inter-package connection portions 150b include lower connection portions 160b and upper connection portions 180b. The lower and upper connection portions 160b and 180b may be formed of a solder material. The lower connection portions 160b may be hemispherical. The inter-package connections 150b will be described in more detail below. The description of the other components will be understood with reference to FIG. 2A and the description thereof.

Referring to FIG. 2C, the stacked structure 100c of semiconductor packages includes a lower semiconductor package 105L, an upper semiconductor package 105U, and an inter-package connection 105B electrically connecting the lower and upper semiconductor packages 105L and 105U. (150c). The package connecting portions 150c include bottom connecting portions 165c and upper connecting portions 180c. The bottom connection portions 165c may be formed in a mesa shape or a column shape. For example, in the form of a cylinder or a polygonal column.

The bottom connection portions 165c may be attached to the upper surface of the lower package substrate 110L. For example, the bottom connection portions 165c may be formed of a metal, and may be formed by various methods such as casting, vapor deposition, adhesion or plating, and may be attached on the lower package substrate 110L.

In addition, a metal barrier layer may be formed on the surface of the bottom connection parts 165c. For example, the body of the bottom connection portions 165c may be formed of copper, and a metal barrier layer such as nickel may be formed on the surface. The metal barrier layer is omitted in order to avoid complication of the drawing.

Although the upper connection portions 180c are illustrated as being larger than the bottom connection portions 165c, they need not necessarily be. The drawings are exaggerated for easy understanding of the technical idea of the present invention.

The process of forming the bottom connecting portions 165c in a mesa shape on the upper surface of the lower package substrate 110L may be less affected by the mutual spacing of the bottom connecting portions 165c than the process of forming by soldering. Accordingly, the bottom connecting portions 165c may be formed in various shapes. For example, the horizontal size may be smaller than the drawing and the vertical size may be larger than the drawing. In this case, only a small portion of the upper connection portions 180c may be formed lower than the surface of the lower molding material 130L. In other words, the center point of the upper connection part 180c may be formed higher than the upper surface of the lower molding material 130L. Although the top connection portions 180c are illustrated as being circular in cross-section, they are not necessarily so. For example, an elliptical shape. The upper connection portions 180c may be formed of a solder material. The package-to-package connections 150c will be described in more detail below. The description of the other components will be understood with reference to FIG. 2A and the description thereof.

2D, the laminate structure 100d of semiconductor packages includes a lower semiconductor package 105L, an upper semiconductor package 105U, and an inter-package connection 105D for electrically connecting the lower and upper semiconductor packages 105L and 105U. And 150d. The package connection portions 150d include a lower connection portion 160d, an intermediate connection portion 170d, and an upper connection portion 180d. The lower connection portions 160d may be formed in a spherical or hemispherical shape. A virtual center point of the lower connection portions 160d may be formed above or below the upper surface of the lower package substrate 110L. The intermediate connection portions 170d may be formed in a mesa shape like the bottom connection portions 165c shown in FIG. 2C, and may be attached on the lower connection portions 160d. The intermediate connection portions 170d may be formed of copper, and a metal barrier layer of, for example, nickel may be formed on the surface. The metal barrier layer is omitted in order to avoid complication of the drawing. The lower and upper connection portions 160d and 180d may be formed of a solder material. The package-to-package connections 150d will be described in more detail below. The description of the other components will be understood with reference to FIG. 2A and the description thereof.

2E, a laminate structure 100e of semiconductor packages includes a lower semiconductor package 105L, an upper semiconductor package 105U, and an inter-package connection 105B that electrically connects the lower and upper semiconductor packages 105L and 105U. (150e). The inter-package connection portions 150e include lower connection portions 160e, intermediate connection portions 170e, intermediate bonding portions 175e, and upper connection portions 180e. The lower connection portions 160e and the intermediate connection portions 170e may be formed with reference to descriptions of the lower connection portions 160b and 160d, the bottom connection portions 165c, and the intermediate connection portions 170d shown in FIGS. Can be understood. The intermediate adhering portions 175e may be formed on the intermediate connecting portions 170e. Although the cross-section of the intermediate adhering portions 175e is shown as being elliptical in the drawing, it is not necessarily required. The intermediate adhering portions 175e may be formed in a spherical or hemispherical shape. When the intermediate adhering portions 175e are formed hemispherically, it can be understood with reference to the lower connecting portions 160b and 160d shown in FIGS. 2B and 2D and the description thereof. In addition, a center point or a virtual center point of the intermediate adhering portions 175e may be formed on the upper surface of the intermediate connecting portions 170e or may be formed below. The lower connection portions 160e, the intermediate bonding portions 175e, and the upper connection portions 180e may be formed of a solder material. The package-to-package connections 150e will be described in more detail below. The description of the other components will be understood with reference to FIG. 2A and the description thereof.

Referring to FIG. 2F, the laminate structure 100f of semiconductor packages includes a lower semiconductor package 105L, an upper semiconductor package 105U, and an inter-package connection 105B electrically connecting the lower and upper semiconductor packages 105L and 105U. (150f). The package connection portions 150f include lower connection portions 160f and package bumps 190f. The lower connection portions 160f can be understood with reference to FIG. 2A and the description thereof. The package bumps 190f may be formed of a metal such as a stud, a stick, or a pillar. The package bumps 190f may be manufactured in a separate process and fixed to the upper package substrate 110U. The package bumps 190f may be formed of copper or the like, and a metal barrier layer such as nickel may be formed on the surface. The metal barrier layer is omitted in order to avoid complication of the drawing. The package-to-package connections 150f will be described in more detail below. The description of the other components will be understood with reference to FIG. 2A and the description thereof.

Referring to FIG. 2G, the laminated structure 100g of semiconductor packages includes a lower semiconductor package 105L, an upper semiconductor package 105U, and an inter-package connection 105R electrically connecting the lower and upper semiconductor packages 105L and 105U. (150g). The inter-package connections 150g include bottom connection portions 165g, intermediate bonding portions 175g, and package bumps 190f. The bottom connection portions 165g, the intermediate bonding portions 175g, and the package bumps 190f may be understood with reference to FIGS. 2C to 2F and the description thereof. The package-to-package connections 150g will be described in more detail below. The description of the other components will be understood with reference to FIG. 2A and the description thereof.

Referring to FIG. 2H, the laminated structure 100H of semiconductor packages includes a lower semiconductor package 105L, an upper semiconductor package 105U, and an inter-package connection 105R electrically connecting the lower and upper semiconductor packages 105L and 105U. (150h). The package connection portions 150h include lower connection portions 160h, intermediate connection portions 170h, intermediate bonding portions 175h, and package bumps 190h. The lower connection portions 160h, the intermediate connection portions 170h, the intermediate bonding portions 175h, and the package bumps 190h may be understood with reference to FIGS. 2B to 2G and the description thereof. The package-to-package connections 150h will be described in more detail below. The description of the other components will be understood with reference to FIG. 2A and the description thereof.

3A and 3B are longitudinal cross-sectional views conceptually showing laminated structures of semiconductor packages including chip connection portions according to the technical idea of the present invention. 3A, a laminate structure 200a of semiconductor packages includes a lower semiconductor package 205L including a lower semiconductor chip 215L including chip connection portions 281, an upper semiconductor package 205U, And package interconnections 250 for electrically connecting the upper semiconductor packages 205L and 205L. The lower semiconductor package 205L includes a lower molding material 230La that does not cover the upper surface of the lower semiconductor chip 215L. The chip connection portions 281 may be formed on the upper surface of the lower semiconductor chip 215L and may be physically or electrically connected to a lower surface of the upper package substrate 210U. The chip connection portions 281 may electrically connect the lower semiconductor chip 215L and the upper semiconductor chip 215U. The lower semiconductor chip 215L may include TSVs 280 (through silicon via) that pass through the body vertically. The TSVs 280 may electrically couple the chip bumps 220 to the chip connections 281. Although the chip connections 281 and the chip bumps 220 are shown as being aligned in the figure, they need not necessarily be aligned. In addition, re-wiring lines may be formed between the chip bumps 281 and the TSVs 280. The rewires will be described in more detail below.

The chip connection portions 281 may transmit valid signals and the package connection portions 250 may transmit a supply voltage, a ground voltage, and / or a test signal. The valid signals may refer to a clock signal, a command signal, and / or a data signal. Conversely, the chip connection portions 281 may transmit a supply voltage or a ground voltage, and the inter-package connection portions 250 may transmit valid signals. In another embodiment, the chip connections 281 may carry a ground voltage, and the inter-package connections 250 may transmit a supply voltage. In another embodiment, when the lower semiconductor chip 215L is a logic device and the upper semiconductor chip 215U is a memory device, the chip connection portions 281 are connected to the shielding ground wirings of the lower semiconductor chip 215L the shielding ground interconnections and the ground wiring of the upper semiconductor chip 215U can be electrically connected. The shielding ground wirings may be disposed between the signal transmission lines in the logic elements. The shielding ground wirings may prevent or reduce interference of electrical signals transmitted through the signal transmission lines. In this case, the supply voltage and the ground voltage may be transmitted through the package-to-package connections 250. As a result, the chip connection units 281 and the package connection units 250 may perform different signal transfer functions.

The chip connection portions 281 may be formed of a solder material. Other, unexplained components will be understood with reference to Figures 2a to 2h and the description thereof. The package-to-package connections 250 are illustratively shown in FIG. 2A. Accordingly, the inter-package connection units 250 can be extended to any one of the inter-package connection units 150b-150h shown in FIGS. 2B to 2H.

3B, the stacked structure 200b of semiconductor packages includes chip connection portions 281, a lower semiconductor package 205L including a lower semiconductor chip 215L, an upper semiconductor package 205U, Package connecting portions 250 for electrically connecting the semiconductor packages 205L and 205L and the lower semiconductor package 205L includes a lower molding material 230Lb covering the upper surface of the lower semiconductor chip 215L, . The chip connecting portions 281 may be surrounded by the lower molding member 230Lb and / or the side portions.

FIG. 4 is a conceptual illustration of another application example of lamination structures of semiconductor packages according to the technical idea of the present invention. 4, a stacked structure 300 of semiconductor packages includes a lower semiconductor package 305L including a lower package substrate 310L and a lower semiconductor chip 315L, an upper semiconductor package 305U, Package connection portions 350 for electrically connecting the upper semiconductor packages 305L and 305U and the lower package substrate 310L and the lower semiconductor chip 315L are electrically connected through a bonding wire 340L Can be connected. The semiconductor packages 305L and 305U according to the present embodiment may each include a memory element. That is, the lower semiconductor chip 315L and the upper semiconductor chip 315U may be memory devices. In this embodiment, each of the package-to-package connections 350 may include a lower connection part 360 and an upper connection part 380. That is, at least two or more components may be stacked. In this case, the lower connection portions 360 may be formed to be smaller than the upper connection portions 380. Alternatively, the maximum height of the lower connection parts 360 may be lower than the upper surface of the lower semiconductor chip 315L. As described above, when the size of the lower connection portions 360 is relatively reduced and the size of the upper connection portions 380 is relatively increased, the size and arrangement of the package connection portions 350 can be reduced Can be improved.

The technical idea of the present invention described with reference to Fig. 4 can also be applied to the stacked structures 100b-100h, 200a-200b of various semiconductor packages described with reference to Figs. 2B to 3B. In other words, the various package connections 150a-150h, 250a-250b according to the inventive concept illustrated and described in FIGS. 2A-3B may include upper and lower components, respectively, The components may be formed lower than the upper surface of the lower semiconductor chips. The upper components may include upper connections 180a-180e, 280 or package bumps 190f-190h and lower components may include lower connections 160a-160b, 160d-160f, 160h, 260 The bottom connection portions 165c and 165g and the intermediate connection portions 170d-170e and 170h and / or the intermediate bonding portions 175e and 175g-175h. More specifically, when the maximum height of the lower components is lower than the height of the upper surface of the lower semiconductor chip 315L, the maximum height of the upper components relatively increases. As the upper components are formed higher, the process of forming the stacked structures 100b-100h, 200a-200b of the semiconductor packages can be stabilized. This will be described in more detail below.

5A to 5D are longitudinal cross-sectional views conceptually showing chip connecting portions and their connecting structures according to the technical idea of the present invention. In particular, it is conceptually shown that the chip connections are formed between the lower semiconductor chips and the upper package substrates, and the upper surface of the lower semiconductor chips is exposed. The various chip connections shown and described below may be similar in structure to the package-to-package connections shown in FIGS. 2A-2H. However, the size will be variously set according to the design standard.

Referring to FIG. 5A, the chip connection portions 281 may be formed as a single rectangular body between the lower semiconductor chip 215L and the upper package substrate 210L. The chip connections 281 may include solder material. As described briefly above, the side surface of the lower semiconductor chip 215L may be surrounded by the molding material 230L, and the upper surface of the lower semiconductor chip 215L may be exposed. The chip connection portions 281 may be electrically connected to the TSVs 280. The chip connection portions 281 and the TSVs 280 may be electrically connected to each other through the rewiring lines 279. The reordering lines 279 may be formed in the form of a pad, a bar, or a line in a plan view. The pad may electrically connect two or more of the chip pads 281 or the TSVs 280. The chip connections 281, reordering lines 279 and / or TSVs 280 shown in Figure 5a can be applied to the stacked structures 100a-100h of all the semiconductor packages shown in Figures 2A-2H . That is, the stacked structures 100a to 100h of all the semiconductor packages may further include the chip connection portions 281, the re-wiring lines 279, and / or the TSVs 280.

5B, chip connection portions 282 including lower chip connection portions 283 and upper chip connection portions 284 may be formed between the lower semiconductor chip 215L and the upper package substrate 210L have. The lower chip connection portions 283 and the upper chip connection portions 284 may be formed of a solder material. The lower chip connection portions 283 can be understood with reference to the lower connection portions 160a, 160b, 160d, 160e, 160f, and 160h shown in FIGS. 2A, 2B, 2D, 2E, 2F, or 2H. The upper chip connection portions 284 can be understood by referring to the upper connection portions 180a-180e shown in FIGS. 2A to 2E. Also in this embodiment, the rewiring lines 279 and the TSVs 280 can be further formed.

5C, chip connecting portions 285 including bottom chip connecting portions 286 and upper chip connecting portions 284 may be formed between the lower semiconductor chip 215L and the upper package substrate 210L have. The bottom chip connection portions 286 may be formed in a mesa shape or a column shape. The bottom chip connection portions 286 may be attached to one surface of the lower semiconductor chip 215L. The bottom chip connection portions 286 may be formed of metal. The bottom chip connections 286 can be understood with reference to the bottom connections 165c, 165d, 165e, 165g, 165h shown in Figures 2c, 2d, 2e, 2g or 2h. The upper chip connection portions 284 can be understood with reference to the upper connection portions 180a-180e and FIG. 5b shown in FIGS. 2A to 2E. Also in this embodiment, the rewiring lines 279 and the TSVs 280 can be further formed.

5D, chip connection portions 285 including lower chip connection portions 283 and chip connection bumps 288 may be formed between the lower semiconductor chip 215L and the upper package substrate 210L have. The lower chip connection portions 283 can be understood with reference to the lower connection portions 160a, 160b, 160d, 160e, 160f, and 160h shown in FIGS. 2A, 2B, 2D, 2E, 2F, . The chip connection bumps 288 may be formed of a metal, such as a stud, a stick, or a column. The chip connecting bumps 288 may be manufactured in a separate process and fixed to the upper package substrate 210U. The chip connection bumps 288 can be understood with reference to the package bumps 190f, 190g, 190h of Figures 2f, 2g and 2h. Also in this embodiment, the rewiring lines 279 and the TSVs 280 can be further formed.

FIGS. 6A to 6D are longitudinal cross-sectional views conceptually showing chip connecting portions of different shapes and their connecting structures according to the technical idea of the present invention. FIG. In particular, the chip connections are formed between the lower semiconductor chips and the upper package substrates, and the upper surface of the lower semiconductor chips is partially or wholly covered with the lower molding material. The various chip connections shown and described below are also applicable to the package connections 150a-150h and / or the chip connections 281, 282, 285, 287 shown in Figures 5A-5D shown in Figures 2A- ) Can be similar in structure. However, the size will be variously set according to the design standard.

Referring to Figs. 6A to 6D, referring to Figs. 5A to 5D, the lower molding material 230Lb may cover the upper surface of the lower semiconductor chip 215L. Accordingly, the chip connecting portions 281, 282, 285, and 287 may be partially or entirely covered with the lower molding material 230Lb. In other words, the chip connection portions 281, 282, 285, and 287 may be exposed from the lower molding material 230Lb at a lower portion and / or a side portion. 5A to 5D, the rewiring lines 279 and the TSVs 280 may be further formed in these embodiments.

7A to 7D are longitudinal cross-sectional views conceptually showing imaginary shapes of various connections of package lamination structures according to the technical idea of the present invention. The meaning of the virtual shapes means that the components are not formed actually, but are formed according to the respective manufacturing processes. Specifically, it may be a conceptual shape of various inter-package connections and / or chip connections before a reflow process is performed.

The various connection portions may refer to any one or any of the various package-to-package connections and chip connection portions shown in FIGS. 1A to 6D.

7A, the connection portion 50a includes a lower connection portion 60a and an upper connection portion 80a, and the upper connection portion 80a may have a larger volume than the lower connection portion 60a. Alternatively, the vertical height H1 of the upper connection part 80a may be greater than the vertical height H2 of the lower connection part 60a. Alternatively, the horizontal width D1 of the upper connection portion 80a may be greater than the horizontal width D2 of the lower connection portion 60a. The horizontal widths D1 and D2 may be understood as a diameter of the upper connection portion 80a and / or the lower connection portion 60a in a plan view or a transverse sectional view. Alternatively, the virtual radius or curvature (r1, radius or curvature) of the upper connection portion 80a may be formed to be larger than the imaginary radius or curvature r2 of the lower connection portion 60a. The lower connection portion 60a and the upper connection portion 80a may include a solder material. Accordingly, the lower connection portion 60a and the upper connection portion 80a may be formed by a soldering process, and the upper connection portion 80a and the lower connection portion 60a may be formed in a spherical or hemispherical shape.

7B, the connection portion 50b includes a lower connection portion 60b and an upper connection portion 80b. The upper connection portion 80b may have a larger volume than the lower connection portion 60b, The imaginary center C1 of the lower surface 60b can be located at the same level as the lower surface 10. The imaginary center C1 may be understood as the center of the imaginary radius or curvature r3 of the lower connection portion 60b. The lower connection portion 60b and the upper connection portion 80b may be formed of a solder material. In particular, the lower connection portion 60b may be hemispherical.

7C, the connection portion 50c includes a lower connection portion 60c and an upper connection portion 80c. The upper connection portion 80c may have a larger volume than the lower connection portion 60c, The hypothetical center C2 of the lower surface 60c can be located lower than the lower surface 10. The imaginary center C2 may be understood as the center of the imaginary radius or curvature r4 of the lower connection portion 60c.

7D, the connection portion 50d includes a lower connection portion 60d and an upper connection portion 80d. The upper connection portion 80d may have a larger volume than the lower connection portion 60d, The imaginary center C3 of the lower surface 60d can be located higher than the lower surface 10. [ The imaginary center C3 may be understood as the center of the imaginary radius or curvature r5 of the lower connection portion 60d.

In other words, the upper connection portions 80a-80d may be formed to be higher, wider, or larger than the lower connection portions 60a-60d in the embodiments of the present invention. The lower connection portions 60a-60d may be formed by a screen printing process or a soldering process. The upper connection portions 80a-80b may be formed by a soldering process. However, the process of connecting the upper connection portions 80a-80d and the lower connection portions 60a-60d may be performed in a via hole formed by a laser drilling process or the like. The via hole may be formed through a process of selectively removing a molding material or the like to expose a part of the surface of the lower connection portions 60a-60d. The laser drilling process may be a finer process that allows relatively fine processing than the screen printing process or the soldering process. Therefore, in order to precisely arrange the connecting portions 50a, a relatively elaborate laser drilling process should be more heavily used. The smaller the size of the lower connection portions 60a-60d, the smaller the contribution of the screen printing process and / or the soldering process. The larger the size of the upper connection portions 80a-80d, The contribution of the drilling process will increase. Therefore, the upper connection portions 80a-80d should be formed to be larger than the lower connection portions 60a-60d, which is a good method for forming the connection portions 50a-50d more precisely. Particularly, the upper connection portions 80a-80d must be filled with flux before the reflow process for connecting the lower connection portions 60a-60d and the upper connection portions 80a-80d. The reflow process can be performed stably when the surface of the upper connection portions 80a-80d is sufficiently filled with the solvent. That is, as the upper connection portions 80a-80d are larger, the upper connection portions 80a-80d can be sufficiently immersed in the flux. Therefore, it is preferable that the upper connection portions 80a-80d are formed as large as possible while minimizing the mutual separation distance. Generally, the upper package substrate 110U is not flat. The upper package substrate 110U is bent without maintaining the flatness while the semiconductor package manufacturing process is being performed. Therefore, if the upper connection portions 80a-80d can not be formed sufficiently large, the surface can not be sufficiently immersed in the flux. Therefore, it is a very important technological improvement that the upper connection portions 80a-80d are formed larger than the lower connection portions 60a-60d. This will be described again in the process of fabricating the stacked structures of the various upper semiconductor packages.

8A to 8J are conceptual diagrams illustrating actual shapes of various connection portions of the package lamination structures according to the technical idea of the present invention. The meaning of the actual shapes can be understood as meaning that the respective components are finally formed shapes. The various connection portions may refer to any one or any of the various package-to-package connections and chip connection portions shown in FIGS. 1A to 6D.

Referring to FIG. 8A, the connecting portion 51a includes a waist portion Wa and may be formed to be physically and / or electrically connected between the lower land 12a and the upper land 17a. The waist portion Wa may visually indicate a slender portion of the connection portion 51a. The waist portion Wa can virtually and / or visually distinguish the connection portion 51a from an upper part and a lower part. In other words, the waist portion Wa can divide the connecting portion 51a into an upper connecting portion 81a and a lower connecting portion 61a. The maximum width Da1 of the upper connection portion 81a may be greater than the maximum width Da2 of the lower connection portion 61a. The width Da3 of the waist portion Wa may be smaller than the maximum width Da2 of the lower connection portion 61a. The waist portion Wa may mean a portion having a minimum width Da3 existing between the maximum width Da2 of the lower connection portion 61a and the maximum width Da1 of the upper connection portion 81a have. The height Ha1 of the upper connection portion 81a may be defined as a height from the surface of the upper land 17a or the upper insulating portion 18a that partially covers the upper land 17a to the waist Wa And the height Ha2 of the lower connection portion 61a is defined as a height from the surface of the lower insulating member 13a that partially covers the lower land 12a or the lower land 12a to the waist Wa . The height Ha1 of the upper connection portion 81a may be greater than the height Ha2 of the lower connection portion 61a. Alternatively, the volume of the upper connection part 81a may be larger than the volume of the lower connection part 61a. In addition, the maximum width Da1 of the upper connection portion 81a may be located above the middle of the upper connection portion 81a. The waist Wa may not be formed horizontally, but it is assumed herein that the waist Wa is formed horizontally. The upper connection portion 81a and the lower connection portion 61a may be formed of a solder material in a spherical or hemispherical shape. Accordingly, the horizontal width Da1, Da2, Da3 may mean the diameter of the circle in a plan view or a cross-sectional view. In addition, the connection 51a may be a real shape of the inter-package connections 150a, 250 shown conceptually in Figures 2a, 3a, and 3b.

8B, the connecting portion 51b includes a waist portion Wb for separating the upper connecting portion 81b from the lower connecting portion 61b, and a virtual center C of the lower connecting portion 61b is connected to the lower It may be located lower than the surface of the land 61b. The case where the imaginary central point C of the lower connection portion 61b is located higher than the surface of the lower land 61b will be understood with reference to FIG. The maximum width Db1 of the upper connection portion 81b may be greater than the width Db2 of the waist portion Wb. The height Hb1 of the upper connection portion 81b may be greater than the height of the lower connection portion 61b.

8C, the connecting portion 51c includes a mesa bottom connecting portion 66c and a spherical upper connecting portion 81c, and a height Hc1 of the upper connecting portion 81c is set to a height of the bottom connecting portion 66c Hc2). The maximum width Dc1 of the upper connection portion 81c may be greater than the width Dc2 of the bottom connection portion 66c. A part of the upper surface of the mesa bottom connecting portion 66c may be exposed without being in contact with the upper connecting portion 81c.

8D, the connection portion 51d includes a spherical or hemispherical lower connection portion 61d, a mesa-shaped intermediate connection portion 71d, and a spherical upper connection portion 81d, and the height Hd1 of the upper connection portion 81d, May be greater than the height Hd2 of the intermediate connection portion 71d or the height Hd3 of the lower connection portion 61d. In addition, the height Hd1 of the upper connection portion 81d is formed to be larger than a height Hd2 + Hd3 of the height Hd2 of the intermediate connection portion 71d and the height Hd3 of the lower connection portion 61d . The maximum width Dd1 of the upper connection portion 81d may be greater than the width Dd2 of the bottom connection portion 66d. A part of the upper surface of the intermediate connection portion 71d may be exposed without being in contact with the upper connection portion 81d. A portion of the lower portion of the side surface of the intermediate connection portion 71d may be covered with the lower connection portion 61d.

Referring to FIG. 8E, the connecting portion 51e includes a lower connecting portion 61e, an intermediate connecting portion 71e, an intermediate bonding portion 76e, and an upper connecting portion 81e. The upper connecting portion 81e and the intermediate adhering portion 76e can be virtually or visually identified based on the waist We. The maximum width of the upper connection portion 81e may be greater than the maximum width of the intermediate bonding portion 76e. The maximum width of the intermediate bonding portion 76e may be greater than the width of the waist portion We. The heights of the respective components can be set variously. For example, although the top connection portion 81e is illustrated as having the largest height, it need not necessarily be. As the connection portion 51e is formed into a multi-layered structure, the relative height, width, or size of each component can be variously applied.

Referring to FIG. 8F, the connection portion 51f includes a lower connection portion 61f and a bump portion 91f. The bump portion 91f may be formed of a metal material in the form of a stud or a column. The height Hf1 of the bump portion 91f may be higher than the height Hf2 of the lower connection portion 61f. A portion of the lower portion of the side surface of the bump portion 91f may be covered with the lower connection portion 61e. The lower connection portion 61e may be formed in a spherical or hemispherical shape. The imaginary central point of the lower connection portion 61e may be located above or below the surface of the lower land 12f. This can be understood in more detail with reference to Figures 8A and 8B.

Referring to Fig. 8G, the connection portion 51g includes a bottom connection portion 66g, an intermediate connection portion 76g, and a bump portion 91f. The height Hg1 of the bump portion 91g may be greater than the height Hg2 of the intermediate adhering portion 76g or the height Hg3 of the bottom connecting portion 66g. The connecting portion 51g may be understood in more detail with reference to Figs. 8C to 8F.

Referring to Fig. 8H, the connection portion 51h includes a lower connection portion 61h, an intermediate connection portion 71h, an intermediate bonding portion 76h, and a bump portion 91h. The height Hh1 of the bump portion 91h is greater than the height Hh2 of the intermediate adhering portion 76h, the height Hh3 of the intermediate connecting portion 71h or the height Hh4 of the lower connecting portion 61h . The height Hh2 of the intermediate adhering portion 76h, the height Hh3 of the intermediate connecting portion 71h and / or the height Hh4 of the lower connecting portion 61h may be variously set according to a design rule. . More specific shapes and descriptions of the respective components can be understood in more detail with reference to Figs. 8C to 8G.

8I, the connection portion 51i includes a waist portion Wi for separating the upper connection portion 81i from the lower connection portion 61i, and the lower connection portion 61i includes the flat portions SWi on the side wall. can do. The flat portions SWi may be formed as a part of the side wall of the lower connection portion 61i. The flat portions SWi may extend to a lower end of the lower connection portion 61i.

The upper lands 17a-17h shown in Figures 8a-8i can be part of the upper packages 105U, 205U shown in Figures 2a-2h, 3a and / or 3b and the lower lands 12a- May be part of the lower packages 105L, 205L or lower semiconductor chips 115L, 215L.

FIGS. 9A to 9I are conceptual diagrams showing the shapes of various connection portions and via holes of the package laminate structures according to the technical idea of the present invention. 9A, the connection portion 52a includes a lower connection portion 62a and an upper connection portion 82a. The upper connection portion 82a includes a via hole Va (see FIG. 9A) for exposing a part of the surface of the lower connection portion 62a . The width Dva of the lowermost end Vla of the via hole Va may be smaller than the maximum width Dla of the lower connection portion 62a. A gap Ga may be formed between the via hole Va and the waist Wa.

9B, the connection portion 52b includes a lower connection portion 52b and an upper connection portion 82b. The upper connection portion 82b includes a via hole (not shown) for exposing most or all of the surface of the lower connection portion 62b, (Vb). The lower connection portion 62b may include flat portions SWb on the side wall. The width Dvb of the lowermost end of the via hole Vb may be larger than the width Dlb of the lowermost end of the lower connection portion 62b. Therefore, a gap Gbl may be formed between the via hole Vb and the lowermost end of the lower connection portion 62b.

9C, the connection portion 52c includes a lower connection portion 52c and an upper connection portion 82c. The upper connection portion 82c includes a via hole (not shown) that exposes the entire upper surface of the lower connection portion 62c, Vc. The lower connection portion 62c may include flat portions SWc on the side wall and the flat portions SWc may extend to the lower surface 23c.

Gb, and Gc are formed between the waist portions Wa, Wb, and Wc of the connection portions 52a, 52b, and 52c and the side walls of the via holes Va, Vb, and Vc, respectively, May be formed. The via-holes Va, Vb, and Vc may be formed such that the sidewalls thereof are inclined in a shape having a wide upper portion and a narrower lower portion. The tilted angle of the sidewalls of the via-holes Va, Vb, Vc may be set differently. For example, 10 [deg.] To 30 [deg.]. The angles at which the sidewalls of the via-holes Va, Vb, Vc are inclined will be set in consideration of the interval, pitch, and the like from the adjacent connection portions. The via holes Va, Vb, and Vc vertically penetrate the molding materials 32a, 32b, and 32c and extend to the upper and / or side surfaces of the lower connection portions 62a, 62b, and 62c, 23b, and 23c, respectively.

9D, the connecting portion 52d includes a mesa-shaped connecting portion 67d and an upper connecting portion 82d, and the upper connecting portion 82d is formed to expose a part of the surface of the mesa-shaped connecting portion 67d. And may be formed in the via hole Vd. The lowermost width Dvd of the via hole Vd may be formed to be larger than the horizontal width Dmd of the mesa-shaped connecting portion 67d. A gap Gd may be formed on a part of the surface of the mesa-shaped connecting portion 67d.

9E, the connecting portion 52e includes a mesa-shaped connecting portion 67e and an upper connecting portion 82e, and the upper connecting portion 82e includes a via formed to expose a part of a side surface of the mesa- And can be formed in the hole Ve. The width Dve of the lowermost end of the via hole Ve may be equal to the horizontal width of the mesa-shaped connecting portion 67e. A gap Ge may be formed between a part of the side surface of the mesa-shaped connecting portion 67e and the sidewall of the via hole Ve.

9F, the upper connection portion 82f includes a mesa-shaped connection portion 67f and an upper connection portion 82f, and the upper connection portion 82f is configured to expose the entire side surface of the mesa-shaped connection portion 67f And may be formed in the via-hole Vf formed. The via hole Vf may expose a part of the upper portion of the lower connection portion 62f. A gap Gf may be formed between a part of the side surface of the mesa-shaped connecting portion 67f and the side wall of the via hole Vf.

In FIGS. 9D to 9F, the via-holes Vd, Ve, and Vf may be formed such that the side walls are inclined in a wide upper portion and a narrow lower portion. The via holes Vd, Ve, and Vf vertically penetrate the molding materials 32d, 32e, and 32f and expose the upper and side surfaces of the mesa type connecting portions 67d, 67e, and 67f, respectively, .

9G, the connecting portion 52g includes a lower connecting portion 62g, a meshing connecting portion 67g, an intermediate connecting portion 77g, and an upper connecting portion 82g, Hole Vg that exposes a part of the surface of the gate electrode 77g. A gap Gg may also be formed between a part of the surface of the intermediate connection part 77g and a sidewall of the via hole Vg.

9H, the connecting portion 52h includes a lower connecting portion 62h, a meshing connecting portion 67h, an intermediate connecting portion 77h, and an upper connecting portion 82h, and the upper connecting portion 82h includes the mesa- Hole Vh that exposes a part of the surface of the connection portion 67h. The via hole Vh may further expose a part of the side surface of the mesa-shaped connection portion 67h. A gap Gh may also be formed between a part of the surface of the mesa-shaped connecting portion 67h and the side wall of the via hole Vh.

9i, the connecting portion 52i includes a lower connecting portion 62i, a meshing connecting portion 67i, an intermediate connecting portion 77i, and an upper connecting portion 82i, (Vi) that exposes a part of the surface of the gate electrode 62i. A gap Gi may also be formed between a part of the surface of the lower connection part 62i and the sidewall of the via hole Vi.

9G to 9I, the via-holes Vg, Vh, and Vi may be formed such that the sidewalls are inclined in a shape having a wide upper portion and a narrower bottom portion. The via holes Vg, Vh and Vi vertically penetrate the molding materials 32g, 32h and 32i and partly or wholly of the surface of the intermediate connection part 77h and part of the surface of the mesa type connection part 67h Or all of the surface of the lower connection portion 62h. The gaps Gbl and Ga-Gi may mean an air gap.

Hereinafter, methods of forming a stacked structure of semiconductor packages according to various embodiments according to technical aspects of the present invention will be described. 10A to 10F are vertical cross-sectional views for explaining a method of forming a top package in a method of forming a laminated structure of semiconductor packages according to the technical idea of the present invention.

Referring to FIG. 10A, an upper package substrate 110U including upper lands 155U and wire pads 145 is prepared. The upper lands 155U and the wire pads 145 may be electrically connected. The upper lands 155U and the wire pads 145 may be formed using a screen printing process, a deposition process, an adhering process, or a plating process.

Referring to FIG. 10B, upper semiconductor chips 115U are mounted on the upper package substrate 110U. An insulating adhesive may be interposed between the upper package substrate 110U and the upper semiconductor chips 115U. The upper semiconductor chips 115U may include bonding pads 135. [

Referring to FIG. 10C, the bonding pads 135 and the wire pads 145 may be electrically connected to each other through the bonding wires 140.

Referring to FIG. 10D, an upper molding material 130U covering the upper semiconductor chips 110U is formed and separated for each of the upper semiconductor chips 105U. The upper molding material 130U may be made of epoxy resin or polyimide. The upper semiconductor chips 105U may be separated by a sawing process or a cutting process.

Referring to FIG. 10E, the upper semiconductor package 105U may be turned over and the upper connection part 180 may be formed on the upper lands 155U.

In an application embodiment of the present invention, package bumps 190 may be formed on the upper lands 155U with reference to FIG. 10E or 10F, the upper semiconductor package 105U according to the technical idea of the present invention can be completed.

11A to 11J are longitudinal cross-sectional views for conceptually illustrating a method of forming a laminated structure of semiconductor packages according to an embodiment of the technical idea of the present invention. Referring to FIG. 11A, the lower lands 155L are formed on the lower package substrate 110L. The lower lands 155L may be formed using a screen printing technique. Alternatively, it may be formed using a deposition technique, a plating technique, an ink jet technique, or the like. At this time, the chip bump lands 121 may be formed simultaneously or in another process. That is, the lower lands 155L and the chip bump lands 121 are formed on the lower package substrate 110L.

Referring to FIG. 11B, chip bumps 120 are formed on the lower package substrate 110L. The chip bumps 120 may be formed using a screen printing technology process, an inkjet process, or a soldering process. The chip bumps 120 may be electrically connected to the chip bump lands 121, respectively.

Referring to FIG. 11C, lower connection portions 160 are formed on the lower lands 155L. The lower connection portions 160 may be formed using a screen printing technique, an ink jet technique, or a soldering technique. The process of forming the chip bumps 120 and the process of forming the lower connection portions 160 may be performed simultaneously. That is, the chip bumps 120 and the lower connection portions 160 may be formed at the same time. Although the figure shows that the chip bumps 120 and the lower lands 160 may have similar surface heights, this is exemplary. The lower lands 160 may be formed sufficiently higher than the chip bumps 120. The chip bumps 120 and the lower lands 160 may have the same height as the chip bumps 120 and the lower lands 160. That is, The different heights of the two components can be understood as meaning that the two components are formed through different processes.

Referring to FIG. 11D, the lower semiconductor chips 115L are mounted on the chip bumps 120. FIG. The lower semiconductor chips 115L may have a flip chip design and may be logic devices. The order of the process of forming the lower connection portions 160 and the process of mounting the lower semiconductor chips 115L may be changed. For example, when the lower connection portions 160 are formed using a screen printing technique or the like, the lower semiconductor chips 115L may be mounted before the lower semiconductor chips 115L are mounted. However, if the lower connection portions 160 are formed using a soldering technique or the like, they may be performed after the lower semiconductor chips 115L are mounted.

Referring to FIG. 11E, a molding control film 135 is formed on the lower semiconductor chips 115L. The molding control film 135 may be formed in close contact with the upper surface of the lower semiconductor chips 115L. The molding control film 135 can secure a space with the lower package substrate 110L. In addition, the molding control film can secure a space with respect to the surface of the lower connection portions 160. The molding control film may be a tape of various materials such as cellulose, acetate, polyvinyl, polyurethane or the like.

Referring to FIG. 11F, a lower molding material 130L is filled in a space between the lower package substrate 110L and the lower package substrate 110L. The lower molding material 130L may be formed to cover the lower connection portions 160, cover the side surface of the lower semiconductor chip 115L, and fill the lower region of the molding control film 135. [ The lower molding material 130L may be formed around the chip bumps 120 only. In other words, it may be filled only between the lower package substrate 110L and the lower semiconductor chips 115L. That is, the side surfaces of the lower semiconductor chips 115L may be exposed to air. In this case, the lower molding material 130L may be an insulating adhesive. Alternatively, the lower side of the lower semiconductor chips 115L may be surrounded by the molding material, and the upper side of the lower semiconductor chips 115L may be exposed to the air. At this time, the molding material 130L may cover the surface of the lower connection parts 160. [ In other words, the molding material 130L can be semi-peeled in the space between the lower package substrate 110L and the lower package substrate 110L.

Referring to FIG. 11G, the molding control film is removed, and a laser drilling process is performed to expose the surface of the lower connection portions 160. [ The laser drilling process is a process of selectively removing the lower molding material 130L and may be a process of forming openings O for exposing all or a part of the surface of the lower connection parts 160. [ The height from the uppermost surface of the lower connection portions 160 to the upper surface of the molding material 130L is greater than the height from the surface of the lower package substrate 110L to the uppermost surface of the lower connection portions 160 Can be largely formed. Alternatively, the space of the openings O may be formed larger than the volume of the lower connection portions 160. When the openings O are regarded as via holes, the inner space of the via hole may be formed to be larger than the volume of the lower connection portions 160. [ The meaning of the height may mean either a vertical height, a horizontal maximum width, or a maximum diameter.

Referring to FIG. 11H, solder balls 125 are formed on the lower surface of the lower package substrate 110L. The solder balls 125 may be electrically connected to the chip bumps 120. The solder balls 125 may be formed through a soldering process. The order of the laser drilling process and the process of forming the solder balls 125 may be changed.

Referring to FIG. 11I, the lower package substrate 110L and the molding material 130L are separated into a single lower package 105L. The separation process may be a sawing process, a drilling process, a cutting process, or the like.

Referring to FIG. 11J, the upper connections 180 of the upper semiconductor package 105U, shown with reference to FIG. 10E, are dipped in solder flux F in the vessel t. In this process, as shown at the left and right ends of the drawing, the upper surface of the container t and the upper surface of the upper package substrate 110U can be brought close to or in contact with each other. The top surface of the container t may serve to determine the depth at which the top connection portions 180 are immersed in the flux. At this time, when the upper connection portions 180 are sufficiently large, the upper connection portions 180 can be sufficiently immersed in the solvent F. [ Further, as the upper connection part 180 is formed larger, the surface areas of the upper connection parts 180 immersed in the solder solvent will be averaged, and the surface areas thereof are physically and electrically connected to the lower connection part 160 It would be more appropriate. The size or the surface area of the upper connection part 180 may be more specifically the height of the upper connection parts 180 protruding from the surface of the upper package substrate 110U. According to the technical idea of the present invention, it is recommended that the upper connection portions 180 are formed to be larger. Therefore, the technical idea of the present invention can provide a more stable connection structure physically and electrically. Also, for example, the upper package substrate 110U may be a shape that is finely or noticeably warped. The upper package substrate 110U should ideally be flat, but is substantially unlikely to be formed completely flat. In this case, if the upper connection portions 180 are not formed sufficiently large, the upper connection portions 180 that can not be immersed in the flux may occur, or flux may be applied to the surface of the upper package substrate 110U . Therefore, according to the technical idea of the present invention, when the upper connection part 180 is formed sufficiently large, an unstable factor of the process due to the warping of the upper package substrate 110U can be sufficiently solved.

Referring to FIG. 11K, the upper semiconductor package 105U and the lower semiconductor package 105L are laminated. The surface of the upper connection portions 180 is sufficiently filled with the solvent F, but is omitted in order to avoid complication of the drawing. In this process, the lower connection portions 160 and the upper connection portions 180 may be physically / electrically coupled and / or connected by heating and / or squeezing in the openings O. [ In this process, the manner in which the lower and / or the upper links 160 and 180 are coupled and / or connected has been previously described variously. It may be understood that the coupling is integrated.

Referring to FIG. 11L, the package bumps 190 of the upper semiconductor package 105U shown in FIG. 10F are immersed in the solder solvent F. FIG. Can be understood in more detail with reference to FIG. 11I and the explanations thereof. The subsequent process can be understood in more detail with reference to FIG. 11k. In addition, methods of forming semiconductor package lamination structures including chip connections may be fully understood with reference to methods of forming the semiconductor package lamination structures described above. On the other hand, in the soldering process, the solder material tends to be formed spherically due to surface tension. Thus, if it is described herein as spherical or hemispherical, or is shown as spherical or hemispherical in the figures, it can be understood that the components can be formed using a soldering process. In order to facilitate understanding of the technical concept of the present invention, each constituent element may be described or shown differently from the actual shape. In addition, those skilled in the art will appreciate that the lower connection 160 and the upper connection 180 can be applied in various forms from the drawings attached hereto and their descriptions You can expect it enough.

12A and 12B are conceptual diagrams of semiconductor modules including a stacked structure of semiconductor packages according to various embodiments of the technical concept of the present invention. 12A and 12B, the semiconductor modules 500a and 500b include module boards 510a and 510b, a plurality of semiconductor elements 520 mounted on the module boards 510a and 510b, At least one of the plurality of semiconductor elements 520 includes one of the stacked structures of the semiconductor packages according to the technical idea of the present invention. The module boards 510a and 510b may be PCBs. The semiconductor modules 500a and 500b may include a plurality of contact terminals 530 formed on the side surfaces of the module boards 510a and 510b. The contact terminals 530 may be electrically connected to the semiconductor elements 500a and 500b, respectively.

13 is a conceptual illustration of an electronic system including a stacked structure of semiconductor packages according to various embodiments of the technical concept of the present invention. 13, the electronic system 600 may include a control unit 610, an input unit 620, an output unit 630, and a storage unit 640 have. The control unit 610 may collectively control the electronic system 600 and the respective parts. The control unit 610 may be understood as a central processing unit or a central control unit, and may include the semiconductor module 500 according to the technical idea of the present invention. In addition, the controller 610 may include a stacked structure of semiconductor packages according to the technical idea of the present invention. The input unit 620 may send an electrical command signal to the controller 610. The input unit 620 may be an image reader such as a keyboard, a keypad, a mouse, a touch pad, a scanner, or various input sensors. The input unit 620 may include a stacked structure of semiconductor packages according to the technical idea of the present invention. The output unit 630 may receive an electrical command signal from the controller 610 and output the result of the processing by the electronic system 600. The output 630 may be a monitor, printer, beam emitter, or various mechanical devices. The output unit 630 may include a stacked structure of semiconductor packages according to the technical idea of the present invention. The storage unit 640 may be a component for temporarily or permanently storing an electrical signal to be processed by the controller 610 or an electrical signal processed by the controller 610. The storage unit 640 may be physically and electrically connected to or coupled to the controller 610. The storage unit 640 may be a semiconductor memory, a magnetic storage device such as a hard disk, an optical storage device such as a compact disk, or a server having other data storage functions. In addition, the storage unit 640 may include a stacked structure of semiconductor packages according to the technical idea of the present invention. The communication unit 650 receives an electrical command signal from the controller 610 and can send or receive an electrical signal to another electronic system. The communication unit 650 may be a modem, a wired transceiver such as an Ad-Card, a wireless transceiver such as a WiBro interface, or an infrared port. In addition, the communication unit 650 may include a stacked structure of semiconductor packages according to the technical idea of the present invention. The electronic system according to the technical idea of the present invention may be a computer, a network server, a networking printer or scanner, a wireless controller, a mobile communication terminal, an exchange, or any other electronic device having a programmed operation.

In addition, elements not labeled with reference numerals or denoted by reference numerals in the drawings may be easily understood from the other drawings and the description thereof, and the names and functions thereof.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of illustration, You can understand that you can. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

100, 200, 300: laminated structure of semiconductor packages
105, 205, 305: semiconductor package
110, 210 and 310: package substrate
115, 215, and 315: semiconductor chips
120, 220, 320: chip bump
121: Chip bump land
125, 225, 325: solder balls
130, 230, 330: Molding material
135, 235, 335: bonding pads
140, 240, 340: bonding wire
145, 245, 345: wire pads
150, 250, 350: package-to-package connection
155, 255, 355: upper and lower lands
160, 260, 360: Lower connection
165: bottom connection 170: intermediate connection
175: intermediate bonding portion 180: upper connection portion
190: package bump 279: rewiring structure
280: TSV 281: Chip connection
500: semiconductor module 510: module board
520: semiconductor package 530: contact terminal
600: electronic system 610:
620: input unit 630: output unit
640: storage unit 650: communication unit

Claims (10)

A lower package substrate, and
A lower semiconductor package including a lower semiconductor chip disposed on an upper surface of the lower package substrate;
An upper package substrate, and
An upper semiconductor package including an upper semiconductor chip disposed on an upper surface of the upper package substrate; And
And an inter-package connection unit connecting the lower package substrate and the upper package substrate,
The lower semiconductor package includes:
And a lower molding material surrounding the lower semiconductor chip and exposing an upper surface of the lower semiconductor chip,
The inter-
A lower connection portion having a first vertical height formed on an upper surface of the lower package substrate; And
And an upper connection formed on a lower surface of the upper package substrate and having a second vertical height greater than the first vertical height,
Wherein the lower molding material surrounds a part of a side wall of the upper connection portion. The method according to claim 1,
The inter-
And a waist portion which is a boundary portion between the lower connection portion and the upper connection portion,
The first vertical height is a distance from an upper surface of the lower package substrate to the waist, and
Wherein the second vertical height is a distance from a lower surface of the upper package substrate to the waist portion. The method according to claim 1,
Wherein the lower connection portion has a first horizontal maximum width and the upper connection portion has a second horizontal maximum width larger than the first horizontal maximum width. The method according to claim 1,
Wherein a radius or curvature of the upper connection portion is larger than a radius or a curvature of the lower connection portion. The method according to claim 1,
Wherein the lower connection portion has a spherical or hemispherical shape and includes a flat portion on the side wall. The method according to claim 1,
Wherein the lower molding material is in direct contact with the side wall of the upper connection portion and the upper surface of the lower molding material is located at a higher level than the upper surface of the lower connection portion. The method according to claim 1,
Wherein the upper semiconductor chip is larger in horizontal width than the lower semiconductor chip. The method according to claim 1,
Further comprising chip connecting portions electrically connecting the first conductive portions formed on the upper surface of the lower semiconductor chip and the second conductive portions formed on the lower surface of the upper package substrate on the upper surface of the lower semiconductor chip, Respectively. The method according to claim 1,
Wherein the lower connection portion has a mesa shape. delete
KR1020100052827A 2009-12-17 2010-06-04 Semiconductor Packages and Stack Structures of the Same and Methods of Fabricating the Same KR101685652B1 (en)

Priority Applications (7)

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US12/910,415 US8508954B2 (en) 2009-12-17 2010-10-22 Systems employing a stacked semiconductor package
CN2010105942754A CN102104035A (en) 2009-12-17 2010-12-17 Stacked semiconductor packages, methods of fabricating the same, and systems employing the same
US13/934,942 US9042115B2 (en) 2009-12-17 2013-07-03 Stacked semiconductor packages
US14/693,352 US20150228627A1 (en) 2009-12-17 2015-04-22 Stacked semiconductor packages, methods for fabricating the same, and /or systems employing the same
US15/241,452 US9978721B2 (en) 2009-12-17 2016-08-19 Apparatus for stacked semiconductor packages and methods of fabricating the same
US15/971,600 US10403606B2 (en) 2009-12-17 2018-05-04 Method of fabricating a semiconductor package
US16/448,392 US10593652B2 (en) 2009-12-17 2019-06-21 Stacked semiconductor packages

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KR1020090126345 2009-12-17

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US9030022B2 (en) * 2011-10-24 2015-05-12 Taiwan Semiconductor Manufacturing Company, Ltd. Packages and methods for forming the same
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US20080076208A1 (en) * 2006-09-27 2008-03-27 Yen-Yi Wu Method of making a semiconductor package and method of making a semiconductor device
US20080157328A1 (en) * 2006-12-27 2008-07-03 Nec Electronics Corporation Semiconductor device and method for manufacturing same

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US20080076208A1 (en) * 2006-09-27 2008-03-27 Yen-Yi Wu Method of making a semiconductor package and method of making a semiconductor device
US20080157328A1 (en) * 2006-12-27 2008-07-03 Nec Electronics Corporation Semiconductor device and method for manufacturing same

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