KR101658792B1 - Computing system and method - Google Patents

Abstract

A computing system in a multi-core or many-core environment is provided. For load balancing among tasks within a computing system, a plurality of tasks are distributed to cores in consideration of various variables such as the number of cores and hardware (H / W), bus structure, and memory size.

Description

[0001] COMPUTING SYSTEM AND METHOD [0002]

In a computing system in a multi-core or many-core processor environment, in order to increase performance scalably according to the number of cores, there is no need for an idle core to exist To a load balancing method that evenly allocates the load.

Stream processors are being used for processing multimedia data such as audio, video, and graphics. Recently, for low power and high performance, research and use of stream processors in multi-core or many-core environments capable of parallel processing of tasks are increasing.

In order to increase the performance of the multi-core or the manic core processor according to the number of cores, it is important to balance the load so that idle cores do not exist. If the number of cores increases, load balancing can not be done efficiently, and overall system performance improvement is not significant.

In particular, in the case of multimedia data processing, since the type and amount of data generated and processed according to time are variable, a system that can adaptively cope with such a situation is required.

For such load balancing, conventionally, a method of allocating tasks to idle cores by monitoring whether the cores are idle periodically has been used. However, this method is effective when the number of cores is relatively small, such as for a processor having two to eight cores, but is not effective for a large number of cores.

For example, if the number of cores is 16, 32, 64, 128, etc., control for processor load balancing, such as monitoring the status of each core and synchronizing between tasks, Because.

According to an aspect of the present invention, there is provided a computer program product including a task profiler for calculating a latency of each of a plurality of tasks to be processed, a dependency analyzing unit for analyzing dependencies between the plurality of tasks, A scheduler for performing software pipelining for the plurality of tasks using a plurality of cores and at least one piece of hardware information.

In this case, the plurality of jobs to be processed have a plurality of iterations.

Here, the scheduler calculates a minimum Initiation Interval (mII), which is a minimum cycle of a processing start interval between one of the plurality of interactions, with reference to the TDG, and the mII Can be used to find an optimal solution of task mapping where each event can be overlapped and map the plurality of tasks to the plurality of cores and at least one hardware using the optimal solution.

If the optimal solution is not found using the mII, the scheduler adds one cycle to the mII until it finds the optimal solution, finds the optimal solution using each cycle, May be used to map the plurality of jobs to the plurality of cores and at least one hardware.

According to an embodiment of the present invention, the scheduler maps the plurality of jobs to a plurality of cores and at least one hardware, and searches for the optimal solution by a heuristic search method.

The optimal solution may be a mapping combination of tasks maximizing the processing instruction cycle (IPC) of the computing system.

Meanwhile, the plurality of cores and the at least one hardware information may include at least one of a number of the plurality of cores and at least one hardware, an inner structure of the plurality of cores and at least one hardware, a topology of the plurality of cores and at least one hardware , An internal buffer size of the plurality of cores and at least one hardware.

According to another aspect of the present invention, there is provided a method for processing a task, the method comprising: calculating latency of each of a plurality of tasks to be processed; extracting a task dependency graph (TDG) by performing dependency analysis among the plurality of tasks; And performing software pipelining for the plurality of jobs using a plurality of cores and at least one piece of hardware information.

In a manic core processor environment, the load balancing between the cores is maximized, so the number of idle cores is minimized and thus the overall data processing speed is improved.

Figure 1 illustrates a computing system in accordance with an embodiment of the present invention.
2 illustrates an exemplary structure of multi-core and hardware in a processing unit in a computing system according to an embodiment of the present invention.
FIG. 3 illustrates exemplary pseudo code of an application source input to a computing system according to an embodiment of the present invention.
FIG. 4 shows a result of generating a task dependency graph (TDG) using the application source of FIG. 3 according to an embodiment of the present invention.
Figure 5 illustrates the result of performing software pipelining for task activity using the TDG of Figure 4 in accordance with one embodiment of the present invention.
6 is a flow chart illustrating a computing method in accordance with an embodiment of the present invention.
Figure 7 is a flow chart detailing software pipelining steps in a computing method according to an embodiment of the present invention.

Hereinafter, some embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to or limited by the embodiments. Like reference symbols in the drawings denote like elements.

Figure 1 illustrates a computing system 100 in accordance with one embodiment of the present invention.

The computing system 100 includes a processing unit 140 in a multi-core or many-core (collectively, multicore) environment. The processor 140 may include a plurality of cores capable of processing tasks in parallel and may also include at least one dedicated hardware or a fixed hardware.

In a processor of a multicore environment, in order to maximize utilization of resources, it is required to maximize parallel processing through appropriate scheduling of tasks.

Conventional software pipelining can be used to optimize the parallelism between instructions (Arithmetic-Logic Units, ALUs) or other Function Units (FUs) ) This is a method for parallel processing by appropriately mapping emitters.

According to an embodiment of the present invention, this software pipelining technique is utilized to parallelize tasks among a plurality of cores in a multicore environment.

When the application source code is input, the task profiler 110 analyzes the source code and calculates the processing time, i.e., latency, according to the types of tasks to be processed.

The application source code analyzed in the present embodiment includes a task interruption. That is, a unit code including a plurality of tasks must be repeated through a loop or for statement.

When the task latency is analyzed by the task profiler 110, the task analyzer 120 calculates a Task Dependency Graph (TDG), taking into account the dependency between tasks in the unit code having the mutation, . According to this TDG, a dependency can be grasped on which task can be processed after a task is processed. For this process, the source code can be converted into assembly language and analyzed.

Then, the scheduler 130 calculates a minimum initialization interval (mII) for allowing a one-time transition and a next one to be performed in an overlapping manner, taking into account task variation, Find the optimal solution of Task Mapping.

The optimal solution to this task mapping is a mapping combination that can maximize the task per cycle (TPC), which is a task to be processed per cycle. And, the search for such an optimal solution can be performed by a heuristic search.

If no optimal solution is found in mII, the scheduler 130 increases the initiation interval (II) by one cycle and then finds the optimal solution again. In this way, II is incremented by one cycle until the optimal solution is found, and the optimal solution is found.

When an II with the optimal solution is found, the scheduler 130 maps the tasks to the multicore and dedicated hardware using the optimal solution, and completes the task scheduling.

Then, the processing unit 140 processes the task by processing the task according to the scheduler 130 scheduling.

The operation of the task profiler 110, the task analyzer 120 and the scheduler 130 will be described in more detail below with reference to FIG.

2 illustrates an exemplary structure of multicore and hardware in processing unit 140 in a computing system according to an embodiment of the present invention.

In this embodiment, the processing unit 140 includes four cores 210, 220, 230 and 240, four dedicated hardware 251, 252, 253 and 254 for ROP (ROP), a dedicated hardware BMU (Batch Management Unit) 260 and a fragment generation hardware FG (Fragment Generation)

The cores 210, 220, 230 and 240 and some of the hardware 253, 254, 260 and 270 may have a buffer therein and some of the hardware 251 and 252 may not have a buffer .

The descriptor of this hardware structure is used when the scheduler 130 of FIG. 1 performs task mapping.

FIG. 3 illustrates an exemplary pseudo code 300 of unit codes to be processed during a plurality of occurrences within an application source input to a computing system according to an embodiment of the present invention.

In this embodiment, the numerical code 300 is intended to be treated as a 100-time variation. The capital code 300 includes operations such as BMU, VS (Vertex Shader), FG, PS (Pixel Shader), and ROP.

The numeric code 300 is analyzed by the task profiler 110. In this embodiment, the latency of the BMU is 1, the latency of VS is 2, the latency of PS is 3, the latency of FG is 1, Is assumed to be 1.

These latencies are analyzed by the task profiler 110.

2, the BMU, FG and ROP are processed by dedicated hardware, and the remaining VS, PS can be processed by the core 210, 220, 230 or 240.

On the other hand, in the job dependency, the VS can be processed only if the BMU in the capitalization code 300 is executed twice. And FG can only be processed if two VSs are processed.

Also, the PS is processed twice, one after the FG process, and one time after the PS process. The ROP is also processed twice, once the PS is processed, and once for the ROP.

FIG. 4 illustrates a result of generating a Task Dependency Graph (TDG) 400 using the application source of FIG. 3 according to an embodiment of the present invention.

As described above, tasks have dependencies, and these dependencies can be represented by a graph structure.

As described above, the task analyzer 120 can process the two VSs in parallel after the BMU process, the FG can be processed only when both of the VSs are processed, the two PSs can be processed in parallel after the FG process, After each PS process, the TDG 400 expresses that two ROPs can be processed in parallel and provides them to the scheduler 130.

Figure 5 illustrates the result of performing software pipelining for task activity using the TDG of Figure 4 in accordance with one embodiment of the present invention.

The scheduler 130 uses the latency of each task provided by the task profiler 110, the TDG provided by the task analyzer 120, and the configuration information Descriptor of the cores and hardware described in FIG. 2, Maps to cores and hardware.

In this process, the scheduler uses the software pipeline technique described above.

First, the scheduler 130 finds a minimum start interval mll (minimum Initiation Interval) for one event and the next event to be processed in an overlapping manner.

Such mII can be determined by referring to the structure of the hardware, the kind of work, and the like, and can be understood at a normal knowledge level of the software pipeline technique.

When mII is found, the scheduler 130 determines whether the mII can find an optimal solution among the combinations that map the tasks to each of the cores or dedicated hardware.

Here, BMU, FG, and ROP with dedicated hardware are mapped to corresponding dedicated hardware, respectively, and the remaining operations, VS and PS, are appropriately mapped to the four cores.

If the optimal solution can not be found using this mII, then the II (Initiation Interval) is incremented by 1, and it is searched again. If the optimal solution is found through this process, II is determined as the final II.

In the task mapping optimal solution of this embodiment, the final II 510 is 3.

Then, two BMU1s in the first transition are placed on dedicated hardware, and two VS1s are mapped to core 3 and core 4, respectively. Then, after VS processing, FG1 is processed in dedicated hardware, and two PS1s are mapped to be processed in cores 1 and 2 in parallel.

Then, using the result, two ROP1s are mapped to ROP1 and ROP2 for parallel processing.

On the other hand, as shown, while VS1 is being processed in core 4, BMU2 of the second transition is mapped to be processed in dedicated hardware.

And while FG1 is being processed on dedicated hardware, VS2 of the second transition is mapped to be processed on Core 4.

In this way, software pipelining is performed that minimizes idle cores or idle hardware and overlaps emulation.

Observing the steady state section 520 includes tasks belonging to different mutations, but in section 520 there are two BMUs, two VSs, two FGs, two PSs, two ROPs It includes all 10 tasks that make up a transaction.

Thus, one transaction that originally took 10 cycles would take only 3 cycles in each of the steady state intervals.

Thus, Task Per Cycle (TPC), which is the throughput per cycle, has been improved from 1 (= 10 Tasks / 10 Cycles) to 3.3 (= 10 Tasks / 3 Cycles) without such software pipelining.

Therefore, parallel processing is improved 3.3 times. Of course, there is no complete overlap at the beginning before entering the steady state and at the end after the transition, but this is only negligible as the number of emissions increases.

6 is a flow chart illustrating a computing method in accordance with an embodiment of the present invention.

In step S610, the source code of the application is input. As described above, the application source code includes a unit of work having a plurality of mutations.

According to the computing method according to an embodiment of the present invention, in such a transaction processing, the parallel processing efficiency of a given multicore and a plurality of hardware is maximized.

Then, in step S620, the task profiler 110 obtains the processing latency of each of a plurality of jobs included in one transaction. This process is as described above with reference to Figs.

In step S630, the task analyzer 120 analyzes the dependency of each of a plurality of tasks included in one of the transactions to generate a TDG. The generation process of TDG and its exemplary results are as described above with reference to FIG.

Then, in step S640, the scheduler 130 performs software pipelining for a plurality of occurrences, referring to the operation latency, the TDG, and the descriptors of the multicores and hardware.

The software pipelining process will be described in more detail below with reference to FIG.

Thus, when software pipelining is performed, the entire worker movement is scheduled, and the processing unit 140 processes the work according to the schedule.

Figure 7 is a flow chart detailing software pipelining steps in a computing method according to an embodiment of the present invention.

In step S710, the mII of the task variation is calculated. The mII is determined by the scheduler in consideration of hardware structure, latency of operations, data loading / store cycle, and the like. The mII determination is as described above with reference to Fig.

Then, in step S720, the scheduler searches for an optimal solution of the task mapping using mII. This search process may be a heuristic search as described above.

Meanwhile, according to an embodiment of the present invention, the optimal solution may be defined as a task mapping combination capable of maximizing the TPC, which is the task throughput per cycle, according to the task mapping.

In step S730, it is determined whether the optimal solution is derived. If the optimal solution is derived, the scheduler determines the task mapping using the optimal solution in step S750 and schedules the entire work shift.

However, if it is determined in step S730 that the optimal solution has not been derived, the process of searching for the optimal solution is repeated by increasing II by 1 in step S740.

Through this process, a software pipelining process similar to the embodiment of FIG. 5 is performed. In the multicore environment, the idle time of each of the cores and / or the dedicated hardware can be minimized, have.

The embodiments of the present invention described above are systematic and efficient as compared with the method of allocating jobs when an idle core is detected while monitoring idle cores according to a conventional method. Also, the control for idle core monitoring and task allocation is not complicated.

The method according to an embodiment of the present invention can be implemented in the form of a program command which can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, and the like, alone or in combination. The program instructions recorded on the medium may be those specially designed and constructed for the present invention or may be available to those skilled in the art of computer software. Examples of computer-readable media include magnetic media such as hard disks, floppy disks and magnetic tape; optical media such as CD-ROMs and DVDs; magnetic media such as floppy disks; Magneto-optical media, and hardware devices specifically configured to store and execute program instructions such as ROM, RAM, flash memory, and the like. Examples of program instructions include machine language code such as those produced by a compiler, as well as high-level language code that can be executed by a computer using an interpreter or the like. The hardware devices described above may be configured to operate as one or more software modules to perform the operations of the present invention, and vice versa.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. This is possible.

Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined by the equivalents of the claims, as well as the claims.

100: Computing System
110: Task Profiler
120: Task Analyzer
130: Task Scheduler
140:

Claims (15)

A task profiler for calculating a latency of each of a plurality of tasks to be processed;
A task analyzer for analyzing dependency between the plurality of tasks and extracting a task dependency graph (TDG); And
A scheduler that performs software pipelining for the plurality of jobs using a plurality of cores and at least one piece of hardware information,
Lt; / RTI >
Wherein the plurality of jobs to be processed have a plurality of iterations,
The scheduler comprising:
Calculating a minimum initiation interval (mII), which is a minimum cycle of a processing start interval between one of the plurality of interactions, with reference to the TDG,
And finds an optimal solution of the task mapping in which each of the mutations can be overlapped using the mII. delete The method according to claim 1,
The scheduler comprising:
And using the optimization solution to map the plurality of tasks to the plurality of cores and at least one hardware. The method of claim 3,
The scheduler comprising:
If the optimal solution is not found using the mII, one cycle is added to the mII until the optimal solution is found, and the optimum solution is found using each cycle,
And using the optimization solution to map the plurality of tasks to the plurality of cores and at least one hardware. The method of claim 3,
The scheduler comprising:
And maps the plurality of jobs to a plurality of cores and at least one hardware and finds the optimal solution by a heuristic search. The method of claim 3,
Wherein the optimization solution is a mapping combination of tasks that maximizes a processing task cycle (TPC) of the computing system. The method according to claim 1,
The plurality of cores and at least one hardware information,
A plurality of cores and at least one hardware, an inner structure of the plurality of cores and at least one hardware, a topology of the plurality of cores and at least one hardware, an inner buffer size of the plurality of cores and at least one hardware , ≪ / RTI > Calculating a latency of each of a plurality of Tasks to be processed;
Extracting a task dependency graph (TDG) by performing dependency analysis between the plurality of tasks; And
Performing software pipelining for the plurality of jobs using a plurality of cores and at least one piece of hardware information
Lt; / RTI >
Wherein the plurality of jobs to be processed have a plurality of iterations,
Calculating a minimum Initiation Interval (mII), which is a minimum cycle of a processing start interval between one of the plurality of interactions, with reference to the TDG; And
A step of finding an optimal solution of the task mapping in which each of the mutations can be overlapped using the mII
Lt; / RTI > delete 9. The method of claim 8,
Wherein performing the software pipelining comprises:
Mapping the plurality of jobs to the plurality of cores and at least one piece of hardware using the optimal solution
Lt; / RTI > 11. The method of claim 10,
Wherein performing the software pipelining comprises:
If the optimal solution is not found using the mII, one cycle is added to the mII until the optimum solution is found, and the optimal solution is found using each cycle
Further comprising the steps of: 11. The method of claim 10,
Wherein performing the software pipelining comprises:
And mapping the plurality of jobs to a plurality of cores and at least one hardware and finding the optimal solution by a heuristic search. The method of claim 10, wherein
Wherein the optimization solution is a mapping combination of tasks maximizing a processing TPC (task per cycle) of a computing system on which the computing method is executed. 9. The method of claim 8,
The plurality of cores and at least one hardware information,
A plurality of cores and at least one hardware, an inner structure of the plurality of cores and at least one hardware, a topology of the plurality of cores and at least one hardware, an inner buffer size of the plurality of cores and at least one hardware Gt; a < / RTI > A computer-readable recording medium storing a program for carrying out the method according to any one of claims 8 to 14.

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