KR101649876B1 - Supply Voltage Level Shifter - Google Patents

Abstract

A voltage level shifter for use in a circuit having a multi-level supply voltage is disclosed. The voltage level shifter of the present invention may be applied to a circuit having multiple power supply voltages to transmit a signal of the first power supply voltage region to a second power supply voltage region higher than the first power supply voltage at high speed. In the voltage level shifter of the present invention, the logic high signal in the first power source voltage region does not cause the problem that the PMOS transistor in the second power source voltage region can not be sufficiently turned off, and unnecessary DC current discharge path does not occur.

Description

Supply Voltage Level Shifter

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage level shifter which is applied to a circuit having multiple power supply voltages, and which can block unwanted DC current discharge paths while transferring a signal in a low voltage region to a high voltage region.

In a circuit having multiple supply voltages, there may be a problem in signal transmission when signals are transferred to different power supply voltage level regions. For example, in a situation where a signal must be transferred from a circuit portion of a low voltage region to a circuit portion of a high voltage region, a logic high signal level of the low voltage region completely turns the PMOS transistor of the high voltage region into a turn- off), and signal transmission may not be performed properly.

In order to solve such a problem, the conventional methods include (1) a method using a dual voltage and (2) a method using a voltage drop method using a diode.

FIG. 1 is a diagram showing a conventional circuit using a dual voltage. The dual power supply voltages VDDL and VDDH are used together in a power supply level shifter. Such voltage level shifters are disclosed in Korean Patent Publication No. 2000-0077253.

Referring to FIG. 1, two pairs (M15 and M13, M16 and M14) of a PMOS transistor and an NMOS transistor are connected in series between a high power supply voltage VDDH and a ground, And the gates of the transistors M15 and M16 are cross-connected from the drain terminals of both of them. The two NMOS transistors M13 and M14 operate by receiving a complementary input signal IN. The inverter is connected to the output terminal again.

This circuit basically blocks this problem by disposing the logic high input (IN) of the low voltage region so that it is not connected to the high-voltage region of the PMOS transistor. However, according to this arrangement, the N-well for arranging the PMOS transistors M11, M15, M16, and M18 on the P-type substrate must be separately disposed, Not only is inefficient, but also increases the total area.

FIG. 2 is a diagram showing an example of a conventional circuit using a voltage drop method using a diode. In FIG. 2, a level using only one power supply voltage VDDH is used without using two power supply voltages VDDH and VDDL. Is an example of a shifter.

According to this method, an NMOS-type diode M21 is applied to a portion that changes from the low voltage region to the high voltage region, and the voltage of the node a11 is set to the threshold voltage V of the diode M21 _t-M21 ) to make VDDH-Vt _-M21 . Thus, the PMOS transistor M22 in the high voltage region is completely turned off by the input signal IN in the low voltage region.

However, this method does not work when the voltage difference between the level of the input signal IN and the power supply voltage VDDH in the high voltage region is greater than required. In other words, if the power supply voltage VDDH in the high voltage region is large, the voltage of the node all is not sufficiently lowered so that the PMOS transistor M22 may not be sufficiently turned off by the input signal IN having a low voltage logic high . In this case, a DC current discharge path through the transistors M21, M22, and M23 may occur.

Actually, since the threshold voltage of the diode M21 may vary depending on the temperature or the process, there is also a problem that the node all voltage is controlled to be different from the designed voltage. Further, since the node all is charged through the diode M21 when the input signal IN becomes logical low, the transistor M21 must use a considerably large size.

[Related Prior Art]

Korean Patent Publication No. 2000-0077253 (voltage level shifter and display device)

An object of the present invention is to solve the above problems, and it is an object of the present invention to provide a circuit having multiple power supply voltages, which can transmit a signal in a low voltage region at high speed to a high voltage region while eliminating inefficiency in layout design and blocking an unnecessary direct current discharge path (Voltage Level Shifter).

According to an aspect of the present invention, there is provided a voltage level shifter including first and second PMOS transistors and first to third NMOS transistors.

The first PMOS transistor and the first NMOS transistor are connected in series between the second power supply voltage (VDDH) and the ground And the common drain terminal is connected to the gate terminal of the second PMOS transistor through the second node.

The second PMOS transistor and the second NMOS transistor are connected in series between the second power supply voltage and the ground while receiving the input signal IN of the first power supply voltage VDDL region to the gate of the second NMOS transistor. And a common drain terminal is connected to a gate terminal of the first PMOS transistor and a gate terminal of the first NMOS transistor via a third node.

The third NMOS transistor has a first node charged to a voltage lower than the second power supply voltage, a gate connected to the gate terminal, a second node connected to the drain terminal, and the input signal connected to the source terminal, And controls the voltage of the second node in conjunction with the signal.

According to a method of charging the first node lower than the second power supply voltage, several embodiments are possible.

For example, according to the first embodiment, the voltage level shifter further includes a fourth transistor having the input signal supplied to the gate, the drain connected to the second power supply voltage, and the first node connected to the source, The voltage of the node can be charged to VDDL-Vt _{-M31 which} is lower than the second power supply voltage. Here, V _{t -M 31} is the threshold voltage of the fourth NMOS transistor.

In this case, a capacitor provided between the second power supply voltage and the first node may be further included, and coupling may occur due to the third and fourth NMOS transistors and the fourth NMOS transistor, The voltage can be prevented from being lowered.

According to the second embodiment, the voltage level shifter may further include m (m > = 1) diodes provided between the second power supply voltage and the first node. At this time, the voltage of the first node is maintained at a voltage lower by m times the diode voltage than the first power supply voltage. Here, when the diode is implemented using a MOS transistor, the voltage of the first node is VDDH- (mxVt _-M31 ).

Further, in addition to the first or second embodiment, the voltage level shifter may have a current source at the first node to stably maintain the first node voltage.

The inverter may further include an inverter for inverting the third node voltage at an end of the voltage level shifter. The output signal OUT of the inverter has the same logic state as the input signal as the signal of the second power supply voltage region.

The voltage level shifter according to the present invention can be applied to a circuit to which at least two power supply voltages are applied so that a signal in a low voltage range can be transmitted to a high voltage range at a high speed. Nevertheless, since the voltage level shifter of the present invention operates at a single power supply voltage, there is no unnecessary arrangement problem in design such as disposing N-wells on a P-type substrate. Therefore, layout design is easier and more efficient than the prior art.

Naturally, there is no problem that the logic high signal in the low voltage region does not sufficiently turn off the PMOS transistor in the high voltage region, and unnecessary DC current discharge path does not occur.

1 is a conventional circuit diagram using a dual voltage,
FIG. 2 is a conventional circuit diagram using a voltage drop method using a diode,
3 is a circuit diagram of a level shifter according to an embodiment of the present invention, and
4 is a circuit diagram of a level shifter according to another embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in more detail with reference to the drawings.

The voltage level shifter 300 of the present invention, which is illustratively shown in FIG. 3, may be applied to a circuit having at least a first power supply voltage VDDL and a second power supply voltage VDDH. Here, the ground (GND) level is not included in at least two power supply voltages. Nevertheless, the level shifter 300 of the present invention is a single power supply circuit using only the second power supply voltage VDDH higher than the first power supply voltage VDDL.

The input signal IN input to the level shifter 300 is a signal of the first power supply voltage region and the output signal OUT output from the level shifter 300 is input to the input signal IN as a signal of the second power supply voltage region, (High, Low) state. It is assumed that the second power supply voltage VDDH is higher than the first power supply voltage VDDL in the low voltage region.

3, the level shifter 300 includes a first NMOS transistor M34, a second NMOS transistor M36, a third NMOS transistor M33, a fourth NMOS transistor M33, A first PMOS transistor M35, a second PMOS transistor M37 and a third PMOS transistor M39 are connected in series between the PMOS transistor M31 and the fifth NMOS transistor M38, And their connection relations are as follows.

The pair of the first PMOS transistor M35 and the first NMOS transistor M34 and the pair of the second PMOS transistor M37 and the second NMOS transistor M36 are connected to the second power supply voltage VDDH, (GND) to form a common drain circuit. The drain terminal of each of the first PMOS transistor M35 and the first NMOS transistor M34 is connected to the gate terminal of the second PMOS transistor M37 while being connected to the second node n32. The drain terminal of each of the second PMOS transistor M37 and the second NMOS transistor M36 is connected to the gate terminal of the first PMOS transistor M35 while being connected to the third node n33.

The first NMOS transistor M34 has a gate terminal connected to the third node n33 and a drain and a source terminal connected between the second node n32 and the ground GND to supply the voltage of the second node n32 Pull down. The second NMOS transistor M36 is connected to the gate terminal of the input signal IN and is connected between the third node n33 and the ground GND to pull down the voltage of the third node n33.

The third NMOS transistor M33 has a gate terminal connected to a first node n31, and a drain and a source terminal connected to a second node n32 and an input signal IN. The input signal IN is connected to the gate terminal of the fourth NMOS transistor M31 and the second power supply voltage VDDH and the first node n31 are connected to the drain and source terminals, respectively. The arrangement of the fourth and fifth MOS transistors M31 is for the embodiment of Fig. 3 and may have different connection relationships in other embodiments described below.

The third PMOS transistor M39 and the fifth NMOS transistor M38 form an inverter, and an output signal OUT is connected to each drain terminal. Since the third node n33 is commonly connected to each gate terminal of the third PMOS transistor M39 and the fifth NMOS transistor M38, the output signal OUT is inverted from the voltage of the third node n33 will be.

3 is composed of a first NMOS transistor M34, a second NMOS transistor M36, a first PMOS transistor M35, a second PMOS transistor M37, and a third PMOS transistor M37. And the third NMOS transistor M33. The inverter implemented with the third PMOS transistor M39 and the fifth NMOS transistor M38 in the rear stage is not an essential configuration and the fourth NMOS transistor M31 is not constituted by the first node n31 voltage Lt; RTI ID = 0.0 > and / or < / RTI >

Hereinafter, the operation of the power supply voltage level shifter 300 of FIG. 3 will be described.

<When the input signal IN of the first power supply voltage region is logic high: Fig. 3>

When the input signal IN in the first power supply voltage VDDL region becomes the logic high voltage VDDL, the second NMOS transistor M36 is first turned on and the third node n33 is discharged to the ground GND , The voltage of the third node (n33) becomes logic low. Accordingly, the third PMOS transistor M39 is turned on and the fifth NMOS transistor M38 is turned off, so that the output signal OUT is output to the logic high of the second power supply voltage VDDH level. As a result, the logic high (VDDL) of the first power supply voltage region is changed to the logic high (VDDH) of the second power supply voltage region.

At this time, the first PMOS transistor M35 is turned on by the voltage of the third node n33, which is logic low, and becomes logic high while the second node n32 is charged by the second power supply voltage VDDH, The 2-PMOS transistor M37 is completely turned off by the second node n32 charged with the second power supply voltage VDDH. The first NMOS transistor M34 is turned off by the third node n33 which is a logic low.

On the other hand, the voltage of the second node n32 must be changed to the same logic as the input signal IN. That is, if the input signal IN is a logic high (VDDL), the second node n32 must also be a logic high (VDDH), and if the input signal IN is a logic low, the second node n32 must also be a logic low do. 1, since the first NMOS transistor M34 is controlled by the voltage of the third node n33, the third NMOS transistor M33 is used instead of the third NMOS transistor M33 when the input signal IN is logic low It is necessary to provide a configuration for discharging the voltage of the second node n32 to the ground level in conjunction with the input signal IN, and this configuration is the third NMOS transistor M33. However, when the input signal IN is logic high, the third NMOS transistor M33 must be turned off like the first NMOS transistor M34.

As a result, the gate voltage of the third NMOS transistor M33, that is, the voltage of the first node n31 must be kept lower than the second power voltage VDDH. Various structures using the fourth NMOS transistor M31 are shown to maintain the voltage. Fig. 3 is an example thereof, and Fig. 4 is another example thereof.

3, the fourth NMOS transistor M31 is turned on by the input signal IN so that the voltage of the first node n31 is the input signal IN which is the logic high voltage VDDL of the first power supply voltage region, Is subtracted from the threshold voltage of the fourth NMOS transistor M31. That is, when the input signal IN is logic high, the voltage V _n31 of the first node _n31 is VDDL-V _t-M31 . Here, _Vt-M31 is the threshold voltage of the fourth emmos transistor M31.

In order for the third NMOS transistor M33 to turn on, the gate voltage must be higher than the source voltage (or the drain voltage) by a threshold voltage V _t-M33 or more (V _t-M33 is the threshold voltage of the third NMOS transistor M33 ). VDDL-Vt _-M31 is input from the first node n31 to the gate of the third NMOS transistor M33, the second power supply voltage VDDH is input from the second node n32 to the drain terminal thereof, And a logic high (VDDL) of the first power supply voltage region, which is the input signal IN, is input to the terminal and is biased.

As a result, when the input signal IN is a logic high (VDDL), the gate-drain terminal voltage V _GD of the third NMOS transistor M33 is negative as shown in the following equation (1) Is not formed.

The gate-source terminal voltage V _{GS of} the third eXmos transistor M33 is also expressed as | V _t-M31 | The channel is not formed even toward the source side.

As a result, the third NMOS transistor M33 is completely turned off. Therefore, although the first PMOS transistor M35 is turned on, the input signal having the logic high (VDDL) of the first power supply voltage region at the second power supply voltage VDDH through the third NMOS transistor M33 IN are not formed.

As described above, when the input signal IN which is the logic high (VDDL) of the first power supply voltage region is output to the logic high (VDDH) of the second power supply voltage region, the second NMOS transistor M36 and the The high-speed processing can still be performed only by the two gate delays due to the three-PMOS transistor M39 and the voltage of the first node n31 is always charged to the voltage lower than the input signal IN by the threshold voltage The third NMOS transistor M33 is not turned on, so that a DC current discharge path does not occur.

<When the input signal IN of the first power supply voltage region is logic low: Fig. 3>

When the input signal IN becomes a logical low (GND) from the logic high (VDDL), the second NMOS transistor M36 is completely turned off. In a complementary manner, the second node n32 becomes a logic low to turn on the second PMOS transistor M37, so that the third NMOS transistor M33 must be turned on. First, since the first node n31 is charged with VDDL-Vt- _M31 , the input signal IN has a value VDDL-Vt _-M31 obtained by subtracting the threshold voltage V _t-M33 from the voltage of the first node n31 -V _t-M33 ), the third NMOS transistor M33 starts to turn on. That is, IN? (VDDL-Vt _-M31 -Vt _-M33 ) is the turn-on condition of the third NMOS transistor M33.

The fourth NMOS transistor M31 is turned off as the input signal IN transitions from logic high VDDL to logic low while the first node n31 is still charged with VDDL-Vt _-M31 do.

Accordingly, when the input signal IN becomes lower than VDDL-Vt- _M31 -Vt _-M33 , the third NMOS transistor M33 is turned on and the voltage of the second node n32 is discharged to a logic low level. Then, the second PMOS transistor M37 is turned on, the voltage of the third node n33 becomes a logic high, and the first PMOS transistor M35 is also turned off. The first NMOS transistor M34 is also turned on by the voltage of the third node n33 which is logic high to accelerate the discharge of the second node n32 voltage to the logic low.

The third PMOS transistor M39 is turned off, the fifth NMOS transistor M38 is turned on, and the output signal OUT becomes a logic low.

3, a capacitor MC may be disposed between the second power supply voltage VDDH and the first node n31, according to an embodiment of the present invention. The voltage of the first node n31 may be lowered by coupling between the fourth and fifth NMOS transistors M31 and M33 as the input signal IN is changed to a logic low state, The capacitor MC delays the drop of the voltage of the first node n31. The capacitor MC maintains the voltage of the first node n31 and relaxes the coupling effect of the third and fourth NMOS transistors M33 and M31.

The fourth NMOS transistor M31 does not need to be large in size because it does not participate in charging and discharging during operation, and only needs to charge the first node n31 at the time of power-up. Therefore, the coupling effect by the fourth NMOS transistor M31 is negligible. That is, the capacitor MC is not an essential configuration. For the same reason, the PMOS transistor may be arranged instead of the fourth NMOS transistor M31.

According to the above circuit, a level shift is possible between arbitrary voltages. The level shifter of the present invention can also be implemented by the following circuit of Fig.

<Another Embodiment of Level Shifter: Fig. 4>

The level shifter 400 according to the embodiment of FIG. 4 is basically the same as the level shifter 300 of FIG. 3 except that a fourth emmos transistor M31, which receives the input signal IN as a gate terminal, A diode is arranged in place of the diode.

Referring to FIG. 4, the fourth NMOS transistor M31 is implemented as a MOS diode by connecting its gate terminal with the drain terminal to the second power supply voltage VDDH. Accordingly, the voltage of the first node n31 becomes VDDH-Vt- _M31 , not VDDL-Vt _-M31 . However, theoretically, in the circuit of FIG. 4, if the voltage difference between VDDH and VDDL is Vt _-M31 + Vt _-M33 or more, a direct current path from VDDH to VDDL may occur.

In this case, the fourth NMOS transistor connected in series by a plurality (m) of the diode in place (M31), a first node (n31) of the voltage _{non-VDDH-V t-M31 VDDH- (} m × V t-M31 ). &Lt; / RTI &gt; These diodes need not be large in size.

<Examples>

The important point in the level shifters 300 and 400 of the present invention is that the control voltage of the third NMOS transistor M33, that is, the voltage of the first node n31 is kept lower than the second power supply voltage. According to the embodiment, in order to more stably maintain the voltage drop of the threshold voltage _Vt-M31 through the fourth NMOS transistor M31 of FIG. 3 and FIG. 4, a current source Current Source) can be placed.

The current source may be any type, and the sixth NMOS transistor M32 of FIG. 3 is an example thereof. Referring to FIG. 3, a sixth NMOS transistor M32 having a gate terminal and a source terminal connected to the ground (GND) is connected to the first node n31 and functions as a current source. As described above, the current source can be arranged even when the PMOS transistor is arranged instead of the fourth NMOS transistor M31.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be construed as limiting the scope of the invention as defined by the appended claims. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention.

Claims (7)

First and second PMOS transistors and first to third NMOS transistors,
The first PMOS transistor and the first NMOS transistor are connected in series between the second power supply voltage (VDDH) and the ground A common drain terminal is connected to a gate terminal of the second PMOS transistor via a second node,
The second PMOS transistor and the second NMOS transistor are connected in series between the second power supply voltage and the ground while receiving the input signal IN of the first power supply voltage VDDL region to the gate of the second NMOS transistor. And a common drain terminal is connected to a gate terminal of the first PMOS transistor and a gate terminal of the first NMOS transistor via a third node,
The third NMOS transistor has a first node charged to a voltage lower than the second power supply voltage, a gate connected to the gate terminal, a second node connected to the drain terminal, and the input signal connected to the source terminal, And controls the voltage of the second node in response to the signal.
The method according to claim 1,
Further comprising a fourth NMOS transistor having the input signal supplied to the gate and the drain connected to the second power supply voltage and the first node connected to the source, so that the voltage of the first node is lower than the second power supply voltage VDDL -V _{t-M31 &lt; /} RTI &gt;
And V _{t -M 31} is a threshold voltage of the fourth NMOS transistor.
3. The method of claim 2,
And a capacitor provided between the second power supply voltage and the first node, so that the voltage of the first node is low due to coupling that can be generated by the third and fourth NMOS transistors The voltage level shifter is turned off.
The method according to claim 1,
Further comprising m (m &gt; = 1) diodes connected in series between the second power supply voltage and the first node so that the voltage of the first node is lowered by m times the diode voltage of the second power supply voltage Voltage level shifter.
5. The method of claim 4,
The diode is implemented using a MOS transistor,
Wherein a voltage of the first node is charged to VDDH- (mxVt _-M31 ), and Vt _-M31 is a threshold voltage of the MOS transistor.
6. The method according to any one of claims 2 to 5,
And a current source is provided to the first node to maintain the first node voltage.
The method according to claim 1,
Further comprising an inverter for inverting the third node voltage to output an output signal (OUT) having the same logic state as the input signal as the signal of the second power supply voltage region.

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