KR101642161B1 - Magenetic Memory of performing Bidirectional Switching Operation - Google Patents

Magenetic Memory of performing Bidirectional Switching Operation Download PDF

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Publication number
KR101642161B1
KR101642161B1 KR1020110090100A KR20110090100A KR101642161B1 KR 101642161 B1 KR101642161 B1 KR 101642161B1 KR 1020110090100 A KR1020110090100 A KR 1020110090100A KR 20110090100 A KR20110090100 A KR 20110090100A KR 101642161 B1 KR101642161 B1 KR 101642161B1
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South Korea
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layer
intermediate semiconductor
semiconductor layer
lower wiring
conductive buffer
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KR1020110090100A
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Korean (ko)
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KR20130026744A (en
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송윤흡
길규현
양형준
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한양대학교 산학협력단
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165Auxiliary circuits
    • G11C11/1659Cell access

Abstract

A magnetic memory capable of performing a bidirectional switching operation is disclosed. The bidirectional switching layer is connected to the MTJ layer which can change the resistance state by changing the magnetization direction by the applied current. The bidirectional switching layer has an intermediate semiconductor layer formed between two conductive films. The intermediate semiconductor layer is doped p-type and forms a Schottky junction. Further, the intermediate semiconductor layer is pinch-off according to the applied bias, and is modeled by a zener diode. Thus, a bi-directional switching operation can be performed.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a magnetic memory that performs bidirectional switching operations,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetic memory having a switching element, and more particularly, to a magnetic memory having a bi-directional switching element using a Schottky barrier.

Recently, a method of reducing the size of a device for high integration of a memory device exposes a certain limit. Therefore, researches have been actively carried out to improve the degree of integration of devices by changing the conditions other than the size of the device. MLC (Multi Level Cell) technology capable of storing a plurality of information in one memory cell is actively discussed as a technology proposed for improving the integration degree. The MLC technology has been evaluated as a technology having a considerable efficiency because it improves the data storage capacity of each cell and the conventional manufacturing process is not changed much.

In addition, there is a technique of increasing the density of the stacked structure of existing chips through the packaging process, thereby reducing the size of the packaged chips or increasing the storage capacity even in the same size. This technique is in line with the technology of forming a laminated structure in three dimensions. This is a technology for realizing a wiring structure between substrates during wafer bonding and connecting the electrode pads, thereby stacking a plurality of chips in the same planar space. And a plurality of chips in which memory cells are formed can be integrated.

In addition, there is a cross-point memory in which a variable resistance material is used as a cell, arranged in a matrix form of a cell, and then connected to the upper and lower portions of the cell.

In the cross-point memory, the variable resistance material has a structure in which two wirings are disposed on the upper and lower sides of the resistance-variable layer. The two wirings have a shape vertically intersecting each other, and the resistance variable layer is disposed at the intersection point. In order to perform the individual read operation and the write operation for the cross point memory, a selection element must be connected to the resistance variable layer. That is, even if a predetermined bias is applied to the two wirings, the selectivity of the cell can be ensured only if the selection device having the characteristic of turning on only the bias having the specific level is disposed.

A transistor is considered as a selection device for securing selectivity of a cell. However, the transistor occupies a large area, and is difficult to form on the upper or lower portion of the resistance variable layer. In the case of disposing on the resistance variable layer, there is a burden that an epitaxial process for forming a silicon single crystal or a polycrystal is necessarily added. In addition, when a transistor is disposed below and a resistance-variable layer is formed on the upper portion, an interlayer insulating film must be interposed between the transistor and the resistance-variable layer, and a via contact through the interlayer insulating film must be formed.

Further, techniques for forming a diode with a selection element in addition to a technology using a transistor as a selection element are discussed.

1 is a sectional view showing a magnetic memory using a diode as a selection element according to the prior art.

1, a p-type region 110 is formed on an n-type substrate 100, an insulating layer 120 is formed on a p-type region 110, and a lower wiring 130 . The resistance variable layer 140 is formed on the lower wiring 130. An upper wiring 150 is formed on the resistance variable layer 140.

In particular, the resistance-variable layer 140 has a typical structure of an STT-MRAM employing a method of reversing the magnetization of the free layer according to a spin transfer torque method.

When the STT-MRAM element is used as the resistance variable layer 140, bi-directional driving is essential. This means that the selectivity of the cell can not be secured by the conventional unidirectional p / n junction diode structure. That is, in the case where the diode is formed by only the p region 110 formed on the n-type substrate 100 in FIG. 1, bidirectional driving to the resistance variable layer 140 can be achieved due to the inherent rectifying characteristic of the diode No problems are exposed. That is, only a forward current can be formed in the direction of the substrate 100 through the p region 110, and only a current path from the upper wiring 150 to the lower wiring 130 is formed. This means that it is impossible to form a reverse current in the diode formed by the p region 110 and the substrate 100.

Unidirectional driving is also required to effect magnetization reversal in the resistance variable layer 140, but it is efficient to perform bidirectional driving in view of the characteristics of the element. However, in FIG. 1, a problem that bidirectional driving can not be performed occurs.

In order to solve the above-described problems, the present invention provides a magnetic memory capable of driving the MTJ layer, which is a resistance variable layer, in both directions.

According to an aspect of the present invention, there is provided a bi-directional switching device including: a bi-directional switching layer modeled as a zener diode according to a bias applied; And a MTJ layer formed on the bi-directional switching.

According to the present invention described above, a p-type doped intermediate semiconductor layer is disposed between the conductive lower wiring layer and the conductive buffer layer. In the intermediate semiconductor layer, the depletion region expands and the pinch-off shape in which the bulk region disappears is generated in accordance with the applied bias. By the pinch-off, a yield phenomenon occurs in the lower wiring layer and the conductive buffer layer in accordance with the magnitude of the bias, which is modeled as a Zener diode. In addition, since it can be modeled as a different zener diode depending on the direction of the bias, a bi-directional switching operation can be performed.

1 is a sectional view showing a magnetic memory using a diode as a selection element according to the prior art.
2 is a cross-sectional view illustrating a magnetic memory having bidirectional selection elements according to a preferred embodiment of the present invention.
3 to 7 are a conceptual diagram and band diagram for explaining the operation of the bidirectional switching layer shown in FIG. 2 according to a preferred embodiment of the present invention.

The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for like elements in describing each drawing.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Example

2 is a cross-sectional view illustrating a magnetic memory having bidirectional selection elements according to a preferred embodiment of the present invention.

Referring to FIG. 2, a magnetic memory according to an embodiment of the present invention includes a bi-directional switching layer 200 and a magnetic tunneling junction (MTJ) layer 300. An upper wiring layer 400 is formed on the MTJ layer 300.

The bidirectional switching layer 200 has a lower wiring layer 210, an intermediate semiconductor layer 220, and a conductive buffer layer 230.

The lower wiring layer 210 is made of a conductive material and is required to have a predetermined work function. Preferably, the lower wiring layer 210 includes TiN.

The intermediate semiconductor layer 220 is formed on the lower wiring layer 210 and is formed of a semiconductor material such as Si or GaAs. In particular, the intermediate semiconductor layer 220 is doped p-type. For example, when the intermediate semiconductor layer 220 includes Si, B or Ga may be used as the dopant.

A conductive buffer layer 230 is formed on the intermediate semiconductor layer 220. The conductive buffer layer 230 facilitates the formation of a MTJ layer 300 and forms a bidirectional switching element together with the lower wiring layer 210 and the intermediate semiconductor layer 220.

An MTJ layer 300 is provided on the bidirectional switching layer 200.

The MTJ layer 300 includes an input free layer 310, a non-magnetic metal layer 320, and an input pinned layer 330.

The input free layer 310 and the input pinned layer 330 are made of a ferromagnetic material and the nonmagnetic metal layer 320 includes a nonmagnetic metal such as Cu, Al, or Cr.

In addition, the input free layer 310 and the input fixing layer 330 may be formed by mutually changing positions. The magnetization direction of the input free layer 310 is changed and is equal to or different from the magnetization direction of the input pinned layer 330 when a current equal to or greater than a specific threshold value is applied so that the spin transfer torque acts on the MTJ layer 300 .

When the magnetization directions of the input free layer 310 and the input fixed layer 330 are the same, the MTJ layer 300 realizes a low resistance state. When the magnetization directions of the input free layer 310 and the input fixed layer 330 are different , The MTJ layer 300 implements a high resistance state.

The input free layer 310 may be made of a soft magnetic metal and may be made of CoFeB or FePt. The input pinned layer 330 may be composed of a multi-layered film of a semiconductive metal and a soft magnetic metal. IrMn or FeMn may be used as the semiconductive metal. Examples of the soft magnetic metal include Co, Fe, Ni, Can be used. In addition, the input free layer 310 and the input fixing layer 330 may be formed by changing their positions.

3 to 7 are a conceptual diagram and band diagram for explaining the operation of the bidirectional switching layer shown in FIG. 2 according to a preferred embodiment of the present invention.

Referring to Fig. 3, the state before the bonding is started is disclosed.

That is, the bidirectional switching layer is composed of the lower wiring layer 210, the intermediate semiconductor layer 220, and the conductive buffer layer 230.

For convenience of explanation, it is assumed that the lower wiring layer 210 and the conductive buffer layer 230 are made of the same material. Therefore, the work functions of the lower wiring layer 210 and the conductive buffer layer 230 are the same.

Further, the intermediate semiconductor layer 220 is assumed to be p-type doped Si. The work function of the lower wiring layer 210 and the conductive buffer layer 230 is set lower than the work function of the intermediate semiconductor layer 220.

The Fermi level E FS of the intermediate semiconductor layer 220 is maintained at a level higher than the Fermi level E FM1 of the lower wiring layer 210 disposed on both sides and the Fermi level E FM2 of the conductive buffer layer 230 before the bonding is performed. This is due to the assumption that the work function of the intermediate buffer layer 220 is higher. Since the work function is the energy required to move the electrons of the Fermi level to vacuum, higher work function means lower Fermi level than other film materials. In particular, since the intermediate semiconductor layer 220 is doped with p-type, the Fermi level maintains a lower value than the level of the intrinsic semiconductor.

Referring to FIG. 4, a band diagram at the time of bonding the lower wiring layer 210, the intermediate semiconductor layer 220, and the conductive buffer layer 230 is shown. When the junction is made, charge transfer occurs until an equilibrium state in which the Fermi level of each film quality coincides is formed.

That is, the electrons of the lower wiring layer 210 of the conductive metal and the conductive buffer layer 230 move to the intermediate semiconductor layer 220 by the diffusion phenomenon. Therefore, a depletion region is formed in the intermediate semiconductor layer 220 by recombination of electrons and holes. In the lower wiring layer 210 made of a metal and the conductive buffer layer 230, a positive charge region is disclosed. However, on the energy diagram, the electric potential of the conductor is the same, so that the Fermi level distortion does not occur.

The diffusion of the carriers occurs due to the bonding, and when the equilibrium state is reached, the Fermi levels of the lower wiring layer 210, the intermediate semiconductor layer 220, and the conductive buffer layer 230 coincide with each other. In the depletion region, there are negative charges due to the movement and disappearance of holes. Therefore, diffusion of electrons, which are carriers of the metal, into the intermediate semiconductor layer 220 by the potential barrier formed in the depletion region is blocked. Therefore, a Schottky barrier appears at the interface between the lower wiring layer 210 / the intermediate semiconductor layer 220 and the junction between the intermediate semiconductor layer 220 and the conductive buffer layer 230.

Referring to FIG. 5, a bias from the lower wiring layer 210 toward the conductive buffer layer 220 is applied. That is, a voltage of positive polarity is applied to the lower wiring layer 210, and a voltage of negative polarity is applied to the conductive buffer layer 230. Accordingly, the applied bias is directed from the lower wiring layer 210 to the conductive buffer layer 230. This means that a reverse bias is applied to the lower wiring layer 210 / the intermediate semiconductor layer 220 and that a positive bias is applied to the intermediate semiconductor layer 220 / conductive buffer layer 230.

In the lower wiring layer 210 / the intermediate semiconductor layer 220 to which the reverse bias is applied, the level of the energy barrier is increased by the reverse bias. Also, the depletion region formed in the intermediate semiconductor layer 220 shows a tendency to expand. The reverse bias forms the difference between the Fermi level E FM1 of the lower wiring layer 210 and the Fermi level E FS of the intermediate semiconductor layer. That is, the Fermi level E FS of the intermediate semiconductor layer 220 is higher than the Fermi level E FM1 of the lower wiring layer 210 due to the reverse bias. Therefore, the flow of current is blocked by the formation of the barrier.

In the intermediate semiconductor layer 220 / conductive buffer layer 230 to which the positive bias is applied, the level of the energy barrier decreases. That is, the Fermi level E FS of the intermediate semiconductor layer 220 is lower than the Fermi level E FM2 of the conductive buffer layer 230. Also, the width of the depletion region formed in the intermediate semiconductor layer 220 shows a tendency to decrease.

A depletion region appears in the region of the lower wiring layer 210 and the intermediate semiconductor layer 220 adjacent to the conductive buffer layer 230. A bulk region of the intermediate semiconductor layer 220 may exist between the depletion regions formed on both sides. In the bulk region of the intermediate semiconductor layer 220, the energy bands of the conduction band Ec and the valence band E V remain smooth.

Referring to FIG. 6, a bias of a higher level than the bias shown in FIG. 5 is applied from the lower wiring layer 210 toward the conductive buffer layer 230.

The depletion region of the intermediate semiconductor layer 220 is enlarged by the increased reverse bias in the lower wiring layer 210 / the intermediate semiconductor layer 220 to which the reverse bias is applied. In addition, the width of the depletion region tends to decrease in the intermediate semiconductor layer 220 / conductive buffer layer 230 to which the positive bias is applied. The depletion region expands at the bonding interface of the lower wiring layer 210 / the intermediate semiconductor layer 220 to which the reverse bias is applied. That is, the depletion region of the intermediate semiconductor layer 220 is enlarged and a pinch-off phenomenon occurs in which the entire intermediate semiconductor layer 220 is composed of a depletion region. This means that the bulk region having a smooth energy band disappears.

Therefore, even if the size of the bias is further increased between the lower wiring layer 210 and the conductive buffer layer 230, no further increase of the current occurs.

This is because the energy band difference between the lower wiring layer 210 and the conductive buffer layer 230, E FM2 - E FM1 is significantly increased. Also, between the lower wiring layer 210 to which a reverse bias is applied and the intermediate semiconductor layer 220, a Zener yield phenomenon occurs at a normal low voltage. That is, when the width of the potential barrier formed by the intermediate semiconductor layer 220 disposed between the lower wiring layer 210 and the conductive buffer layer 230 is sufficiently narrow, electrons tunneling occurs and electrons tunnel from the conductive buffer layer 230 to the lower wiring layer 230. [ Tunneling of the electrons toward the second electrode 210 occurs. Therefore, current flow from the lower wiring layer 210 toward the conductive buffer layer 230 is generated due to electron tunneling.

The structure described above can be modeled as a zener diode formed between the lower wiring layer 210 and the conductive buffer layer 230. That is, when a voltage higher than a predetermined level is applied, the Zener diode is turned on, and when a voltage lower than a certain level is applied, the Zener diode blocks the flow of current.

Therefore, the flow of current from the lower wiring layer 210 to the MTJ layer 300 can be controlled.

Referring to FIG. 7, a bias from the conductive buffer layer 230 toward the lower wiring layer 210 is applied. Therefore, a reverse bias is applied between the conductive buffer layer 230 and the intermediate semiconductor layer 220, and a positive bias is applied between the intermediate semiconductor layer 220 and the lower wiring layer 210. The depletion region is enlarged by the reverse bias between the conductive buffer layer 230 and the intermediate semiconductor layer 220 as shown in FIG. 6, and the intermediate semiconductor layer 220 is expanded by the reverse bias between the conductive buffer layer 230 and the intermediate semiconductor layer 220, - Off.

Accordingly, a zener diode is formed between the conductive buffer layer 230 and the lower wiring layer 220. However, it is opposite to the Zener diode shown in FIG. That is, in FIG. 7, the positive direction of the Zener diode is directed from the lower wiring layer 210 to the conductive buffer layer 230. Therefore, when a bias is applied from the conductive buffer layer 230 and a voltage of a predetermined level or higher is applied, the Zener diode is turned on, and a condition is satisfied in which a current can flow. This means that when a bias is applied through the conductive buffer layer 230, a current can flow only at a voltage higher than a certain level. Whereby the switching operation of the Zener diode from the conductive buffer layer 230 to the lower wiring layer 210 can be controlled.

6 and 7, even if the direction of the bias is set between the lower electrode layer 210 and the conductive buffer layer 230, a zener diode is formed in the bidirectional switching layer 200, The switching characteristic is turned on only when the bias is applied. This means that the bi-directional switching layer 200 is modeled as a Zener diode regardless of the direction of the bias. In this way, a selective turn-on operation can be performed on the MTJ layer 300, and data write and read operations can be performed.

200: bidirectional switching layer 210: lower wiring layer
220: intermediate semiconductor layer 230: conductive buffer layer
300: MTJ layer 310: input free layer
320: non-magnetic metal layer 330: input fixed layer

Claims (5)

  1. A bidirectional switching layer modeled as a Zener diode according to an applied bias; And
    And an MTJ layer formed on the bi-directional switching layer,
    Wherein the bi-
    A lower wiring layer of a conductive material;
    An intermediate semiconductor layer formed on the lower wiring layer and doped with p-type; And
    And a conductive buffer layer of a metal material formed on the intermediate semiconductor layer.
  2. The magnetic memory according to claim 1, wherein a Schottky barrier appears at an interface between the junction of the lower wiring layer and the intermediate semiconductor layer and a junction between the intermediate semiconductor layer and the conductive buffer layer.
  3. delete
  4. The magnetic memory according to claim 1, wherein the work function of the intermediate semiconductor layer is larger than the work function of the lower wiring layer or the conductive buffer layer.
  5. The magnetic memory according to claim 1, wherein the intermediate semiconductor layer is in a pinch-off state in which only a depletion region is present according to a bias applied.
KR1020110090100A 2011-09-06 2011-09-06 Magenetic Memory of performing Bidirectional Switching Operation KR101642161B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10373653B2 (en) 2017-06-13 2019-08-06 Samsung Electronics Co., Ltd. Semiconductor device having first memory section and second memory section stacked vertically on each other

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100237314A1 (en) * 2009-03-19 2010-09-23 Takayuki Tsukamoto Resistance change type memory
KR101048906B1 (en) * 2008-01-11 2011-07-12 가부시끼가이샤 도시바 resistance change type memory

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101048906B1 (en) * 2008-01-11 2011-07-12 가부시끼가이샤 도시바 resistance change type memory
US20100237314A1 (en) * 2009-03-19 2010-09-23 Takayuki Tsukamoto Resistance change type memory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10373653B2 (en) 2017-06-13 2019-08-06 Samsung Electronics Co., Ltd. Semiconductor device having first memory section and second memory section stacked vertically on each other

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