KR101630180B1 - Wire bonding structure and method thereof - Google Patents

Wire bonding structure and method thereof Download PDF

Info

Publication number
KR101630180B1
KR101630180B1 KR1020140125874A KR20140125874A KR101630180B1 KR 101630180 B1 KR101630180 B1 KR 101630180B1 KR 1020140125874 A KR1020140125874 A KR 1020140125874A KR 20140125874 A KR20140125874 A KR 20140125874A KR 101630180 B1 KR101630180 B1 KR 101630180B1
Authority
KR
South Korea
Prior art keywords
end
wire
stitch
conductive
plurality
Prior art date
Application number
KR1020140125874A
Other languages
Korean (ko)
Other versions
KR20160034655A (en
Inventor
문주형
송경민
유재복
Original Assignee
주식회사 에스에프에이반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 에스에프에이반도체 filed Critical 주식회사 에스에프에이반도체
Priority to KR1020140125874A priority Critical patent/KR101630180B1/en
Publication of KR20160034655A publication Critical patent/KR20160034655A/en
Application granted granted Critical
Publication of KR101630180B1 publication Critical patent/KR101630180B1/en

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494Connecting portions
    • H01L2224/4941Connecting portions the connecting portions being stacked
    • H01L2224/49425Wedge bonds
    • H01L2224/49427Wedge bonds outside the semiconductor or solid-state body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909Post-treatment of the connector or wire bonding area
    • H01L2224/85951Forming additional members, e.g. for reinforcing

Abstract

A wire bonding structure of a semiconductor package is disclosed. This wire bonding structure is a wire bonding structure in which a plurality of leads formed on the surface of a substrate and a plurality of input / output pads of the semiconductor chip are electrically connected using a conductive wire, And the other end of the conductive wires is stitch bonded to one stitch position where one end of the conductive wires is formed on one lead surface, Lt; / RTI >

Description

[0001] WIRE BONDING STRUCTURE AND METHOD THEREOF [0002]

The present invention relates to a wire bonding structure and a method thereof, and more particularly,

Output pads and leads of a semiconductor chip are electrically connected to each other using a conductive wire, and a method thereof.

Typically, the wire bonding refers to a predetermined area (for example, a lead or a wiring pattern, etc.) of an input / output pad of a semiconductor chip and a substrate (for example, a lead frame, a printed circuit board, a circuit film, , And a lead is taken as an example in the following description), thereby electrically connecting the input / output pads of the semiconductor chip and the leads.

Normally, such a wire bonding structure is a typical structure in which one input / output pad and one lead are connected with a conductive wire in a one-to-one relationship.

Unlike the conventional wire bonding structure, in some cases, one end of a plurality of conductive wires may be bonded to a plurality of input / output pads, and the other end of each of the conductive wires may be bonded to one lead have. Such a conventional wire bonding structure is shown in Figs. 1A and 1B.

1A to 1B are views showing a conventional wire bonding structure.

As shown in Figs. 1A and 1B, one end of each of the three conductive wires W1, W2 and W3 is bonded onto three different input / output pads 21, 23 and 25 of the semiconductor chip 20 And the other ends of the three conductive wires W1, W2 and W3 are bonded onto one lead 30 on the superty 10, the respective ends of the three conductive wires W1, W2 and W3 And the other end is stitch bonded to three different stitch positions (SP) on the one lead 30. That is, the three conductive wires w1, w2 and w3 are stitch-bonded to three stitch positions (SP1, SP2 and SP3 in Fig. 1A) arranged in a line on the one lead 30 Therefore, conventionally, the width of the lead 30 has to be formed in a substantially rectangular shape and its width (or length) has to be increased as much as possible.

However, in the conventional wire bonding structure, when two or more of the conductive wires are bonded on one lead 30, design constraints are caused according to the length and arrangement of the leads, It is not possible to meet the requirements of the semiconductor package which has recently been made into a fine pitch as well as an increase in the production cost. .

As the length of the lead becomes longer, the wire angle becomes larger, so that the weak bonding and the conductive wire are drawn toward the adjacent leads 31 and 33 so that contact with the adjacent leads 31 and 33 Resulting in short defects.

In addition, when a plurality of conductive wires are stitch-bonded to one lead, a capillary touches the stitches that are initially bonded, which can cause damage and cause defects.

Accordingly, an object of the present invention is to provide a wire bonding structure and a method thereof, which can bond at least two conductive wires to one lead having a fine pitch, without increasing the lead length.

According to an aspect of the present invention, there is provided a wire bonding structure including a plurality of leads formed on a surface of a substrate and a plurality of input / output pads of the semiconductor chip using a conductive wire, A stitch position in which one end of a plurality of conductive wires is ball-bonded to different input / output pads and the other end of the plurality of conductive wires is formed on one lead surface, stitch bonding to a multi-layer structure.

According to another aspect of the present invention, there is provided a wire bonding method comprising: ball bonding one end of a plurality of conductive wires to different input / output pads; and bonding the other end of the plurality of conductive wires to one stitch position stitch bonding to a stitch position in a multi-layered structure.

According to the present invention, by stacking a plurality of conductive wires in one stitch position on one lead by using a bump ball, the design restriction according to the lead arrangement and the conductive wire arrangement disappears, It is advantageous to miniaturize the semiconductor package without changing the length, and design constraints are reduced in the case of subcutaneous fabrication such as PCB and lead frame. In addition, the PCB manufacturing cost is reduced by the short lead length.

FIGS. 1A and 1B are views showing a conventional wire bonding structure.
2A and 2B are views showing a wire bonding structure according to an embodiment of the present invention.
3 to 8 are cross-sectional views illustrating a wire bonding method according to an embodiment of the present invention.
FIG. 9 is an image of wire bonding structures manufactured according to an embodiment of the present invention taken at various angles through SEM equipment.
10A to 10G are cross-sectional views illustrating a wire bonding process applicable to the wire bonding method according to an embodiment of the present invention.

The wire bonding structure of the present invention is a wire bonding structure in which one end of a plurality of conductive wires is ball-bonded to different input / output pads and one end of the plurality of conductive wires is formed at one stitch position ) To be bonded in a multilayer structure.

As described above, the wire bonding structure of the present invention uses a bump ball to form a multi-layered structure in which a plurality of conductive wires are piled up at one stitch position on the lead surface, Design constraints due to the arrangement disappear, and it is advantageous to miniaturize the semiconductor package without changing the lead length, and the design constraint in the PCB production is reduced. In addition, the PCB manufacturing cost is reduced by the short lead length.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention.

FIG. 2A is a cross-sectional view illustrating a wire bonding structure according to an embodiment of the present invention, and FIG. 2B is a plan view of the wire bonding structure shown in FIG. 2A.

2A and 2B, a conductive wiring pattern including a plurality of leads 110-1 to 110-7 to 110-13 is formed on a surface of the supertor 100 . The supersatellite 100 may be a rigid printed circuit board, a flexible circuit film, a flexible circuit tape, a lead frame or an equivalent thereof, no.

Each of the leads 110-1, 110-7, ..., 110-13 formed on the surface of the supertor 100 has a length of each lead 30 shown in FIG. 1B L1 is formed to have a relatively short length L2.

A semiconductor chip 120 having a plurality of input / output pads 120-1, ..., 120-8, 120-9, 120-10, ..., 120-17 formed on the superty 100, Respectively.

One end of the first conductive wire 115-1 is ball-bonded to an input / output pad 120-8 (hereinafter referred to as a first input / output pad) of the semiconductor chip 120, The other end of the staple position 115-1 is positioned at one stitch position (or position) on the lead 110-7 of one of the plurality of leads 110-1, ..., 110-7, ..., Stitch Position: SP).

The first bump ball B1 is formed on the other end of the stitch-bonded first conductive wire 115-1.

One end of the second conductive wire 115-2 is ball-bonded to the second input / output pad 120-9 adjacent to the first input / output pad 120-8 and the other end of the second conductive wire 115-2 is ball- And the ends are stitch-bonded on the formed first bump balls B1.

A second bump ball B2 is formed on the first bump ball B2 to which the other end of the second conductive wire 115-2 is stitch-bonded.

One end of the third conductive wire 115-3 is ball-bonded to the third input / output pad 120-10 adjacent to the second input / output pad 120-9, and the other end of the third conductive wire 115-3 is ball- And the end portion is stitch bonded onto the second bump ball B2.

A third bump ball B3 is formed on the second bump ball B2 to which the other end of the third conductive wire 115-3 is stitch-bonded.

As described above, the wire bonding structure according to an embodiment of the present invention is characterized in that one end of each of the first to third conductive wires 115-1, 115-2, and 115-3 has different input / output pads 120-8 and 120- 9 and 120-10 and the other ends of the conductive wires 115-1, 115-2 and 115-3 are piled up at one stitch position specified on the surface of one lead 110-7 Structure.

Due to such a bonding structure, there are no design limitations in terms of lead length and arrangement when multi-bonding bonding two or more wires.

And free from the pressure for making large size leads for multi-bonding. In addition, the arrangement of the leads is made uniform, thereby reducing the wire angle.

In addition, fine pitch leads can be manufactured and bonded, and as a result, fineness of the lead width can be reduced, thereby reducing the production cost of the PCB.

Hereinafter, a wire bonding method according to an embodiment of the present invention will be described with reference to FIGS. 3A and 3G. FIG.

The wire bonding method according to an embodiment of the present invention can be largely divided into a die attach process of FIG. 3 and a wire bonding process of FIGS.

Referring to FIG. 3, a die attach process according to an embodiment of the present invention is a process of bonding a semiconductor chip 120 to a supertor 100, and a semiconductor chip 120) is adhered onto the supertor (100).

The wire bond process after the die attach process can be roughly classified into six process steps. This is for the purpose of understanding and simplifying the description, but is not intended to limit the invention to the six process steps. It will thus be appreciated by those skilled in the art that, in some cases, some process steps may be categorized into a single process step, of course.

When the die attach process is completed, first, the primary wire bonding process of FIG. 4 proceeds.

In the primary wire bonding process, one end of the first conductive wire 115-1 is ball-bonded to one of the input / output pads (120-8 of Fig. 2B) of the semiconductor chip 120, 0.0 > 110-7 < / RTI >

Bonding equipment such as capillary, wire clamp, etc. may be used to perform this primary wire bonding process.

The primary wire bonding process will be described below with reference to FIGS. 10A to 10G.

First, as shown in FIG. 10A, a first conductive wire 115-1 formed with a metal ball 16 is protected by a capillary 10 and stands on an input / output pad (120-8 of FIG. 2B) . Reference numeral 14 denotes a wire clamp.

Thereafter, as shown in FIG. 10B, a first conductive wire 115-1 having a ball is placed on the input / output pad (120-8 of FIG. 2B) by the capillary 10, The ball formed on the pad 10 contacts the surface of the input / output pad (120-8 of Fig. 2B) with an appropriate load.

Then, after the balls are brought into contact, the capillary 10 is ultrasonically vibrated, and energy is generated between the ball and the metal material of the input / output pad (120-8 of FIG. 2B) So that a bond for ball bonding can be obtained.

Thereafter, as shown in FIGS. 10C and 10D, the capillary 10 forms a loop height on the ball-bonded input / output pad 120-8 while drawing a proper orbit , And leads 110-7 formed on the superty 100 for stitch bonding.

Then, as shown in FIG. 10E, the stitch bonding 19 is performed on the lead 110-7 of the supertwale 100. FIG. At this time as well as ball bonding, an appropriate load and ultrasonic vibration can be applied for bonding.

The capillary 10 is lifted and the wire clamp 14 catches the first conductive wire 115-1 in the capillary 10 and thereby the first conductive wire 115-1 Is cut off after being stitch bonded, thereby completing the primary wire bonding process of FIG.

5, when the first wire bonding process shown in FIG. 4 is completed, the first conductive wire 115-1 is connected to the stitch-bonded portion of the first conductive wire 115-1, The bump ball forming process proceeds.

10F, the electric torch 6 is moved to the lower end of the first conductive wire 115-1 under the capillary 10, Causing a discharge (8).

Next, as shown in Fig. 10G, the wire connected to the capillary 10 by the electric discharge forms the ball 16.

Thereafter, the formed ball 16 is bonded to the stitch-bonded portion of the other end of the first conductive wire 115-1 by heat, pressure, and ultrasonic waves, and then the wire is pulled by the wire clamp 14 A bump ball B1 as shown in Fig. 5 is formed on the stitch-bonded portion of the other end of the first conductive wire 115-1.

When the first bump ball forming process as shown in FIG. 5 is completed, a secondary wire bonding process as shown in FIG. 6 is performed.

In the secondary wire bonding process, one end of the second conductive wire 115-2 is ball-bonded to the second input / output pad (120-9 of FIG. 2B) adjacent to the first input / output pad (120-8 of FIG. 2B) And the other end of the second conductive wire 115-2 is stitch bonded to the first bump ball B1 formed by the first bump ball forming process.

The second wire bonding process differs from the second wire bonding process in that the area where the other end of the second conductive wire 115-2 is stitch bonded is on the bump ball B1 formed in the first bump ball forming process. Is the same as the primary wire bonding process performed according to Figs. 10A to 10E. Therefore, detailed description of the secondary wire bonding process is omitted.

When the secondary wire bonding process of FIG. 6 is completed, a secondary bump ball forming process in which a secondary bump ball is formed proceeds as shown in FIG.

The second bump ball forming process is also the same as the first bump ball forming process performed in Figs. 10F and 10G described above, except that the second bump ball forming process is on the stitch-bonded region of the other end of the second conductive wire Which is different from the primary bump ball forming process.

When the second bump ball forming process of FIG. 7 is completed, the third wire bonding fixation of FIG. 8 proceeds.

In the third wire bonding process, one end of the third conductive wire 115-3 is ball-bonded to a third input / output pad (120-10 of FIG. 2B) adjacent to the second input / output pad (120-9 of FIG. 2B) And the other end of the third conductive wire 115-3 is stitch bonded to the second bump ball B2. A detailed description thereof will be omitted from the above description, as it can be understood from the foregoing description.

By completion of the above-described third wire bonding process, one ends of the first to third conductive wires 115-1, 115-2, and 115-3 are connected to the input / output pads 120-8, 120-9, and 120-10 And the other end of each of the conductive wires 115-1, 115-2, and 115-3 is stacked in a multilayer structure stacked up from one lead 110-7 surface.

In FIG. 9, the wire bonding structures manufactured according to the wire bonding method described above are photographed at various angles using SEM (E-beam lithography) equipment.

As can be seen from the images of FIG. 9, it can be seen that a good wire bonding structure is shown without a defect that a corresponding lead to which a plurality of conductive wires are bonded and peripheral leads adjacent to the corresponding lead are short-circuited.

By stacking a plurality of conductive wires on the stitch position of one lead surface by using a bump ball in this manner, the design constraint according to the lead arrangement and the conductive wire arrangement disappears, and the lead length It is advantageous to miniaturize the semiconductor package without change and the design constraint is reduced when the PCB is manufactured. In addition, the PCB manufacturing cost is reduced by the short lead length.

As described above, the wire bonding structure according to the present invention is not limited to the configuration and method of the embodiments described above, but various modifications can be made to the embodiments. For example, although the bonding structure in which three conductive wires are continuously stacked on one stitch position of the lead surface is exemplified throughout this specification, four or more conductive wires are continuously stacked on one lead position on the lead surface It will be appreciated that the present invention is applicable to a bonding structure in which a plurality of conductive wires are stacked on a substrate, and that the effect obtained by the present invention can be maximized as the number of conductive wires increases.

Claims (5)

  1. A wire bonding structure for electrically connecting a plurality of leads formed on a surface of a substrate to a plurality of input / output pads of a semiconductor chip using a conductive wire,
    A plurality of conductive wires are bonded to one input / output pad by ball bonding, and the other end of the plurality of conductive wires is formed on one lead surface by stitch bonding ) And bonded in a multilayer structure,
    The multi-
    A first conductive wire having the other end stitched to the one lead surface;
    A first bump ball formed on the other end of the first conductive wire;
    A second conductive wire having the other end stitched on the first bump ball;
    A second bump ball formed on the other end of the second conductive wire;
    A third conductive wire having the other end stitched on the second bump ball; And
    A third bump ball formed on the other end of the third conductive wire,
    And a wire bonding structure.
  2. delete
  3. A wire bonding method for electrically connecting a plurality of leads formed on a surface of a substrate to a plurality of input / output pads of a semiconductor chip using a conductive wire,
    Ball bonding one end of the plurality of conductive wires to different input / output pads; And
    And stitch bonding the other ends of the plurality of conductive wires to one stitch position formed on the lead surface to bond the conductive wires in a multilayer structure,
    Wherein the plurality of conductive wires include first through third conductive wires,
    The step of bonding in the multi-
    Stitch bonding the other end of the first conductive wire to the one stitch position;
    Forming a first bump ball on the other end of the stitch-bonded first conductive wire;
    Stitch bonding the other end of the second conductive wire on the first bump ball;
    Forming a second bump ball on the other end of the stitch-bonded second conductive wire;
    Stitch bonding the other end of the third conductive wire on the second bump ball; And
    And forming a third bump ball at the other end of the stitch-bonded third conductive wire.
  4. delete
  5. delete
KR1020140125874A 2014-09-22 2014-09-22 Wire bonding structure and method thereof KR101630180B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020140125874A KR101630180B1 (en) 2014-09-22 2014-09-22 Wire bonding structure and method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020140125874A KR101630180B1 (en) 2014-09-22 2014-09-22 Wire bonding structure and method thereof

Publications (2)

Publication Number Publication Date
KR20160034655A KR20160034655A (en) 2016-03-30
KR101630180B1 true KR101630180B1 (en) 2016-06-14

Family

ID=55660272

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020140125874A KR101630180B1 (en) 2014-09-22 2014-09-22 Wire bonding structure and method thereof

Country Status (1)

Country Link
KR (1) KR101630180B1 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005176004A (en) 2003-12-12 2005-06-30 Sanyo Electric Co Ltd Three-dimensional image display device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020015214A (en) * 2000-08-21 2002-02-27 마이클 디. 오브라이언 Semiconductor package
KR100401020B1 (en) * 2001-03-09 2003-10-08 앰코 테크놀로지 코리아 주식회사 Stacking structure of semiconductor chip and semiconductor package using it
KR100526847B1 (en) * 2003-11-19 2005-11-08 앰코 테크놀로지 코리아 주식회사 Double wire bonding structure of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005176004A (en) 2003-12-12 2005-06-30 Sanyo Electric Co Ltd Three-dimensional image display device

Also Published As

Publication number Publication date
KR20160034655A (en) 2016-03-30

Similar Documents

Publication Publication Date Title
TWI483369B (en) Through silicon via bridge interconnect
JP4416760B2 (en) Stacked package module
JP3935370B2 (en) Bumped semiconductor element manufacturing method, semiconductor device and manufacturing method thereof, circuit board, and electronic device
US20090045497A1 (en) Semiconductor device and method of manufacturing the same
US9171790B2 (en) Package on package devices and methods of packaging semiconductor dies
US20050148175A1 (en) Semiconductor device and manufacturing method thereof
JP3765952B2 (en) Semiconductor device
US20080157397A1 (en) Flip-chip packages and methods of manufacturing the same
JP2004056138A (en) Method of bonding lead frames in package assembly, manufacture of chip laminated package, and chip laminated package
US20040004291A1 (en) Semiconductor device
US8786102B2 (en) Semiconductor device and method of manufacturing the same
JP4014912B2 (en) Semiconductor device
JP2012104790A (en) Semiconductor device
EP0680086B1 (en) Semiconductor device and method of producing said semiconductor device
US8022523B2 (en) Multi-chip stack package
US20080023831A1 (en) Semiconductor device and manufacturing method for the same
KR101227228B1 (en) Wire bond interconnection
CN1246899C (en) The semiconductor device
JP2005526376A (en) Die stacking method and apparatus
CN1197156C (en) Semiconductor Equipment
CN1193424C (en) The semiconductor device
US6259163B1 (en) Bond pad for stress releif between a substrate and an external substrate
JP2007123520A (en) Laminated semiconductor module
CN1266764C (en) Semiconductor device and its producing method
KR20040041635A (en) Semiconducto chip with multiple rows of bond pads

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20190329

Year of fee payment: 4