KR101530896B1 - 핀 인터페이스를 갖는 다층의 배선 요소 - Google Patents

핀 인터페이스를 갖는 다층의 배선 요소 Download PDF

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Publication number
KR101530896B1
KR101530896B1 KR1020107001200A KR20107001200A KR101530896B1 KR 101530896 B1 KR101530896 B1 KR 101530896B1 KR 1020107001200 A KR1020107001200 A KR 1020107001200A KR 20107001200 A KR20107001200 A KR 20107001200A KR 101530896 B1 KR101530896 B1 KR 101530896B1
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South Korea
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conductive
layer
metal layer
interconnecting
forming
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Korean (ko)
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KR20100050457A (ko
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벨가셈 하바
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테세라, 인코포레이티드
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0355—Metal foils
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0361—Etched tri-metal structure, i.e. metal layers or metal patterns on both sides of a different central metal layer which is later at least partly etched
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0384—Etch stop layer, i.e. a buried barrier layer for preventing etching of layers under the etch stop layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
KR1020107001200A 2007-06-29 2008-06-23 핀 인터페이스를 갖는 다층의 배선 요소 Active KR101530896B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/824,484 2007-06-29
US11/824,484 US7911805B2 (en) 2007-06-29 2007-06-29 Multilayer wiring element having pin interface
PCT/US2008/007978 WO2009005696A1 (en) 2007-06-29 2008-06-23 Multilayer wiring element having pin interface

Publications (2)

Publication Number Publication Date
KR20100050457A KR20100050457A (ko) 2010-05-13
KR101530896B1 true KR101530896B1 (ko) 2015-06-23

Family

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Application Number Title Priority Date Filing Date
KR1020107001200A Active KR101530896B1 (ko) 2007-06-29 2008-06-23 핀 인터페이스를 갖는 다층의 배선 요소

Country Status (6)

Country Link
US (1) US7911805B2 (https=)
EP (1) EP2172089B1 (https=)
JP (2) JP5421254B2 (https=)
KR (1) KR101530896B1 (https=)
CN (1) CN101772995B (https=)
WO (1) WO2009005696A1 (https=)

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US8058101B2 (en) 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
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US8238114B2 (en) * 2007-09-20 2012-08-07 Ibiden Co., Ltd. Printed wiring board and method for manufacturing same
US8558379B2 (en) 2007-09-28 2013-10-15 Tessera, Inc. Flip chip interconnection with double post
US20100044860A1 (en) * 2008-08-21 2010-02-25 Tessera Interconnect Materials, Inc. Microelectronic substrate or element having conductive pads and metal posts joined thereto using bond layer
US20100090339A1 (en) * 2008-09-12 2010-04-15 Kumar Ananda H Structures and Methods for Wafer Packages, and Probes
US8330272B2 (en) 2010-07-08 2012-12-11 Tessera, Inc. Microelectronic packages with dual or multiple-etched flip-chip connectors
US9159708B2 (en) 2010-07-19 2015-10-13 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US8580607B2 (en) 2010-07-27 2013-11-12 Tessera, Inc. Microelectronic packages with nanoparticle joining
US8853558B2 (en) 2010-12-10 2014-10-07 Tessera, Inc. Interconnect structure
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Also Published As

Publication number Publication date
CN101772995A (zh) 2010-07-07
US7911805B2 (en) 2011-03-22
EP2172089B1 (en) 2019-08-28
JP2014060431A (ja) 2014-04-03
WO2009005696A1 (en) 2009-01-08
CN101772995B (zh) 2016-07-13
EP2172089A4 (en) 2011-08-10
EP2172089A1 (en) 2010-04-07
JP2010532567A (ja) 2010-10-07
US20090002964A1 (en) 2009-01-01
JP6001524B2 (ja) 2016-10-05
JP5421254B2 (ja) 2014-02-19
KR20100050457A (ko) 2010-05-13

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