KR101469579B1 - Array Substrate of In-Plane Switching Mode Liquid Crystal Display Device - Google Patents

Array Substrate of In-Plane Switching Mode Liquid Crystal Display Device Download PDF

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KR101469579B1
KR101469579B1 KR1020070141725A KR20070141725A KR101469579B1 KR 101469579 B1 KR101469579 B1 KR 101469579B1 KR 1020070141725 A KR1020070141725 A KR 1020070141725A KR 20070141725 A KR20070141725 A KR 20070141725A KR 101469579 B1 KR101469579 B1 KR 101469579B1
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South Korea
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common
electrode
liquid crystal
portion
plurality
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KR1020070141725A
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Korean (ko)
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KR20090073707A (en
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유성수
박선익
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엘지디스플레이 주식회사
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    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1343Electrodes
    • G02F1/134309Electrodes characterised by their geometrical arrangement
    • G02F1/134363Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1343Electrodes
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136286Wiring, e.g. gate line, drain line
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40Arrangements for improving the aperture ratio

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to improving an aperture ratio in an array substrate for a transverse electric field type liquid crystal display device in which a common electrode and a pixel electrode are formed on the same plane.
In accordance with an aspect of the present invention, A gate wiring formed in one direction on the substrate; First and second common wirings arranged in parallel to the gate wirings; A data line crossing the gate line and defining a pixel region; A thin film transistor formed at an intersection of the gate and the data line; A pixel electrode which is in contact with the thin film transistor and includes an extension portion including a plurality of first depressions corresponding to an upper portion overlapped with the second common wiring and a plurality of vertical portions branched vertically in the extension portion; An extension portion which is in contact with the first common wiring and includes a plurality of second depressions corresponding to an upper portion overlapping with the first common wiring, and a common electrode including a plurality of vertical portions branched vertically from the extension portion And an array substrate for a transverse electric field type liquid crystal display device.
The above-described structure is advantageous in that the pixel electrode vertical portion and the common electrode vertical portion can be extended by the first and second common wirings through the first and second depressions designed in the pixel electrode extension portion and the common electrode extension portion, respectively. Accordingly, the aperture ratio can be improved by minimizing the area where the front line due to the abnormal arrangement of the liquid crystal corresponding to the pixel area is minimized.

Description

[0001] The present invention relates to an array substrate for a lateral electric field type liquid crystal display device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to improving an aperture ratio in an array substrate for a transverse electric field type liquid crystal display device in which a common electrode and a pixel electrode are formed on the same plane.

Generally, the driving principle of a liquid crystal display device utilizes the optical anisotropy and polarization properties of a liquid crystal. Since the liquid crystal is thin and long in structure, it has a directionality in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Therefore, when the molecular alignment direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular alignment direction of the liquid crystal due to optical anisotropy, so that image information can be expressed.

Currently, active matrix liquid crystal display (AM-LCD), in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner, has been receiving the most attention because of its excellent resolution and video realization capability.

The liquid crystal display comprises an upper substrate, which is a color filter substrate on which a common electrode is formed, and a lower substrate, which is an array substrate on which pixel electrodes are formed, and is made of liquid crystal filled between the upper and lower substrates.

In such a liquid crystal display device, when the common electrode and the pixel electrode are formed vertically and a method of driving the liquid crystal by the vertical electric field generated by the vertical electric field is used, there is a peak where the transmittance and the aperture ratio are excellent. However, It has disadvantages.

Therefore, a new technology has been proposed to overcome the above-mentioned drawbacks, and the liquid crystal display device described below has an advantage of excellent viewing angle characteristics by a driving method using a transverse electric field.

1 is a plan view showing a unit pixel of a conventional array substrate for a transverse electric field type liquid crystal display device.

As shown in the figure, a gate wiring 20 is formed in one direction on the substrate 10 and a data wiring 30 defining a pixel region P perpendicularly intersecting the gate wiring 20 is formed. The data line 30 has at least one refracting portion.

First and second common wirings 50a and 50b are formed corresponding to the upper side and the lower side spaced apart in parallel to the gate wiring 20, respectively. The first and second common wirings 50a and 50b receive the same common voltage.

A thin film transistor T is formed at a point of intersection of the gate line 20 and the data line 30. The thin film transistor T includes a gate electrode 25 extending from the gate wiring 20 and a semiconductor layer (not shown) formed on the upper portion of the gate electrode 25 and overlapped with the gate electrode 25, A source electrode 32 extending from the wiring 30 and a drain electrode 34 spaced apart from the source electrode 32. [

The semiconductor layer includes an active layer 40 made of pure amorphous silicon (a-Si: H) and an ohmic contact layer (not shown) made of amorphous silicon (n + a-Si: H) containing impurities.

A pixel electrode 70 which is in contact with the drain electrode 34 through a drain contact hole CH1 exposing a part of the drain electrode 34 is formed corresponding to the pixel region P. [ The pixel electrode 70 includes an extended portion 70a that is in contact with the drain electrode 34 and a plurality of vertical portions 70b that are vertically branched to the pixel region P in the extended portion 70a.

A common electrode 80 is formed in contact with the first common wiring 50a through a common contact hole CMH1 exposing a part of the first common wiring 50a. The common electrode 80 includes an extended portion 80a in contact with the first common wiring line 50a and a plurality of vertical portions 80b perpendicularly branched to the pixel region P in the extended portion 80a .

The pixel electrode vertical part 70b and the common electrode vertical part 80b which are arranged in parallel to the data line 30 have at least one refraction part and are alternately repeatedly arranged in the pixel area P. [

The second common line 50b may be a first electrode, the pixel electrode extension 70a overlapped with the first electrode may be a second electrode, A storage capacitor Cst having a dielectric layer made of an insulating film is formed.

At this time, the pixel electrode extension 70a is generally designed to have a rectangular shape for the purpose of ensuring a sufficient storage capacity.

However, the above-described structure causes a problem that a uniform horizontal electric field is not formed between the pixel electrode extension portion 70a and the vertical portion 70b of the pixel electrode adjacent to the common electrode extension portion 80b and the vertical portion 80 of the common electrode. .

This will be described in detail with reference to the accompanying drawings.

FIG. 2 is a plan view showing an enlarged portion corresponding to the storage capacitor, and FIG. 3 is a sectional view taken along the line III-III 'of FIG. 2, showing a state in which the color filter substrate and the array substrate are attached to each other. At this time, the drain electrode and the drain contact hole are not shown, and the storage capacitor portion will be described as an example.

2 and 3, the array substrate 10 and the color filter substrate 5, which are divided into a display area AA and a non-display area NAA, are adhered to each other, and the array substrate 10 And the color filter substrate 5, the liquid crystal layer 15 is interposed. The liquid crystal panel 90 includes the array substrate 10, the color filter substrate 5, and the liquid crystal layer 15.

A second common wiring 50b and a gate insulating film 45 and a protective film 55 covering the second common wiring 50b are formed on the upper surface of the transparent substrate 2 of the array substrate 10 and the protective film 55 The pixel electrode extension portion and the vertical portions 70a and 70b and the common electrode vertical portion 80b formed corresponding to the pixel region P on the common electrode vertical portion 80b, And the lower alignment film 19 covering the portion 80b are sequentially positioned.

At this time, the second common wiring 50b is formed of the same material as the gate wiring (20 in FIG. 1).

On the other hand, a black matrix 12 corresponding to a non-display area NAA of the lower surface of the transparent substrate 1 of the color filter substrate 5, a color filter layer 16 on the black matrix 12, And the upper alignment film 18 under the filter layer 16 are sequentially positioned.

At this time, the liquid crystal 35 positioned in the space between the pixel electrode vertical portion 70b and the common electrode vertical portion 80b with a horizontal electric field between the pixel electrode vertical portion 70b and the common electrode vertical portion 80b, However, the liquid crystal 35 corresponding to the F and G portions causes a problem of generating a front line according to the abnormal arrangement.

(ITO) or indium-zinc-oxide (IZO) is used for the purpose of improving the transmittance of the pixel electrode extension portion, the vertical portions 70a and 70b and the common electrode vertical portion 80b. ) On the same layer with a transparent conductive material.

At this time, there is a problem that it must be designed to be spaced apart from each other at a predetermined interval in order to prevent short-circuit failure between the pixel electrode extension portion and the vertical portions 70a and 70b and the common electrode vertical portion 80b. Particularly, in the process of designing the pixel electrode extension portion 70a and the common electrode vertical portion 80b in a spaced-apart manner, the pixel electrode vertical portion and extension portions 70a and 70b and the common electrode vertical portion 70b, The liquid crystal 35 corresponding to this portion can not be uniformly controlled.

The portion where the front line is generated due to the abnormal arrangement of the liquid crystal 35 not only lowers the transmittance of light but also may cause a defective light beam, and is designed to be shielded by the black matrix 12. As a result, the aperture ratio is inevitably lowered due to the shielding design of the portion corresponding to the F and G portions by the black matrix.

SUMMARY OF THE INVENTION The present invention is conceived to solve the above-described problems, and an object thereof is to improve the aperture ratio by changing the pixel design of the array substrate for a transverse electric field type liquid crystal display device.

According to an aspect of the present invention, there is provided an array substrate for a transverse electric field type liquid crystal display, including: a substrate; A gate wiring formed in one direction on the substrate; First and second common wirings arranged in parallel to the gate wirings; A data line crossing the gate line and defining a pixel region; A thin film transistor formed at an intersection of the gate and the data line; A pixel electrode which is in contact with the thin film transistor and includes an extension portion including a plurality of first depressions corresponding to an upper portion overlapped with the second common wiring and a plurality of vertical portions branched vertically in the extension portion; An extension portion that is in contact with the first common wiring and includes a plurality of second depressions corresponding to an upper portion overlapping with the first common wiring and a plurality of vertical portions that are vertically branched from the extension portion, And the second common wiring are formed to face each other with the pixel region therebetween, and are separated from each other on the pixel region, and one end of each of the plurality of vertical portions of the pixel electrode is connected to the plurality of second recesses And one end of each of the plurality of vertical portions of the common electrode is located in a one-to-one correspondence with each of the plurality of first depressions, Wherein a vertical portion of the pixel electrode is adjacent to the data line at an outermost portion of the pixel region, Vertically in the vertical section and the common electrode portion characterized by alternately arranged to each other.

At this time, the first and second depressions are vacant spaces patterned by the mask in the step of forming the common electrode with the pixel electrode. The first and second depressions may be designed as polygons including a rectangle.

Wherein the pixel electrode and the common electrode are selected from a group of transparent conductive metal materials including indium-tin-oxide or indium-zinc-oxide in the same layer.

The first and second common wirings receive the same common voltage from the common voltage generator. In this case, the second common wiring may be used as a first electrode, the pixel electrode extending portion which overlaps with the second common wiring may be used as a second electrode, and the first common electrode, And a storage capacitor in which an interposed dielectric film is a dielectric layer is formed.

The present invention has an advantage that the aperture ratio can be improved by extending the vertical portion of the common electrode and the vertical portion of the pixel electrode to an upper portion overlapping the first and second common wirings.

--- Example ---

Even if the ends of each of the pixel electrode vertical portion and the common electrode vertical portion are extended to the upper portion overlapping the first and second common wirings through a plurality of depressions designed in the pixel electrode extension portion and the vertical portion of the common electrode, A pixel design capable of improving the aperture ratio can be provided.

Hereinafter, an array substrate for a transverse electric field type liquid crystal display device according to the present invention will be described with reference to the accompanying drawings.

4 is a plan view showing a unit pixel of an array substrate for a transversal electric field type liquid crystal display device according to the present invention.

As shown in the figure, a gate wiring 120 is formed in one direction on the substrate 110 and a data wiring 130 defining a pixel region P perpendicularly intersecting the gate wiring 120 is formed. The data line 130 has at least one refracting portion.

The first and second common wirings 150a and 150b are configured to correspond to the upper side and the lower side spaced apart in parallel to the gate wiring 120, respectively. The first and second common wirings 150a and 150b receive the same common voltage from a common voltage generating unit (not shown).

A thin film transistor T is formed at an intersection of the gate line 120 and the data line 130. The thin film transistor T includes a gate electrode 125 extending from the gate wiring 120, a semiconductor layer (not shown) formed on the upper portion of the gate electrode 125 and overlapping the gate electrode 125, A source electrode 132 extending from the wiring 130 and a drain electrode 134 spaced apart from the source electrode 132.

The semiconductor layer includes an active layer 140 made of pure amorphous silicon (a-Si: H) and an ohmic contact layer (not shown) made of amorphous silicon (n + a-Si: H) containing impurities.

The pixel electrode 170 is formed to correspond to the pixel region P in contact with the drain electrode 134 through a drain contact hole CH2 exposing a part of the drain electrode 134. [ The pixel electrode 170 includes an extension portion 170a contacting the drain electrode 134 and including first and second depressions T1 and T2 and a pixel region P extending from the extension portion 170a. And includes a plurality of vertically branched vertical portions 170b.

The common electrode 180 is formed in contact with the first common wiring 150a through a common contact hole CMH2 exposing a part of the first common wiring 150a. The common electrode 180 includes an extended portion 180a which is in contact with the first common wiring line 150a and includes third, fourth and fifth depressions T3, T4 and T5, And a plurality of vertical portions 180b vertically branched from the pixel region P to the pixel region P.

The first and second depressions T1 and T2 of the pixel electrode extension 170a and the third, fourth and fifth depressions T3, T4 and T5 of the common electrode extension 180b And corresponds to an empty space patterned by the mask in the step of forming the pixel electrode 170 and the common electrode 180.

At this time, the first and second depressions T1 and T2 of the pixel electrode extension 170a and the third, fourth and fifth depressions T3, T4, and T5 of the common electrode extension 180b, Is designed as a rectangular shape, but this is merely an example, and it can be designed as a polygonal shape including a rectangle.

Particularly, in the present invention, the pixel electrode vertical portion 170b is formed by the first through fifth depressions T1, T2, T3, T4, and T5 designed in the pixel electrode extension portion 170a and the common electrode extension portion 180a, And the common electrode vertical portion 180b are extended to the upper portions overlapping the first and second common wirings 150a and 150b, short-circuit failure is not generated.

That is, the first through fifth depressions T1, T2, T3, T4, T5, and T6 are preferably formed in a design range in which short-circuit failure does not occur between the pixel electrode 170 and the common electrode 180 .

The pixel electrode vertical part 170b and the common electrode vertical part 180b which are arranged in parallel to the data line 130 have at least one refraction part and are alternately repeatedly arranged in the pixel area P. [

At this time, the second common wiring 150b is used as a first electrode, the pixel electrode extension part 170a overlapping the first electrode is used as a second electrode, and the overlapping interspace between the first and second electrodes A storage capacitor Cst having a dielectric layer interposed therebetween is constituted.

In the above-described configuration, the ends of each of the pixel electrode vertical portion 170b and the common electrode vertical portion 180b are connected to the first and second common wirings via the first through fifth depressions T1, T2, T3, T4, and T5, It is advantageous that the aperture ratio can be improved due to the advantage that the short failure is not generated even if it is designed to be extended to the upper portion overlapping with the first and second electrodes 150a and 150b.

This will be described in detail with reference to the accompanying drawings.

FIG. 5 is an enlarged plan view of a portion corresponding to the storage capacitor, and FIG. 6 is a cross-sectional view taken along the line VI-VI 'of FIG. 5, showing a state in which the color filter substrate and the array substrate are bonded to each other. At this time, the drain electrode and the drain contact hole are not shown, and the storage capacitor portion will be described as an example.

As shown in FIGS. 5 and 6, the array substrate 110 and the color filter substrate 105, which are divided into the display area AA and the non-display area NAA, ) And the color filter substrate 105, the liquid crystal layer 115 is interposed. The liquid crystal panel 190 includes the array substrate 110, the color filter substrate 105, and the liquid crystal layer 115.

A second common wiring 150b and a gate insulating film 145 and a protective film 155 covering the second common wiring 150b are formed on the upper surface of the transparent substrate 102 of the array substrate 110 and the protective film 155 The pixel electrode extension portion and the vertical portions 170a and 170b and the common electrode vertical portion 180b formed corresponding to the pixel region P on the common electrode vertical portion 180a, And the lower alignment film 119 covering the portion 180b are sequentially positioned.

At this time, the second common wiring 150b is formed of the same material as the gate wiring (120 in FIG. 4).

On the other hand, a black matrix 112 corresponding to a non-display area NAA of the lower surface of the transparent substrate 101 of the color filter substrate 105, a color filter layer 116 on the black matrix 112, And an upper alignment layer 118 under the filter layer 116 are sequentially disposed.

The pixel electrode extension portion and the vertical portions 170a and 170b and the common electrode vertical portion 180b are formed of a transparent material containing indium-tin-oxide (ITO) or indium-zinc- oxide (IZO) And is formed on the same layer with a conductive material.

At this time, in the present invention, the ends of the common electrode vertical portion 180b are overlapped with the second common wiring 150b by the first and second depressions T1 and T2 designed in the pixel electrode extension portion 170a The distance between the pixel electrode vertical portion 170b and the common electrode vertical portion 180b corresponding to the pixel region P can be uniformly secured. That is, in the present invention, F and G portions corresponding to the conventional storage capacitor (Cst in FIG. 2) are not generated.

A uniform horizontal electric field can be secured up to a portion corresponding to the pixel electrode vertical portion 170b and the end portion of the common electrode vertical portion 180b so that the pixel electrode vertical portion 170b corresponding to the first half of the pixel region P, And the liquid crystal 135 located in the space between the common electrode vertical portion 180b and the common electrode vertical portion 180b.

Accordingly, in the present invention, since the F and G portions corresponding to the conventional storage capacitor (Cst in FIG. 2) are designed to correspond to the second common wiring 150b, the aperture ratio is improved by the area corresponding to the F and G portions .

However, it should be understood that the present invention is not limited to the above-described embodiment, and various changes and modifications may be made without departing from the spirit and scope of the present invention.

1 is a plan view showing a unit pixel of a conventional array substrate for a transverse electric field type liquid crystal display.

2 is an enlarged plan view of a portion corresponding to the storage capacitor;

3 is a cross-sectional view taken along line III-III 'of FIG.

4 is a plan view showing a unit pixel of an array substrate for a transverse electric field type liquid crystal display device according to the present invention.

5 is an enlarged plan view of a portion corresponding to the storage capacitor;

6 is a cross-sectional view taken along the line VI-VI 'of FIG. 5;

Description of the Related Art [0002]

110: substrate 135: liquid crystal

150b: second common wiring 170: pixel electrode

180b: pixel electrode vertical portion T1, T2: first and second depressed portions

P: pixel region Cst: storage capacitor

Claims (7)

  1. Claims [1]
    A gate wiring formed in one direction on the substrate;
    First and second common wirings arranged in parallel to the gate wirings;
    A data line crossing the gate line and defining a pixel region;
    A thin film transistor formed at an intersection of the gate and the data line;
    A pixel electrode which is in contact with the thin film transistor and includes an extension portion including a plurality of first depressions corresponding to an upper portion overlapped with the second common wiring and a plurality of vertical portions branched vertically in the extension portion;
    An extension portion which is in contact with the first common wiring and includes a plurality of second depressions corresponding to an upper portion overlapping with the first common wiring, and a common electrode including a plurality of vertical portions branched vertically from the extension portion and,
    Wherein the first and second common wirings are formed to face each other with the pixel region therebetween, and are separated from each other on the pixel region, and one end of each of the plurality of vertical portions of the pixel electrode is connected to the plurality And one end of each of the plurality of vertical portions of the common electrode is located in a one-to-one correspondence with each of the plurality of first depressions, And the vertical portion of the pixel electrode and the vertical portion of the common electrode alternate with each other in the outermost portion of the pixel region, Wherein the liquid crystal display device is a liquid crystal display device.
  2. The method according to claim 1,
    Wherein the first and second depressions are empty spaces patterned by a mask in the step of forming the common electrode with the pixel electrode.
  3. 3. The method of claim 2,
    Wherein the first and second depressions are designed as a polygon including a rectangle.
  4. The method according to claim 1,
    Wherein the pixel electrode and the common electrode are formed of the same material of the same layer.
  5. 5. The method of claim 4,
    Wherein the same material is selected from the group of transparent conductive metal materials including indium-tin-oxide or indium-zinc-oxide.
  6. The method according to claim 1,
    Wherein the first and second common wirings receive the same common voltage from the common voltage generating unit.
  7. The method according to claim 1,
    Wherein the second common wiring is a first electrode and the pixel electrode extending portion which overlaps with the second common wiring is a second electrode, And a storage capacitor having an insulating film as a dielectric layer.
KR1020070141725A 2007-12-31 2007-12-31 Array Substrate of In-Plane Switching Mode Liquid Crystal Display Device KR101469579B1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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JP2003207803A (en) * 2002-01-10 2003-07-25 Nec Corp In-plane switching mode active matrix liquid crystal display device
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