KR101427578B1 - Thin film transistor array panel and fabricating method thereof, and flat panel display with the same - Google Patents

Abstract

The present invention relates to a thin film transistor panel, a method of manufacturing the same, and a flat panel display having the same, wherein the thin film transistor panel comprises a substrate, a gate line extending in the first direction and having a gate electrode, A gate insulating film covering the gate line, a data line formed on the gate insulating film and extending in a second direction intersecting with the gate line, a source electrode connected to the data line, A bank having an electrode and a drain electrode opposed to the source electrode and facing each other, and a first hole exposing the source electrode and the drain electrode, the bank being plasma-treated and containing fluorine, The source electrode and the drain It is connected to the semiconductor electrode to form a channel protection film that covers the banks and the semiconductor, and is formed on the protective film, and includes a pixel electrode connected with the drain electrode. Since the ink contact angle of the bank of the thin film transistor display panel having such a structure is increased as compared with that of the gate insulating film, the semiconductor can be accurately formed using the inkjet method.

Thin film transistor, aperture ratio, inkjet, fluorine plasma, top pixel, bottom gate,

Description

TECHNICAL FIELD [0001] The present invention relates to a thin film transistor (TFT) display panel, a method of manufacturing the same, and a flat panel display device having the display panel.

The present invention relates to a thin film transistor display panel, a method of manufacturing the same, and a flat panel display device having the display panel.

In general, a flat panel display device is a substantially flat display device that is thin and driven at a low voltage. Such a flat panel display device includes a liquid crystal display device and an electrophoretic display device.

Such a flat panel display device has a thin film transistor panel in which a thin film transistor (TFT) is formed as a switching element though the detailed structure differs depending on the type.

The thin film transistor includes an inorganic semiconductor or an organic semiconductor for forming a channel which is a current flow passage between a source electrode and a drain electrode. Recently, a method of dropping an ink containing an organic semiconductor material by an inkjet method to form an organic semiconductor Is being developed.

However, it is not easy to effectively form an inorganic semiconductor or an organic semiconductor having a fine pattern due to limitations of the apparatus. Therefore, a technique of forming a bank having a hole in a thin film transistor display panel, then advancing the ink jet to selectively allow ink to enter into the hole is mainly used.

With this technique, there is a method of changing the contact angle of the ink inside and outside the hole of the bank through the plasma treatment. However, this method can not be used when the material of the inside and the outside of the bank is the same. In addition, although the material constituting the bank itself has a larger contact angle with respect to ink than the material constituting the bottom of the bank hole, a material having a sufficient contact angle has not been developed yet.

Disclosure of Invention Technical Problem [8] The present invention provides a thin film transistor display panel including a semiconductor formed in a precise pattern without channel damage.

A further object of the present invention is to provide a method of manufacturing a thin film transistor display panel capable of forming a semiconductor in a precise pattern without damaging a channel in a thin film transistor display panel using an organic film as a gate insulating film.

Another aspect of the present invention is to provide a flat panel display having the thin film transistor display panel.

According to an aspect of the present invention, there is provided a thin film transistor display panel including a substrate, gate lines extending in a first direction and having gate electrodes, gate lines formed on the gate lines, A data line extending in a second direction intersecting with the gate line; a source electrode connected to the data line; and a gate electrode formed on the gate electrode, A bank formed on the source electrode and the drain electrode and having a first hole exposing the source electrode and the drain electrode, a bank formed in the first hole, the source electrode and the drain electrode, A semiconductor connected to form a channel, And a pixel electrode formed on the passivation layer and connected to the drain electrode.

And a portion of the fluorine-containing gate insulating film includes a planar ring-shaped region formed along an inner edge of the first hole.

The bank is plasma-treated to contain fluorine, and the gate insulating film is formed of an organic film.

The data line includes a first conductive layer including a transparent conductive oxide and a second conductive layer including a metal. The portion of the source electrode and the drain electrode located within the first hole may include the first conductive layer, and the portion covered by the bank may include a first conductive layer and a second conductive layer.

The thin film transistor display panel according to an embodiment of the present invention further includes a contact assistant member formed on the gate insulating film and in contact with an end portion of the gate line through a contact hole and composed of the first conductive layer.

The data line has a wide end portion formed of the first conductive layer and a portion of the gate insulating film containing fluorine includes the peripheral region of the contact assistant member and the wide end portion of the data line.

The first hole is formed on the gate electrode in a smaller area than the gate electrode.

The pixel electrode covers the semiconductor, and the pixel electrode is made of an opaque metal material.

A second hole exposing a part of the drain electrode is formed in the bank, and the pixel electrode is connected to the drain electrode through the second hole.

According to an aspect of the present invention, there is provided a method of manufacturing a thin film transistor panel, including the steps of: A) forming a gate line including a gate electrode on a substrate; b) forming a gate insulating layer covering the gate line (C) continuously depositing a first conductive layer and a second conductive layer on the gate insulating layer, (D) patterning the first conductive layer and the second conductive layer to form the first conductive layer and the second conductive layer A source electrode and a drain electrode, a data line including a conductive layer, and a blocking portion located above the gate electrode and connected to the source and drain electrodes, the blocking portion being formed of the first conductive layer, E) Forming a bank having a drain electrode and a first hole exposing the blocking portion, F) performing a fluorine plasma treatment, G) Removing the blocking portion by etching the first conductive layer using the second conductive layer exposed through the first hole as a mask; H) forming a semiconductor inside the first hole; I) And forming a protective film covering the semiconductor, and J) forming a pixel electrode on the protective film.

The semiconductor may be formed by dropping a semiconductor material by an inkjet method.

(D) forming a first photoresist pattern by applying a photoresist over the second conductive layer and exposing and developing the photoresist using a halftone mask to form a first photoresist pattern; (D-2) Forming a pattern including a first conductive layer and a second conductive layer around a portion where the data line and the source electrode and the drain electrode are to be formed and the source electrode and the drain electrode by performing etching using the pattern as a mask; ) Forming a second photoresist pattern by etching back the first photoresist pattern, D-4) performing etching using the second photoresist pattern as a mask to form a second photoresist pattern on the second conductive layer Removing the remaining portions except the portion where the source electrode and the drain electrode are to be formed, and D-5) removing the second photoresist pattern.

In the step D-2), the first conductive layer and the second conductive layer are left on the gate electrode at a smaller area than the gate electrode.

In the step E), the first hole is formed on the gate electrode at an area larger than the first conductive layer and the second conductive layer remaining on the gate electrode and smaller than the gate electrode.

In step E), a second hole exposing a part of the drain electrode is formed. In step I), holes aligned with the second hole are formed. In step J), the second hole And the pixel electrode is connected to the drain electrode.

The method of manufacturing a thin film transistor panel according to an exemplary embodiment of the present invention may further include the step of removing the second conductive layer exposed inside the first hole using the bank as a mask, H). ≪ / RTI >

In this case, in the step (D), a contact assistant member including the first conductive layer and the second conductive layer and connected to the wide end of the gate line is further formed, and in the step G-1) The second conductive layer is removed.

According to an aspect of the present invention, there is provided a flat panel display comprising a thin film transistor panel, a common electrode panel opposing the thin film transistor panel, and a thin film transistor panel between the thin film transistor panel and the common electrode panel. And electrophoretic particles disposed in the electrophoretic particles.

As described above, since the thin film transistor panel according to the embodiment of the present invention is plasma-processed so that the banks contain fluorine, when the ink is dripped by the inkjet method, the ink is effectively formed in the first hole of the bank. Therefore, deterioration of characteristics and pixel defects of the thin film transistor can be prevented

Further, since the gate insulating film made of an organic film hardly affects the plasma processing, the semiconductor characteristics are prevented from being deteriorated due to the damage caused by the plasma processing.

Since the electrode portion of the gate electrode is formed to have a larger area than the first hole of the bank, photo leakage caused by light incident from the lower side of the substrate can be prevented.

Further, since the pixel electrode is formed on the uppermost layer of the thin film transistor display panel, it is possible to increase the size of the first hole and the size of the source electrode and the drain electrode, in which the semiconductor is attached, irrespective of the aperture ratio. Therefore, the width ratio (W / L) of the width of the semiconductor to the channel length can be increased to increase the on current (Ion), thereby improving the characteristics of the thin film transistor.

In addition, the aperture ratio can be improved by arranging the pixel electrodes to the top of the thin film transistor and the bank to maximize the area that can contribute to display.

Further, when a lamination process is performed to use the thin film transistor display panel having the above-described structure for use in an electrophoretic display device, it is possible to prevent deterioration of characteristics of the thin film transistor due to permeation of the adhesive component into the semiconductor.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, which will be readily apparent to those skilled in the art to which the present invention pertains. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

In the drawings, the thickness is enlarged to clearly represent the layers and regions. Like parts are designated with like reference numerals throughout the specification. When a portion of a layer, a film, a region, a plate, or the like is on another portion, it includes not only the portion directly above another portion but also the case where another portion exists in the middle. Conversely, when a part is directly above another part, it means that there is no other part in the middle.

<Examples>

Hereinafter, a thin film transistor panel according to an embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2. FIG.

FIG. 1 is a layout diagram of a thin film transistor panel according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line II-II and II'-II 'of FIG.

A plurality of gate lines 121 are formed on an insulating substrate 110 made of transparent glass, silicone or plastic.

The gate line 121 transmits a gate signal, and extends mainly in a first direction (the horizontal direction in Fig. 1). The gate line 121 includes a gate electrode 124 extending in a second direction (vertical direction in FIG. 1).

The gate electrode 124 includes a connection portion 124a and an electrode portion 124b and the electrode portion 124b has a width wider in the first direction and the second direction than the connection portion 124a. However, the connection portion 124a may be formed to have the same width as the electrode portion 124b, and the gate line 121 may extend vertically to form the gate electrode 124. [

Although only one gate line 121 is shown in FIGS. 1 and 2, a plurality of gate lines 121 are formed on the insulating substrate 110.

Each of the gate lines 121 includes a wide end portion 129 for connection with another layer or an external driving circuit.

A gate drive circuit (not shown) for generating a gate signal may be mounted on a flexible printed circuit (not shown) attached to the substrate 110, directly mounted on the substrate 110, 0.0 &gt; 110 &lt; / RTI &gt;

When the gate driving circuit is integrated on the substrate 110, the gate line 121 may extend and be directly connected thereto.

It is preferable that the electrode portion 124b of the gate electrode 124 be formed to be large enough to cover most of the pixel region because the area of the electrode portion 124b is increased, (W / L) can be increased.

As described above, when the width ratio (W / L) to the channel length of the semiconductor is increased, the on current (Ion) of the thin film transistor is increased, thereby improving the characteristics of the thin film transistor.

The gate line 121 and the gate electrode 124 may be formed of an aluminum-based metal such as aluminum (Al) or aluminum alloy, a copper-based metal such as copper (Cu) Such as molybdenum metal such as molybdenum (Mo) or molybdenum alloy, chromium (Cr), tantalum (Ta), titanium (Ti), and tungsten (W).

However, the gate line 121 and the gate electrode 124 may have a multi-film structure including two conductive films (not shown) having different physical properties. For example, the gate line 121 and the gate electrode 124 may be made of a transparent conductive oxide such as ITO or IZO and a double conductive film of a low-resistance metal.

A gate insulating layer 140 having contact holes 141 exposing the end portions 129 of the gate lines is formed on the gate lines 121 and the gate electrodes 124.

The gate insulating film 140 may be formed of an organic insulating film made of a soluble polymer such as polyimide, polyvinyl alcohol, fluorane-containing compound, or parylene, or an inorganic insulating film such as silicon nitride Lt; / RTI &gt;

A data line 171 including a plurality of source electrodes 173, a drain electrode 175 and a contact assistant member 172 are formed on the gate insulating layer 140 .

The data line 171 transmits a data signal and extends mainly in the vertical direction and crosses the gate line 121.

Each source electrode 173 includes a linear portion extending toward the electrode portion 124b of the gate electrode 124 and an extension extending in the second direction at the end of the linear portion.

The data line 171 also includes a wide end portion 179 having a wide width for connection with another layer or an external driving circuit.

A data driving circuit (not shown) for generating a data signal may be mounted on a flexible printed circuit board (not shown) attached to the substrate 110, directly mounted on the substrate 110, .

When the data driving circuit is integrated on the substrate 110, the data line 171 can extend and be directly connected thereto.

The drain electrode 175 formed in an island type includes a linear portion formed in the first direction and an extending portion extending in the vertical direction at the end of the linear portion. The extension of the drain electrode 175 is aligned with the extension of the source electrode 173 and facing each other.

The extended portion of the source electrode 173 and the extended portion of the drain electrode 175 are formed as long as possible within a range that does not exceed the vertical length of the electrode portion 124b.

Accordingly, the width ratio (W / L) of the semiconductor to the channel length can be increased, thereby improving the characteristics of the thin film transistor.

The data line 171 has a multi-film structure including two conductive films (not shown) having different physical properties.

The lower first conductive layer 171p may be made of a transparent conductive oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO).

The upper second conductive layer 171q may be made of a molybdenum-based metal such as molybdenum (Mo) or molybdenum alloy, or an aluminum-based metal such as aluminum (Al) or aluminum alloy.

The second conductive layer 171q may be formed of a silver-based metal such as silver or a silver alloy, a gold-based metal such as gold (Au) or a gold alloy, a copper-based metal such as copper (Cu) , Chromium (Cr), titanium (Ti), tantalum (Ta), or the like.

Here, the wide end portion 179 of the data line 171 is made of only the first conductive layer made of a transparent conductive oxide.

The source electrode 173 is composed of a first conductive layer 173p and a second conductive layer 173q like the data line 171. A first conductive layer 173p is formed in a portion in contact with the semiconductor 154, Only.

Likewise, the drain electrode 175 is also formed of the first conductive layer 175p and the second conductive layer 175q, and only the first conductive layer 175p is left in a portion in contact with the semiconductor 154. [

The contact-assistant member 172 is also made of only the first conductive layer.

The first conductive layers 171p, 173p, and 175p of the data line 171 and the source electrode 173 and the drain electrode 175 are made of the same material, for example, a transparent conductive oxide, and the wide end portions 179 And the contact assistant member 172 are also made of the same transparent conductive oxide as the first conductive layer.

The formation of only a portion of the source electrode 173 and the drain electrode 175 (a portion where the semiconductor contacts), the wide end portion 179 and the contact assistant member 172 are formed only of the transparent conductive oxide, It is not necessary to selectively remove the second conductive layer when the second conductive layer is formed of a material having a good contact property with the top film.

On the other hand, on the substrate 110 on which the data line 171, the source electrode 173, and the drain electrode 175 are formed, a bank 146 is formed.

The bank 146 has a first hole 147 and a drain electrode 175 that have an area slightly smaller than the electrode portion 124b of the gate electrode 124 and expose a portion of the source electrode 173 and the drain electrode 175, 175 which exposes the linear end portions of the first and second openings.

The size of the first hole 147 is smaller than that of the electrode portion 124b because the semiconductor 154 filled in the first hole 147 is directly exposed to the light coming from the lower portion of the substrate 110 This is to prevent the occurrence of photo leakage.

The source electrode 173 and the drain electrode 175 exposed through the first hole 147 of the bank 146 are formed only of the first conductive layers 173p and 175p. The boundary where the first conductive layers 173p and 175p are exposed after the second conductive layers 173q and 175q of the source electrode 173 and the drain electrode 175 are removed is formed in the first hole And substantially coincides with the boundary of the first region 147.

Although the first hole 147 is formed in a rectangular shape in FIG. 1, the first hole 147 may be formed in an elliptical shape or a circular shape.

A semiconductor 154 is formed inside the first hole 147. Semiconductor 154 may comprise an organic semiconductor, a nano particle, or an inorganic semiconductor.

Herein, the inorganic semiconductor includes silicon (Si), and the organic semiconductor includes an oligomer or polymer having a structure capable of easily transferring electrons such as a conjugated system.

The organic semiconductor may be composed of a low-molecular compound or a polymer compound dissolved in an aqueous solution or an organic solvent. In order to apply a low-solubility low-molecular compound to a solution process, a hydrophilic or hydrophobic functional group is bonded to the low- Or derivatives thereof.

Here, the semiconductor 154 is deposited on the inside of the hole 147 with the same area as the area of the first hole 147, and a part of the semiconductor 154 overlaps with the source electrode 173 and the drain electrode 175 .

The gate electrode 124, the source electrode 173 and the drain electrode 175 constitute one thin film transistor together with the semiconductor 154 and the channel of the thin film transistor is connected to the source electrode 173, And the drain electrode 175, as shown in FIG.

The semiconductor 154 is formed by dripping an ink containing a semiconductor material by an inkjet method into the first hole 147. However, when the semiconductor 154 is formed using the inkjet method, it is important that the dropped ink is effectively patterned.

Accordingly, in order to effectively pattern the semiconductor 154, the bank 146 is treated with a fluorine-containing plasma and contains fluorine therein. The fluorine increases the contact angle of the ink with respect to the bank 146 when the semiconductor 154 is formed by the ink jet method. That is, the ink is prevented from getting wet on the surface of the bank 146 and guided to flow into the first hole 147. Thus, the semiconductor 154 is effectively patterned in the interior of the first hole 147.

At this time, fluorine is also contained in the gate insulating film 140 disposed in the inner lower portion of the first hole 147. In FIG. 1, the region containing fluorine is indicated by a hatched region, and the hatched region is formed in the shape of a planar ring formed along the inner edge of the first hole 147.

With this configuration, the width ratio (W / L) of the width of the semiconductor 154 adhered to the inside of the first hole 147 to the channel length is increased, and the patterning of the semiconductor 154 using the inkjet method is effectively performed .

A protective film 180 is formed on the bank 146 and the semiconductor 154. The protective film 180 may be patterned by a dry etching process to have a contact hole in communication with the second hole 148 of the bank 146. The protective film 180 having such a configuration prevents the semiconductor 154 from being damaged during the manufacturing process and thereafter.

The pixel electrode 191 is formed of an opaque metal material and is formed on the protective film 180. The pixel electrode 191 is in contact with a part of the drain electrode 175 through the contact hole of the protective film 180, .

The pixel electrode 191 to which the data voltage is applied generates electrophoresis particles (not shown) between the two electrodes by generating an electric field together with a common electrode (not shown) facing the pixel electrode 191 and receiving a common voltage .

The pixel electrode 191 may be made of a transparent conductive oxide such as ITO or IZO.

Hereinafter, a method of manufacturing the thin film transistor panel shown in FIGS. 1 and 2 will be described in detail with reference to FIGS. 3 to 14. FIG.

FIGS. 3, 5, 7, 9, and 11 are views showing a method of manufacturing the thin film transistor panel of FIGS. 1 and 2 according to an embodiment of the present invention.

4 is a cross-sectional view taken along line IV-IV and line IV-IV 'of FIG. 3, and FIG. 6 is a cross-sectional view taken along line VI- And FIG. 8 is a cross-sectional view cut along the line VIII-VIII and VIII'-VIII 'of the thin film transistor panel of FIG.

9 is a cross-sectional view taken along line X-X and line X'-X 'of FIG. 9, and FIG. 12 is a cross-sectional view of the thin film transistor panel shown in FIG. 11 taken along line XII-XII and XII'- 'Cut along the line.

13 is a cross-sectional view of the thin film transistor panel shown in FIG. 12 in a subsequent process, and FIG. 14 is a cross-sectional view illustrating a process for manufacturing the thin film transistor panel shown in FIGS.

Referring to FIGS. 3 and 4, a gate metal layer such as aluminum or molybdenum is deposited on the substrate 110. Then, the gate metal layer is etched using the etching solution to form the gate line 121 and the gate electrode 124. [ At this time, a wide end portion 129 of the gate line 121 is also formed.

5, 6, and 14, an organic insulating film is laminated on the gate line 121 and the gate electrode 124, and is photo-etched to form the gate insulating film 140 having the contact hole 141.

Then, an ITO layer and a molybdenum layer are laminated on the gate insulating film 140 to form a data metal layer. Here, the ITO layer is the first conductive layer 171p, 173p, and 175p, and the molybdenum layer is the second conductive layer 171q, 173q, and 175q.

Next, a photoresist layer is coated on the molybdenum layer, and the photoresist layer is exposed and developed using a halftone mask to form a primary photoresist pattern 41.

The data line 171, the source electrode 173, the drain electrode 175, the wide end portion 179 and the contact assistant member 172 are etched using the primary photosensitive film pattern 41 as a mask The remaining ITO layer and molybdenum layer are removed except for the portion to be formed.

The source electrode 173 and the drain electrode 175 are preferably formed on the upper portion of the electrode portion 124b with a smaller area than the electrode portion 124b of the gate electrode 124. [ This is because the light generated from the lower portion of the substrate 110 is blocked by the electrode portion 124b, thereby preventing occurrence of photo leakage.

Next, referring to FIGS. 7, 8 and 14, the primary photosensitive film pattern 41 is etched back to form a secondary photosensitive film pattern 42. Etching is performed using the second photoresist pattern 42 as a mask to expose portions of the molybdenum layer formed above the electrode portions 124b of the gate electrode 124 to form the source electrode 173 and the drain electrode 175 The blocking portions 170p made of the ITO layer are formed, and then the second photoresist pattern 42 is removed.

Next, referring to FIGS. 9 and 10, an organic insulating film is applied and photolithographically etched to form a bank 146 having a first hole 147 and a second hole 148.

At this time, the first hole 147 is formed in the upper portion of the electrode portion 124b with an area larger than the cut-off portion 170p, which is smaller than the electrode portion 124b of the gate electrode 124 but remains on the upper portion of the electrode portion 124b A portion of the source electrode 173 and the drain electrode 175 is exposed.

The reason why the size of the first hole 147 is larger than that of the blocking portion 170p on the upper side of the electrode portion 124b is that the source electrode 173 and the drain This is to prevent the electrode 175 from being short-circuited.

On the other hand, when the organic insulating layer is photosensitive, the banks 146 can be formed only by photolithography.

Then, the entire surface of the substrate 110 is treated with CF ₄ plasma. When the fluorine plasma treatment is performed, the bank 146 formed of the organic insulating film contains fluorine therein. At this time, the fluorine contained in the bank 146 may exhibit various types of distribution depending on the plasma processing time.

For example, the fluorine may be uniformly distributed within the entire thickness of the bank 146, and the content density may gradually decrease from the upper side to the lower side of the bank 146, and only the upper side of the bank 146 It may be distributed.

The gate insulating film 140 under the first hole 147 is protected by the blocking portion 170p remaining in the inside of the first hole 147. In this case,

Therefore, the gate insulating film 140 is provided with a planar ring-shaped region (indicated by a hatched region in FIG. 9 as an area between the blocking portion and the first hole) formed along the inner rim of the first hole 147, And the peripheral region of the wide end portion 179 contain fluorine. Therefore, even if the gate insulating film 140 is formed of an organic film, the gate insulating film 140 is damaged due to the plasma treatment, and the characteristics of the thin film transistor can be prevented from deteriorating.

11 and 12, using the molybdenum layer exposed inside the first hole 147 as a mask, the ITO layer exposed inside the first hole 147, that is, the blocking portion 170p ).

13, the molybdenum layer remaining inside the first hole 147 and the molybdenum layer of the wide end portion 179 and the molybdenum layer of the contact assistant member 172, using the bank 146 as a mask, Remove.

Then, the ink containing the semiconductor material is dropped by an inkjet method, and then dried to pattern the semiconductor 154. At this time, the bank 146 contains fluorine by the plasma treatment, and the gate insulating film 140 under the first hole 147 does not contain fluorine.

The fluorine acts to increase the contact angle of the ink. The ink dropped onto the bank 146 is introduced into the first hole 147 having a smaller contact angle than the bank 146, that is, the wettability of the ink is good, and is effectively formed in the first hole 147, And contacts a portion of the electrode 173 and the drain electrode 175 at the same time.

FIG. 15 is a table showing experimental results of the inventors of the present invention. FIG. Referring to the table, when the fluorine plasma is not treated, the contact angle of the ink is very low, so that the pattern accuracy is 0%. On the other hand, when the fluorine plasma is treated, the ink contact angle increases and the pattern accuracy is greatly improved.

On the other hand, it is preferable that the second hole 148 is formed at a position away from the first hole 147 in order to prevent the ink dropped on the bank 146 from entering the inside of the second hole 148.

Although the second hole 148 is formed in the linear end portion of the drain electrode 175 in the embodiment of the present invention, the position of the second hole 148 can be variously changed by changing the shape of the drain electrode 175 have. For example, it is possible to form the same shape as that of the extended portion on the other end of the linear portion, and to form the second hole 148 thereon.

1 and 2, a protective film 180 having contact holes aligned with the second hole 148 of the bank 146 is formed.

After the protective film 180 is formed, an opaque metal material such as chromium is deposited to form the pixel electrode 191. At this time, the pixel electrode 191 is in contact with the drain electrode 175 through the second hole 148 of the bank 146.

16 is a cross-sectional view of a flat panel display having a thin film transistor panel according to an embodiment of the present invention. FIG. 16 shows an electrophoretic display device as an example of a flat panel display device, but the thin film transistor panel of this embodiment is also applicable to other types of flat panel display devices such as a liquid crystal display device and an organic light emitting display device.

The flat panel display shown in Fig. 16 has the thin film transistor panel of the above-described embodiment. Therefore, only the reference numerals are given to the constituent elements of the thin film transistor panel, and a description thereof will be omitted.

The flat panel display of the present embodiment is formed by lamination of a sheet of E-INK Co., Ltd. to the thin film transistor panel of the above-described embodiment.

Specifically, the sheet includes an insulating substrate 210, a common electrode 270 formed on one surface of the insulating substrate 210, a black matrix (not shown) disposed on the common electrode 270, Electrophoretic particles 230 arranged in the pixel space partitioned by the black matrix and an adhesive 240 sealing the electrophoretic particles 230 in the pixel space.

At this time, the adhesive 240 also acts to bond the sheet to the thin film transistor display panel. The common electrode 270 may be made of ITO or IZO.

When a flat panel display device is manufactured by laminating a sheet having such a configuration on a thin film transistor panel, the thin film transistor panel provided in the flat panel display device of this embodiment has the pixel electrode 191 formed on the protective film 180.

Therefore, since the adhesive 240 is prevented from penetrating the semiconductor 154, deterioration of characteristics of the thin film transistor due to penetration of the adhesive is prevented.

This will be described with reference to a graph.

FIG. 17 is a graph showing the characteristics of the thin film transistor before and after the electrophoretic layer is attached to the thin film transistor panel with the structure in which the pixel electrode does not cover the thin film transistor. Lamination is performed before lamination of the electrophoretic layer (left) It can be seen that the current in the off state greatly increases after (right).

On the other hand, in the case of the thin film transistor panel according to the embodiment of the present invention, as shown in Fig. 18, there is no significant change in the characteristic curve of the thin film transistor before (left) and after (right) lamination of the electrophoretic layer .

The electrophoretic particles 230 have a positive or negative electric charge so that the pixel electrode 191 or the common electrode 270 is formed in accordance with the voltage applied to the pixel electrode 191 and the common electrode 270. [ Are moved closer to each other. Accordingly, the natural light incident on the insulating substrate 210 is reflected or absorbed by the electrophoretic particles 230 to display a desired image to the outside.

In the thin film transistor panel according to the embodiment of the present invention, the pixel electrode 191 is disposed on the uppermost layer. Therefore, it is possible to maximize the area that can contribute to display by disposing the pixel electrodes to the top of the thin film transistor and the bank. As a result, a high aperture ratio structure becomes possible, so that an electrophoretic display device that displays an image using natural light can display an image with high luminance.

And, using a color filter, it is possible to express high color and bright color.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, And falls within the scope of the invention.

1 is a layout diagram of a thin film transistor panel according to an embodiment of the present invention,

FIG. 2 is a cross-sectional view of the thin film transistor panel shown in FIG. 1 taken along lines II-II and II'-II '

FIGS. 3, 5, 7, 9, and 11 are plan views showing a method of manufacturing the thin film transistor panel of FIGS. 1 and 2 according to an embodiment of the present invention,

FIG. 4 is a cross-sectional view of the thin film transistor panel of FIG. 3 cut along lines IV-IV and IV-IV '

FIG. 6 is a cross-sectional view of the thin film transistor panel shown in FIG. 5 taken along lines VI-VI and VI'-VI '

8 is a cross-sectional view cut along the line VIII-VIII and VIII'-VIII 'of the thin film transistor panel of FIG. 7,

FIG. 10 is a cross-sectional view of the thin film transistor panel of FIG. 9 cut along the lines X-X and X'-X '

FIG. 12 is a cross-sectional view of the thin film transistor panel of FIG. 11 cut along the lines XII-XII and XII'-XII '

FIG. 13 is a cross-sectional view of the thin film transistor panel shown in FIG. 12,

FIG. 14 is a cross-sectional view of the manufacturing process of the thin film transistor panel shown in FIGS. 5 to 8,

Fig. 15 is a table in which the ink contact angle and the pattern accuracy in the case where the fluorine plasma treatment was not carried out and the case in which the fluorine plasma treatment was carried out were measured.

16 is a cross-sectional view showing an example of a flat panel display device having a thin film transistor panel according to an embodiment of the present invention,

17 is a graph showing the characteristics of the thin film transistor before and after the electrophoretic layer is attached to the thin film transistor panel with the structure in which the pixel electrode does not cover the thin film transistor,

18 is a graph showing the characteristics of the thin film transistor before and after the electrophoretic layer is attached to the thin film transistor panel according to the embodiment of the present invention.

Description of the Related Art

110: Insulation substrate 121: Gate line

124: gate electrode 124a:

124b: electrode part 140: gate insulating film

146: bank 147: first hole

148: second hole 154: semiconductor

171: Data line 173: Source electrode

175: drain electrode 180: protective film

191: pixel electrode 230: electrophoretic particle

240: Adhesive 270: Common electrode

Claims (35)

Board, A gate line formed on the substrate and extending in a first direction, the gate line having a gate electrode, A gate insulating film formed on the gate line and locally containing fluorine in a partial region, A data line formed on the gate insulating film and extending in a second direction intersecting the gate line, A source electrode connected to the data line and a drain electrode separated from the source electrode, A bank formed on the source electrode and the drain electrode and having a first hole exposing the source electrode and the drain electrode, A semiconductor layer formed in the first hole and connected to the source electrode and the drain electrode to form a channel, A protective film covering the bank and the semiconductor, and A pixel electrode formed on the protective film and connected to the drain electrode, And a thin film transistor. The method of claim 1, Wherein a part of the region of the gate insulating film containing fluorine includes a region of a planar ring shape formed along an inner edge of the first hole. The method of claim 1, Wherein said banks are subjected to plasma treatment to contain fluorine. The method of claim 1, Wherein the gate insulating film is formed of an organic film. 5. The method according to any one of claims 1 to 4, Wherein the data line includes a first conductive layer including a transparent conductive oxide and a second conductive layer including a metal, Wherein the portion of the source electrode and the drain electrode located within the first hole comprises the first conductive layer and the portion covered by the bank includes a first conductive layer and a second conductive layer. The method of claim 5, Further comprising a contact assistant member formed on the gate insulating film, the contact assistant member being in contact with an end portion of the gate line through a contact hole and comprising the first conductive layer, Wherein the data line has a wide end portion composed of the first conductive layer, Wherein a part of the region of the gate insulating film containing fluorine further includes a peripheral region of a wide end portion of the contact assistant member and the data line. The method of claim 6, Wherein the first hole is formed on the gate electrode in a smaller area than the gate electrode. 8. The method of claim 7, Wherein the pixel electrode covers the semiconductor. 9. The method of claim 8, Wherein the pixel electrode is made of an opaque metal material. 9. The method of claim 8, A second hole is formed in the bank to expose a part of the drain electrode, and the pixel electrode is connected to the drain electrode through the second hole. The method of claim 1, Further comprising a contact assistant member formed on the gate insulating film, the contact assistant member being in contact with an end portion of the gate line through a contact hole and comprising the first conductive layer, Wherein the data line has a wide end portion composed of the first conductive layer, Wherein a part of the region of the gate insulating film containing fluorine includes the peripheral region of the wide end portion of the contact assistant member and the data line. The method of claim 1, Wherein the first hole is formed on the gate electrode in a smaller area than the gate electrode. The method of claim 1, Wherein the pixel electrode covers the semiconductor. A) forming a gate line including a gate electrode on a substrate, B) forming a gate insulating film covering the gate line, C) continuously depositing a first conductive layer and a second conductive layer on the gate insulating layer, D) patterning the first conductive layer and the second conductive layer to form a data line, a source electrode and a drain electrode including the first conductive layer and the second conductive layer, and a source electrode and a drain electrode, Forming a blocking portion connected to the drain electrode and made of the first conductive layer, E) forming a bank having a source electrode and a drain electrode and a first hole exposing the blocking portion, F) performing a fluorine plasma treatment, G) removing the blocking portion by etching the first conductive layer using the second conductive layer exposed through the first hole as a mask, H) forming a semiconductor inside the first hole, I) forming a protective film covering the bank and the semiconductor, and J) forming a pixel electrode on the protective film And forming a thin film transistor on the substrate. The method of claim 14, Wherein the semiconductor is formed by dropping a semiconductor material by an inkjet method. 15. The method according to claim 14 or 15, The step D) D-1) applying a photoresist over the second conductive layer, exposing and developing the photoresist using a halftone mask to form a primary photoresist pattern, D-2) By performing etching using the primary photoresist pattern as a mask, a pattern including a first conductive layer and a second conductive layer around the data line, a portion where the source electrode and the drain electrode are to be formed, , &Lt; / RTI &gt; D-3) forming a second photoresist pattern by etching back the first photoresist pattern, D-4) removing remaining portions of the second conductive layer formed on the gate electrode except the portion where the source electrode and the drain electrode are to be formed by performing etching using the second photoresist pattern as a mask, And D-5) removing the second photoresist pattern And forming a thin film transistor on the substrate. 17. The method of claim 16, Wherein the first conductive layer and the second conductive layer are left on the gate electrode in a smaller area than the gate electrode in the step (D-2). The method of claim 17, In the step E), the first hole is formed on the gate electrode at a size larger than the first and second conductive layers remaining on the gate electrode and smaller than the gate electrode. Way. The method of claim 18, Wherein in step E) a second hole is formed to expose a part of the drain electrode, and in step I), holes aligned with the second hole are formed, and in step J) And the pixel electrode is connected to the drain electrode. The method of claim 18, And removing the second conductive layer exposed inside the first hole using the bank as a mask, the method further comprising, between step G) and step H) . 20. The method of claim 20, Wherein the contact assistant member includes the first conductive layer and the second conductive layer and is connected to a wide end portion of the gate line in the step (D), and in the (G-1) And removing the second conductive layer. The method of claim 14, In the step E), the first hole is formed on the gate electrode at a size larger than the first and second conductive layers remaining on the gate electrode and smaller than the gate electrode. Way. The method of claim 14, And removing the second conductive layer exposed inside the first hole using the bank as a mask, the method further comprising, between step G) and step H) . The method of claim 14, Further comprising a contact assistant member including the first conductive layer and the second conductive layer and connected to a wide end portion of the gate line in the step (D), and in the step (G-1) 2 conductive layer is removed. Thin film transistor display panel, A common electrode panel facing the thin film transistor panel, and Electrophoretic particles disposed between the thin film transistor display panel and the common electrode display panel / RTI &gt; In the thin film transistor display panel, Board, A gate line formed on the substrate and extending in a first direction, the gate line having a gate electrode, A gate insulating film formed on the gate line and locally containing fluorine in a partial region, A data line formed on the gate insulating film and extending in a second direction intersecting the gate line, A source electrode connected to the data line and a drain electrode separated from the source electrode, A bank formed on the source electrode and the drain electrode and having a first hole exposing the source electrode and the drain electrode, A semiconductor layer formed in the first hole and connected to the source electrode and the drain electrode to form a channel, A protective film covering the bank and the semiconductor, and A pixel electrode formed on the protective film and connected to the drain electrode, And the flat panel display device. 26. The method of claim 25, Wherein a part of the region of the gate insulating film containing fluorine includes a region of a planar ring shape formed along an inner edge of the first hole. 26. The method of claim 25, Wherein the banks are subjected to a plasma treatment to contain fluorine. 26. The method of claim 25, Wherein the gate insulating film is formed of an organic film. 29. The method according to any one of claims 25-28, Wherein the data line includes a first conductive layer including a transparent conductive oxide and a second conductive layer including a metal, Wherein the portion of the source electrode and the drain electrode located within the first hole comprises the first conductive layer and the portion covered by the bank includes a first conductive layer and a second conductive layer. 30. The method of claim 29, Wherein the first hole is formed on the gate electrode in a smaller area than the gate electrode. 32. The method of claim 30, Wherein the pixel electrode covers the semiconductor. 32. The method of claim 31, Wherein the pixel electrode is made of an opaque metal material. 32. The method of claim 31, A second hole is formed in the bank to expose a part of the drain electrode, and the pixel electrode is connected to the drain electrode through the second hole. 26. The method of claim 25, Wherein the first hole is formed on the gate electrode in a smaller area than the gate electrode. 26. The method of claim 25, Wherein the pixel electrode covers the semiconductor.

Images