KR101396088B1 - 3-dimensional cmos field effect transistor and method for manufacturing the same - Google Patents

3-dimensional cmos field effect transistor and method for manufacturing the same Download PDF

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Publication number
KR101396088B1
KR101396088B1 KR1020120142723A KR20120142723A KR101396088B1 KR 101396088 B1 KR101396088 B1 KR 101396088B1 KR 1020120142723 A KR1020120142723 A KR 1020120142723A KR 20120142723 A KR20120142723 A KR 20120142723A KR 101396088 B1 KR101396088 B1 KR 101396088B1
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South Korea
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fin
effect transistor
field effect
channel region
region
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KR1020120142723A
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Korean (ko)
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송윤흡
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한양대학교 산학협력단
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A 3-dimensional CMOS field effect transistor and a method for manufacturing same are provided. The field effect transistor includes an NMOS active region having a first fin and a PMOS active region having a second fin. The first fin includes an n channel region and a source/drain region which is extended from the n channel region. The second fin includes a semiconductor substrate which includes a p channel region and a source/drain region which is extended from the p channel region, an NMOS gate electrode which covers the upper part and both sidewalls of the n channel region, a PMOS gate electrode which covers the upper part and both sidewalls of the p channel region, and gate insulating layers which are interposed between the gate electrodes and the channel regions. Because the height of the second fin is 1.5-3 times greater than that of the first fin, the difference of the electrical property between the NMOS field effect transistor and the PMOS field effect transistor can be remarkably improved. A balance CMOS field effect transistor which can be used as an inverter is provided.

Description

[0001] The present invention relates to a three-dimensional CMOS field effect transistor and a method of manufacturing the same,

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a three-dimensional CMOS field-effect transistor having a Fin structure and a method of manufacturing the same.

In general, discrete components such as metal oxide semiconductor (MOS) field effect transistors are mainly used for switching semiconductor devices. Recently, as the degree of integration of semiconductor devices increases due to the rapid development of the semiconductor industry, MOS field effect transistors are gradually scaled down. However, the scaling down of the MOS field effect transistor leads to a decrease in the channel area and the channel length, which causes problems such as a short channel effect and a deterioration in the gate control force, which makes it difficult to highly integrate the semiconductor devices.

In order to solve the above problem, generally, a method of highly doping channel ions in a channel region is used. However, in this case, the channel resistance increases and the current driving capability is reduced.

Therefore, as another solution for the high integration of semiconductor devices, researches on field effect transistors whose structures are extended in three dimensions have been widely carried out. In this case, research has been actively conducted on a pin field effect transistor which increases a channel area by protruding a channel region in the form of a fin and forming a gate electrode on the semiconductor substrate including the channel region.

In general, a semiconductor device employs a CMOS field effect transistor including an NMOS field effect transistor and a PMOS field effect transistor. At this time, electrical characteristics such as current driving capability required for each of the NMOS field effect transistor and the PMOS field effect transistor may be different depending on the type of the semiconductor device employing the CMOS field effect transistor.

When the semiconductor device is an inverter, the electrical characteristics of the NMOS field effect transistor and the PMOS field effect transistor must be balanced. However, generally, in the same structure, the current drive capability of the PMOS field effect transistor is about 1/2 to 1/3 the current drive capability of the NMOS field effect transistor. Therefore, in order to implement the inverter, it is necessary to improve the current driving capability of the PMOS field effect transistor to the same or similar level as the current driving ability of the NMOS field effect transistor.

Conventionally, a technique of increasing the gate width of the PMOS field-effect transistor by about 2 to 3 times as much as the NMOS field-effect transistor has been used to improve the current driving capability of the PMOS field-effect transistor. However, when the above-described technique is applied, there is a problem that the operation speed of the inverter is delayed and a large offset noise is caused in switching. This is because the charge transfer characteristics between the NMOS field-effect transistor and the PMOS field-effect transistor are basically different from each other, and only the control of the current by the increase of the gate width limits the balance in the switching.

To improve this, Professor T. Ohmi of Tohoku University in Japan proposed a CMOS field effect transistor by controlling the orientation of the substrate. The CMOS field effect transistor is used as a substrate of a PMOS field effect transistor as a (551) oriented silicon substrate, which greatly improves the mobility of charge. However, since the above-described technique uses the orientation control of the substrate, it is difficult to implement the NMOS field effect transistor and the PMOS field effect transistor simultaneously in one substrate orientation.

As described above, there has been a limit in improving the electrical characteristic difference between the NMOS field effect transistor and the PMOS field effect transistor for the implementation of the inverter in the prior art.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a three-dimensional balanced CMOS field effect transistor with improved electrical characteristics between an NMOS field effect transistor and a PMOS field effect transistor, and a method of manufacturing the same.

According to an aspect of the present invention, there is provided a three-dimensional CMOS field-effect transistor. The CMOS field effect transistor includes an NMOS active region having a first fin and a PMOS active region having a second fin, the first fin having an n-channel region and a source / drain region extending from the n- Wherein the second fin comprises a semiconductor substrate comprising a p-channel region and source / drain regions extending from the p-channel region, an NMOS gate electrode covering the top and both sidewalls of the n-channel region, And PMOS gate electrodes covering both sidewalls, and gate insulating films interposed between the gate electrodes and the channel regions, wherein the height of the second fin is 1.5 to 3 times the height of the first fin.

A plurality of the first pins and the second pins may be provided. The first fin and the second fin may be formed by etching the semiconductor substrate.

The semiconductor substrate may be a silicon substrate.

The height of both sidewalls of the second fin covered by the PMOS gate electrode may be greater than the height of both sidewalls of the first fin covered by the NMOS gate electrode.

According to an aspect of the present invention, there is provided a method of manufacturing a three-dimensional CMOS field-effect transistor. The method includes forming a separation layer for separating an NMOS active region and a PMOS active region in a semiconductor substrate, etching the semiconductor substrate in one region with the separation layer therebetween to form a first fin, Forming a second fin by etching the semiconductor substrate in another region with the isolation film interposed therebetween; defining a p-channel region in the second fin to define a PMOS active Forming a gate insulating film on the semiconductor substrate defining the n-channel region and the p-channel region, and forming a gate electrode to cover the sidewalls and upper surfaces of the n-channel region and the p-channel region, .

A plurality of the first pins and the second pins may be formed. The height of the second fin may be 1.5 to 3 times higher than the height of the first fin.

The etching depth of the semiconductor substrate of the PMOS active region may be deeper than the etching depth of the semiconductor substrate of the NMOS active region.

P-channel ions may be implanted to define the p-channel region, and n-channel ions may be implanted to define the n-channel region.

After forming the gate electrode, forming the source / drain regions in the NMOS active region and the PMOS active region may further include forming the source / drain regions.

The semiconductor substrate may be a silicon substrate.

According to the present invention, a difference in electrical characteristics between the NMOS field effect transistor and the PMOS field effect transistor can be remarkably improved, thereby providing a balanced CMOS field effect transistor that can be implemented as an inverter. Moreover, the height of the fins can be made different from each other by a simple and easy method, so that the electrical characteristics of the NMOS field effect transistor and the PMOS field effect transistor can be balanced. In addition, a three-dimensional fin structure is employed, which is advantageous in high integration.

The technical effects of the present invention are not limited to those mentioned above, and other technical effects not mentioned can be clearly understood by those skilled in the art from the following description.

1 is a plan view of a three-dimensional CMOS field effect transistor according to an embodiment of the present invention.
2 is a cross-sectional view taken along the line I-I 'of FIG.
3A to 3J are cross-sectional views illustrating a method of manufacturing a three-dimensional CMOS field-effect transistor according to an embodiment of the present invention.
4 is a graph illustrating a result of a computer simulation of a current-voltage of a three-dimensional CMOS field-effect transistor according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. It is to be understood, however, that the present invention is not limited to the embodiments described herein but may be embodied in other forms and includes all equivalents and alternatives falling within the spirit and scope of the present invention.

When a layer is referred to herein as being "on" another layer or substrate, it may be formed directly on another layer or substrate, or a third layer may be interposed therebetween. In the present specification, directional expressions of the upper side, upper side, upper side, and the like can be understood as meaning lower, lower, lower, and the like according to the standard. That is, the expression of the spatial direction should be understood in the relative direction and should not be construed as limiting in the absolute direction.

In the drawings, the thicknesses of the layers and regions may be exaggerated or omitted for the sake of clarity. Like reference numerals designate like elements throughout the specification.

1 is a plan view of a three-dimensional CMOS field effect transistor according to an embodiment of the present invention.

2 is a cross-sectional view taken along the line I-I 'of FIG.

Referring to FIGS. 1 and 2A and 2B, an NMOS active region A and a PMOS active region B may be positioned around a reference plane of the semiconductor substrate 10. For example, the NMOS active region A and the PMOS active region B may be positioned based on the separator 20. The NMOS active region (A) may be an n-type MOSFET device and the PMOS active region (B) may be a p-type MOSFET device.

The NMOS active region (A) may include a first fin (12). The first fin 12 may include an n-channel region 12a and source / drain regions 12b and 12c extending from the n-channel region 12a. That is, the source / drain regions 12b and 12c may be separated by the n-channel region 12a. The source / drain regions 12b and 12c may be electrically connected to the source / drain electrodes 50a and 50b, respectively.

Meanwhile, the PMOS active region (B) may include a second fin (14). The second fin 14 may include a p-channel region 14a and source / drain regions 14b and 14c extending from the p-channel region 14a. That is, the source / drain regions 14b and 14c may be separated by the p-channel region 14a. The source / drain regions 14b and 14c may be electrically connected to the source / drain electrodes 60a and 60b, respectively.

Thus, since the n-channel region 12a is formed in the first fin 12 and the p-channel region 14a is formed in the second fin 14, a three-dimensional channel region can be defined.

The semiconductor substrate 10 may be a silicon substrate. In this case, the first fin 12 and the second fin 14 may be formed by etching the semiconductor substrate 10. That is, the NMOS active region A and the PMOS active region B may be formed in the semiconductor substrate 10 and may be integrally connected to the semiconductor substrate 10.

In this case, the height of the second pin 14 may be higher than the height of the first pin 12. More specifically, the height of the second fin 14 may be 1.5 to 3 times the height of the first fin 12.

An NMOS gate electrode 40a is disposed to cover upper and side walls of the n-channel region 12a and a PMOS gate electrode 40b is disposed to cover upper and side walls of the p-channel region 14a. The NMOS gate electrode 40a and the PMOS gate electrode 40b may be formed of a conductive material. For example, the NMOS gate electrode 40a may be an n-type doped polysilicon material, and the PMOS gate electrode 40b may be a p-type doped polysilicon material.

Since the height of the second fin 14 is higher than that of the first fin 12 at this time, the height of both side walls of the second fin 14 covered by the PMOS gate electrode 40b is greater than the height of the NMOS May be higher than the height of both side walls of the first fin (12) covered by the gate electrode (40a).

Thereby, the current driving capability of the p-type MOSFET device can be adjusted to the current driving capability level of the n-type MOSFET device. That is, the difference in electric characteristics of both MOSFET devices can be improved.

A gate insulating film 30 is interposed between the n-channel region 12a and the NMOS gate electrode 40a and between the p-channel region 14a and the PMOS gate electrode 40b. The gate insulating film 30 may be a SiO 2 film. The gate insulating film 30 may be formed of a material such as Si 3 N 4 , Al 2 O 3 , CeO 2 , HfO 2 , La 2 O 3 , Ta 2 O 5 , Y 2 O 3 , ZrO 2 , ZrAlO, HfAlO, ZrTiO 4 , SnTiO 4, and SrTiO 3 .

Although the first pin 12 and the second pin 14 are shown in FIGS. 1 and 2A and 2B, the first pin 12 and the second pin 14 are formed on the semiconductor substrate 10).

3A to 3E are cross-sectional views illustrating a method of fabricating a three-dimensional CMOS field-effect transistor according to an embodiment of the present invention.

Referring to FIG. 3A, a separation layer 20 is formed in a semiconductor substrate 10. The semiconductor substrate 10 may be a silicon substrate. The isolation layer 20 may serve to separate the NMOS active region and the PMOS active region. That is, the NMOS active region and the PMOS active region may be isolated by the isolation layer 20.

The isolation layer 20 may be formed through a shallow trench isolation (STI) process. More specifically, the semiconductor substrate 10 may be patterned to form a trench for defining predetermined regions of the semiconductor substrate 10. Thereafter, a separation film 20 for burying the trench can be formed. Through this, the space to be used as the NMOS active region and the PMOS active region can be defined.

3B to 3D, the first fin 12 is formed by etching the semiconductor substrate 10 in one region with the separator 20 interposed therebetween. More specifically, first hard mask patterns 70a may be formed on one region A of the semiconductor substrate 10. [ At this time, the first hard mask pattern 70a may be a film made of a material having an etch selectivity with respect to the separation film 20. [ Thereafter, the semiconductor substrate 10 may be etched using the first hard mask pattern 70a as an etch mask. The etching may be performed in a direction perpendicular to the semiconductor substrate 10. Thus, the first fin 12 can be formed. At this time, a plurality of the first pins 12 may be formed. Thereafter, the n-channel region 12a may be defined in the first fin 12, and the first hard mask pattern 70a may be removed. At this time, the n-channel region 12a can be defined by ion implantation. For example, the n-channel region 12a may be formed by implanting n-channel ions into the first fin 12 using the first hard mask pattern 70a as an ion implantation mask. Thereby, the NMOS active region (A) can be formed.

3E to 3G, the second fin 14 is formed by etching the semiconductor substrate 10 in another region with the separator 20 interposed therebetween. The other region may be a region opposed to one region with the separator 20 interposed therebetween. The second hard mask pattern 70b may be formed on the other region B of the semiconductor substrate 10. [ In this case, the second hard mask pattern 70b may be a film made of a material having an etch selectivity with respect to the separation film 20. The second hard mask pattern 70b may be the same as or different from the first hard mask pattern 70a. The second hard mask pattern 70b may have the same pattern as the first hard mask pattern 70a. Thereafter, the semiconductor substrate 10 may be etched using the second hard mask pattern 70b as an etch mask. The etching may be performed in a direction perpendicular to the semiconductor substrate 10.

The etch depth of the semiconductor substrate 10 may be deeper than the etch depth of the NMOS active region (A). For example, if the second hard mask pattern 70b is made of the same material as the first hard mask pattern 70a, the etch depth may be changed by controlling the etch time. Thereby, the second pin 14 higher than the height of the first fin 12 can be formed. At this time, the process conditions such as the etching time can be adjusted so that the height of the second fin 14 is 1.5 to 3 times higher than the height of the first fin 12.

A plurality of the second pins 14 may be formed. Thereafter, the p-channel region 14a may be defined in the second fin 14, and the second hard mask pattern 70b may be removed. At this time, the p-channel region 14a can be defined using ion implantation. For example, the p-channel region 14a may be formed by implanting p-channel ions into the second fin 14 using the second hard mask pattern 70b as an ion implantation mask. Thereby, the PMOS active region B can be formed.

3B to 3G illustrate a method of forming the second fin 14 after forming the first fin 12 for convenience, but the present invention is not limited thereto. That is, after forming the second fin 14 first, the first fin 12 may be formed. After the hard mask pattern is formed on the entire surface of the semiconductor substrate 10, the etching is performed and the etch is further performed on the PMOS active region B to increase the height of the second fin 14 to the first fin 12). ≪ / RTI >

Referring to FIG. 3H, a gate insulating film 30 is formed on a semiconductor substrate 10 on which a first fin 12 and a second fin 14 are formed. The gate insulating film 30 covers sidewalls and upper surface of the n-channel region 12a of the first fin 12, sidewalls and upper surface of the p-channel region 14a of the second fin 14, . The gate insulating film 30 may be a SiO 2 film. The gate insulating film 30 may be formed of a material such as Si 3 N 4 , Al 2 O 3 , CeO 2 , HfO 2 , La 2 O 3 , Ta 2 O 5 , Y 2 O 3 , ZrO 2 , ZrAlO, HfAlO, ZrTiO 4 , SnTiO 4 And SrTiO 3 . The gate insulating layer 30 may be formed using a conventional deposition method such as atomic layer deposition, sputtering, or chemical vapor deposition.

Referring to FIGS. 3I and 3J, a gate electrode 40 is formed to cover sidewalls and upper surfaces of the n-channel region 12a and the p-channel region 14a. The gate electrode 40 may include an NMOS gate electrode 40a and a PMOS gate electrode 40b. First, the gate conductive film 41 may be formed on the semiconductor substrate 10 on which the gate insulating film 30 is formed. In one example, the gate conductive film 41 may be a polysilicon film. The gate conductive layer 41 may be patterned to form a gate electrode 40 covering the sidewalls and upper surfaces of the n-channel region 12a and the p-channel region 14a. The gate electrode 40 may form the NMOS gate electrode 40a and the PMOS gate electrode 40b at the same time or may be formed separately.

Thereafter, a source / drain region is formed in the first fin 12 extending from the n-channel region 12a using the gate electrode 40 as an ion implantation mask, and a source / drain region extending from the p- Source / drain regions can be formed in the two-pin 14, respectively.

4 is a graph illustrating a result of a computer simulation of a current-voltage of a three-dimensional CMOS field-effect transistor according to an embodiment of the present invention. A SiO 2 film having a thickness of 20 nm was used as a gate insulating film, the height of the first fin of the NMOS active region was set to 48 nm, and the height of the second fin of the PMOS active region was set to 80 nm.

Referring to FIG. 4, it can be seen that the threshold voltage of the p-type MOSFET device in the PMOS active region is -0.409 V and the threshold voltage (V th ) of the n-type MOSFET device in the NMOS active region is approximately 0.471 V. The subthreshold slope (SS) of the p-type MOSFET device in the PMOS active region is -82.3 mV / decade, and the subthreshold slope (SS) of the n-type MOSFET device in the NMOS active region is approximately equal to + 79.8 mV / decade Can be confirmed. Therefore, when the height (80 nm) of the second fin of the PMOS active region is about 1.7 times higher than that of the first fin (48m) of the NMOS active region, it can be seen that the electric characteristics of both MOSFET devices exhibit substantially similar values.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, This is possible.

10: semiconductor substrate 12: first pin
12a: n-channel regions 12b, 12c, 14b, 14c: source / drain regions
14: second pin 20: separator
30: gate insulating film 40: gate electrode
50a, 50b, 60a, 60b: source / drain electrodes
70a, 70b: first and second hard mask patterns

Claims (12)

delete delete delete delete delete Forming a separator for separating the NMOS active region and the PMOS active region in the semiconductor substrate;
Etching the semiconductor substrate to form a first fin in the NMOS active region, forming a portion of the second fin height in the PMOS active region, which is another region, and further etching the PMOS active region, Forming all of the height;
Forming a gate insulating film on the semiconductor substrate having the n-channel region and the p-channel region defined therein; And
Forming a gate electrode to cover sidewalls and top surfaces of the n-channel region and the p-channel region,
Wherein the second pin is higher in height than the first pin.
Method for fabricating a three - dimensional CMOS field effect transistor. The method according to claim 6,
Wherein a plurality of the first fin and the second fin are formed. The method according to claim 6,
Wherein the height of the second fin is 1.5 to 3 times higher than the height of the first fin. delete The method according to claim 6,
Implanting p-channel ions to define the p-channel region, and implanting n-channel ions to define the n-channel region. The method according to claim 6,
After forming the gate electrode,
And forming source / drain regions in the NMOS active region and the PMOS active region. The method according to claim 6,
Wherein the semiconductor substrate is a silicon substrate.
KR1020120142723A 2012-12-10 2012-12-10 3-dimensional cmos field effect transistor and method for manufacturing the same KR101396088B1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050094576A (en) * 2004-03-23 2005-09-28 삼성전자주식회사 Three dimensional cmos field effect transistor and method of fabricating the same
KR100642632B1 (en) 2004-04-27 2006-11-10 삼성전자주식회사 Methods of fabricating a semiconductor device and semiconductor devices fabricated thereby
JP2010114443A (en) 2008-11-10 2010-05-20 Brion Technologies Inc Method and system for general matching and tuning of model base
KR20110056225A (en) * 2009-11-20 2011-05-26 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Finfets with different fin heights

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050094576A (en) * 2004-03-23 2005-09-28 삼성전자주식회사 Three dimensional cmos field effect transistor and method of fabricating the same
KR100642632B1 (en) 2004-04-27 2006-11-10 삼성전자주식회사 Methods of fabricating a semiconductor device and semiconductor devices fabricated thereby
JP2010114443A (en) 2008-11-10 2010-05-20 Brion Technologies Inc Method and system for general matching and tuning of model base
KR20110056225A (en) * 2009-11-20 2011-05-26 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Finfets with different fin heights

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