KR101382943B1 - Solar cell apparatus and method of fabricating the same - Google Patents

Solar cell apparatus and method of fabricating the same Download PDF

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KR101382943B1
KR101382943B1 KR1020120040264A KR20120040264A KR101382943B1 KR 101382943 B1 KR101382943 B1 KR 101382943B1 KR 1020120040264 A KR1020120040264 A KR 1020120040264A KR 20120040264 A KR20120040264 A KR 20120040264A KR 101382943 B1 KR101382943 B1 KR 101382943B1
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layer
window
solar cell
back electrode
light absorbing
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KR20130117258A (en
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성명석
장대진
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엘지이노텍 주식회사
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    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
    • H01L31/0392—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate
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    • H01L31/0322—Inorganic materials including, apart from doping materials or other impurities, only compounds not provided for in groups H01L31/0272 - H01L31/0312 comprising only AIBIIICVI chalcopyrite compounds, e.g. Cu In Se2, Cu Ga Se2, Cu In Ga Se2
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    • H01L31/0749—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type including a AIBIIICVI compound, e.g. CdS/CulnSe2 [CIS] heterojunction solar cells
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    • H01L31/022466—Electrodes made of transparent conductive layers, e.g. TCO, ITO layers
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    • Y02E10/541—CuInSe2 material PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract

발명의 실시예에 따른 태양전지는 지지기판; 상기 지지기판 상에 형성된 이면전극층; 상기 이면전극층 상에 형성된 광 흡수층; 상기 광 흡수층 상에 복수개로 형성되는 버퍼층; 상기 버퍼층 상에 형성된 윈도우층; 및, 상기 윈도우층 상에 형성된 불순물 도핑층;을 포함한다.Solar cell according to an embodiment of the present invention; A back electrode layer formed on the support substrate; A light absorbing layer formed on the back electrode layer; A plurality of buffer layers formed on the light absorbing layer; A window layer formed on the buffer layer; And an impurity doping layer formed on the window layer.

Description

태양전지 및 이의 제조방법{SOLAR CELL APPARATUS AND METHOD OF FABRICATING THE SAME}BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a solar cell,

실시예는 태양전지 및 이의 제조방법에 관한 것이다.An embodiment relates to a solar cell and a manufacturing method thereof.

최근 에너지의 수요가 증가함에 따라서, 태양광 에너지를 전기에너지로 변환시키는 태양전지에 대한 개발이 진행되고 있다.Recently, as the demand for energy increases, development of solar cells for converting solar energy into electrical energy is in progress.

태양전지(Solar Cell 또는 Photovoltaic Cell)는 태양광을 직접 전기로 변환시키는 태양광발전의 핵심소자이다.Solar cells (Solar Cells or Photovoltaic Cells) are the key elements of photovoltaic power generation that convert sunlight directly into electricity.

예로서 반도체의 pn접합으로 만든 태양전지에 반도체의 금지대폭(Eg : Band-gap Energy)보다 큰 에너지를 가진 태양광이 입사되면 전자-정공 쌍이 생성되는데, 이들 전자-정공이 pn 접합부에 형성된 전기장에 의해 전자는 n층으로, 정공은 p층으로 모이게 됨에 따라 pn간에 기전력(광기전력:Photovoltage)이 발생하게 된다. 이때 양단의 전극에 부하를 연결하면 전류가 흐르게 되는 것이 동작원리이다.For example, when solar light having energy greater than the band-gap energy (Eg) is incident on a solar cell made of a pn junction of a semiconductor, electron-hole pairs are generated, and these electron-holes form an electric field formed at a pn junction. As a result, electrons are gathered into the n-layer and holes are gathered into the p-layer, whereby electromotive force (photovoltage) is generated between pn. At this time, when the load is connected to the electrodes at both ends, current flows.

특히, 유리기판, 금속 후면 전극층, p형 CIGS계 광 흡수층, 고 저항 버퍼층, n형 윈도우층 등을 포함하는 기판 구조의 pn 헤테로 접합 장치인 CIGS계 태양전지가 널리 사용되고 있다.Particularly, a CIGS-based solar cell which is a pn heterojunction device of a substrate structure including a glass substrate, a metal back electrode layer, a p-type CIGS light absorbing layer, a high resistance buffer layer, an n-type window layer and the like is widely used.

종래기술에서 전기전도성을 위해 윈도우층을 두껍게 형성하나 상기 윈도우층이 두꺼워지는 경우, 광 투과성이 감소하여 광-전 변환 효율이 감소하게 된다. In the prior art, when the window layer is formed thick for the electrical conductivity, but the window layer is thickened, the light transmittance is reduced, thereby reducing the photoelectric conversion efficiency.

이에 따라 광 투과성과 전기전도성을 동시에 만족시키는 기술에 관한 연구가 계속되고 있다.As a result, research on a technology that satisfies the light transmittance and the electrical conductivity at the same time continues.

발명의 실시예에 따른 태양전지는 광-전 변환 효율을 개선한 태양전지 및 그 제조방법을 제공하는 것을 목적으로 한다.A solar cell according to an embodiment of the present invention is to provide a solar cell and a method of manufacturing the same that improves the photoelectric conversion efficiency.

발명의 실시예에 따른 태양전지는 지지기판; 상기 지지기판 상에 형성된 이면전극층; 상기 이면전극층 상에 형성된 광 흡수층; 상기 광 흡수층 상에 복수개로 형성되는 버퍼층; 상기 버퍼층 상에 형성된 윈도우층; 및, 상기 윈도우층 상에 형성된 불순물 도핑층;을 포함한다.Solar cell according to an embodiment of the present invention; A back electrode layer formed on the support substrate; A light absorbing layer formed on the back electrode layer; A plurality of buffer layers formed on the light absorbing layer; A window layer formed on the buffer layer; And an impurity doping layer formed on the window layer.

발명의 실시예에 따른 태양전지는 윈도우층을 얇게 형성하여 높은 투과율과 전기전도성을 갖는 윈도우층을 제공할 수 있다.The solar cell according to the embodiment of the present invention may provide a window layer having a high transmittance and electrical conductivity by forming a thin window layer.

또한 버퍼층과 윈도우층의 밴드갭 격차를 감소시켜 광-전 변환 효율이 향상될 수 있다.In addition, the photoelectric conversion efficiency may be improved by reducing the band gap gap between the buffer layer and the window layer.

도 1은 실시예에 따른 태양전지를 도시한 단면도이다.
도 2 내지 도 5는 실시예에 따른 태양전지 패널을 제조하는 과정을 도시한 도면들이다.1 is a cross-sectional view showing a solar cell according to an embodiment.
2 to 5 are views illustrating a process of manufacturing the solar cell panel according to the embodiment.

실시예의 설명에 있어서, 각 기판, 층, 막 또는 전극 등이 각 기판, 층, 막, 또는 전극 등의 "상(on)"에 또는 "아래(under)"에 형성되는 것으로 기재되는 경우에 있어, "상(on)"과 "아래(under)"는 "직접(directly)" 또는 "다른 구성요소를 개재하여(indirectly)" 형성되는 것을 모두 포함한다. 또한 각 구성요소의 상 또는 아래에 대한 기준은 도면을 기준으로 설명한다. 도면에서의 각 구성요소들의 크기는 설명을 위하여 과장될 수 있으며, 실제로 적용되는 크기를 의미하는 것은 아니다.
In the description of the embodiments, in the case where each substrate, layer, film or electrode is described as being formed "on" or "under" of each substrate, layer, film, , "On" and "under" all include being formed "directly" or "indirectly" through "another element". In addition, the upper or lower reference of each component is described with reference to the drawings. The size of each component in the drawings may be exaggerated for the sake of explanation and does not mean the size actually applied.

도 1은 실시예에 따른 태양전지를 도시한 단면도이다. 도 1을 참조하면, 태양전지 패널은 지지기판(100), 이면전극층(200), 광 흡수층(300), 버퍼층(400), 고저항 버퍼층(500), 윈도우층(600) 및 불순물 도핑층(700)을 포함한다.1 is a cross-sectional view showing a solar cell according to an embodiment. Referring to FIG. 1, a solar cell panel includes a support substrate 100, a back electrode layer 200, a light absorbing layer 300, a buffer layer 400, a high resistance buffer layer 500, a window layer 600, and an impurity doping layer ( 700).

상기 지지기판(100)은 플레이트 형상을 가지며, 상기 이면전극층(200), 광 흡수층(300), 버퍼층(400), 고저항 버퍼층(500), 윈도우층(600) 및 불순물 도핑층(700)을 지지한다.The support substrate 100 has a plate shape, and includes the back electrode layer 200, the light absorbing layer 300, the buffer layer 400, the high resistance buffer layer 500, the window layer 600, and the impurity doping layer 700. I support it.

상기 지지기판(100)은 절연체일 수 있다. 상기 지지기판(100)은 금속기판일 수 있다. 이외에, 지지기판(100)의 재질로 스테인레스 스틸(SUS, STS) 등이 사용될 수 있다. 상기 지지기판(100)은 포함되는 물질의 성분 비율에 따라 여러 기호로 구분될 수 있으며, C, Si, Mn, P, S, Ni, Cr, Mo 또는 Fe 중의 적어도 하나를 포함할 수 있다. 상기 지지기판(100)은 플렉서블할 수 있다.The support substrate 100 may be an insulator. The support substrate 100 may be a metal substrate. In addition, stainless steel (SUS, STS) or the like may be used as a material of the support substrate 100. The support substrate 100 may be divided into various symbols according to the component ratio of the material included, and may include at least one of C, Si, Mn, P, S, Ni, Cr, Mo, or Fe. The support substrate 100 may be flexible.

상기 지지기판(100) 상에 이면전극층(200)이 배치된다. 상기 이면전극층(200)은 도전층이다. 상기 이면전극층(200)은 태양전지 중 상기 광 흡수층(300)에서 생성된 전하가 이동하도록 하여 태양전지의 외부로 전류를 흐르게 할 수 있다. 상기 이면전극층(200)은 이러한 기능을 수행하기 위하여 전기 전도도가 높고 비저항이 작아야 한다.The back electrode layer 200 is disposed on the support substrate 100. The back electrode layer 200 is a conductive layer. The back electrode layer 200 may allow electric current generated in the light absorbing layer 300 of the solar cell to move so that current flows to the outside of the solar cell. The back electrode layer 200 should have high electrical conductivity and low specific resistance in order to perform this function.

또한, 상기 이면전극층(200)은 CIGS 화합물 형성시 수반되는 황(S) 또는 셀레늄(Se) 분위기 하에서의 열처리 시 고온 안정성이 유지되어야 한다. 또한, 상기 이면전극층(200)은 열팽창 계수의 차이로 인하여 상기 지지기판(100)과 박리현상이 발생되지 않도록 상기 지지기판(100)과 접착성이 우수하여야 한다.In addition, the back electrode layer 200 must maintain high temperature stability during heat treatment in a sulfur (S) or selenium (Se) atmosphere accompanying the formation of the CIGS compound. In addition, the back electrode layer 200 should be excellent in adhesion with the support substrate 100 so that the backing layer and the support substrate 100 are not peeled due to a difference in thermal expansion coefficient.

이러한 이면전극층(200)은 몰리브덴(Mo), 금(Au), 알루미늄(Al), 크롬(Cr), 텅스텐(W) 및 구리(Cu) 중 어느 하나로 형성될 수 있다. 이 가운데, 특히 몰리브덴(Mo)은 다른 원소에 비해 상기 지지기판(100)과 열팽창 계수의 차이가 적기 때문에 접착성이 우수하여 박리현상이 발생하는 것을 방지할 수 있고 상술한 이면전극층(200)에 요구되는 특성을 전반적으로 충족시킬 수 있다. 상기 이면전극층(200)은 400nm 내지 1000nm의 두께로 형성될 수 있다.The back electrode layer 200 may be formed of any one of molybdenum (Mo), gold (Au), aluminum (Al), chromium (Cr), tungsten (W), and copper (Cu). In particular, since molybdenum (Mo) has a smaller difference between the support substrate 100 and the coefficient of thermal expansion than other elements, it is possible to prevent the occurrence of peeling phenomenon due to excellent adhesion and to the back electrode layer 200 described above. Overall required properties can be met. The back electrode layer 200 may be formed to a thickness of 400nm to 1000nm.

상기 이면전극층(200) 상에는 광 흡수층(300)이 형성될 수 있다. 상기 광 흡수층(300)은 p형 반도체 화합물을 포함한다. 더 자세하게, 상기 광 흡수층(300)은 Ⅰ-Ⅲ-Ⅵ족 계 화합물을 포함한다. 예를 들어, 상기 광 흡수층(300)은 구리-인듐-갈륨-셀레나이드계(Cu(In,Ga)Se2;CIGS계) 결정 구조, 구리-인듐-셀레나이드계 또는 구리-갈륨-셀레나이드계 결정 구조를 가질 수 있다. 상기 광 흡수층(300)의 에너지 밴드갭(band gap)은 약 1.1eV 내지 1.3eV일 수 있고, 1.5μm 내지 2.5μm의 두께로 형성될 수 있다.The light absorbing layer 300 may be formed on the back electrode layer 200. The light absorption layer 300 includes a p-type semiconductor compound. More specifically, the light absorbing layer 300 includes an I-III-VI group compound. For example, the light absorbing layer 300 is copper-indium-gallium-selenide-based (Cu (In, Ga) Se 2; CIGS-based) crystal structure, a copper-indium-selenide-based or copper-gallium-selenide Crystal structure. The energy band gap of the light absorbing layer 300 may be about 1.1 eV to 1.3 eV, and may be formed to a thickness of 1.5 μm to 2.5 μm.

상기 광 흡수층(300) 상에 버퍼층(400)이 배치된다. CIGS 화합물을 광 흡수층(300)으로 갖는 태양전지는 p형 반도체인 CIGS 화합물 박막과 n형 반도체인 윈도우층(600) 간에 pn 접합을 형성한다. 하지만 두 물질은 격자상수와 밴드갭 에너지의 차이가 크기 때문에 양호한 접합을 형성하기 위해서는 밴드갭이 두 물질의 중간에 위치하는 버퍼층이 필요하다.The buffer layer 400 is disposed on the light absorbing layer 300. The solar cell having the CIGS compound as the light absorbing layer 300 forms a pn junction between the CIGS compound thin film as the p-type semiconductor and the window layer 600 as the n-type semiconductor. However, since the two materials have a large difference between the lattice constant and the band gap energy, a buffer layer in which a band gap is located between two materials is required in order to form a good junction.

상기 버퍼층(400)을 형성하는 물질로는 CdS, ZnS등이 있고 태양전지의 발전 효율 측면에서 CdS가 상대적으로 우수하여 일반적으로 사용되고 있다. 상기 버퍼층(400)은 50nm 내지 80nm의 두께로 형성될 수 있다.Materials for forming the buffer layer 400 include CdS, ZnS and the like, and CdS is relatively used in terms of power generation efficiency of solar cells. The buffer layer 400 may be formed to a thickness of 50nm to 80nm.

상기 버퍼층(400) 상에 고저항 버퍼층(500)이 배치될 수 있다. 상기 고저항 버퍼층(500)은 불순물이 도핑되지 않은 징크 옥사이드(i-ZnO)를 포함할 수 있다. 상기 고저항 버퍼층(500)의 에너지 밴드갭은 약 3.1eV 내지 3.3eV이고 50nm 내지 60nm의 두께로 형성될 수 있다.The high resistance buffer layer 500 may be disposed on the buffer layer 400. The high resistance buffer layer 500 may include zinc oxide (i-ZnO) that is not doped with impurities. The energy band gap of the high resistance buffer layer 500 is about 3.1 eV to 3.3 eV and may be formed to a thickness of 50 nm to 60 nm.

상기 고저항 버퍼층(500) 상에 윈도우층(600)이 배치된다. 상기 윈도우층(600)은 투명하며, 도전층이다. 또한, 상기 윈도우층(600)의 저항은 상기 이면전극층(200)의 저항보다 높다.The window layer 600 is disposed on the high resistance buffer layer 500. The window layer 600 is transparent and is a conductive layer. In addition, the resistance of the window layer 600 is higher than the resistance of the back electrode layer 200.

상기 윈도우층(600)은 산화물을 포함한다. 예를 들어, 상기 윈도우층(600)은 징크 옥사이드(zinc oxide), 인듐 틴 옥사이드(induim tin oxide;ITO) 또는 인듐 징크 옥사이드(induim zinc oxide;IZO), 알루미늄 도핑된 징크 옥사이드(Al doped zinc oxide;AZO) 또는 갈륨 도핑된 징크 옥사이드(Ga doped zinc oxide;GZO) 및, BZO (ZnO:B) 등을 포함할 수 있다.The window layer 600 includes an oxide. For example, the window layer 600 may include zinc oxide, indium tin oxide (ITO) or indium zinc oxide (IZO), and aluminum doped zinc oxide. ; AZO) or gallium doped zinc oxide (GZO), and BZO (ZnO: B).

상기 윈도우층(600)은 100nm 내지 150nm의 두께로 형성될 수 있다. The window layer 600 may be formed to a thickness of 100nm to 150nm.

상기 윈도우층(600) 상에는 불순물 도핑층(700)이 형성될 수 있다. 상기 불순물 도핑층(700)은 징크 옥사이드(ZnO) 또는 인듐 틴 옥사이드(induim tin oxide;ITO)를 포함할 수 있으며, 불순물로 몰리브덴(Mo)을 포함할 수 있다.An impurity doped layer 700 may be formed on the window layer 600. The impurity doping layer 700 may include zinc oxide (ZnO) or indium tin oxide (ITO), and may include molybdenum (Mo) as an impurity.

상기 불순물 도핑층(700)은 120nm 내지 200nm의 두께로 형성될 수 있다. The impurity doped layer 700 may be formed to a thickness of 120nm to 200nm.

상기 불순물 도핑층(700)의 에너지 밴드갭은 3.2eV 내지 3.6eV의 값을 가질 수 있다.The energy band gap of the impurity doped layer 700 may have a value of 3.2 eV to 3.6 eV.

일반적으로 윈도우층은 전기 전도성을 위해 800nm 내지 1000nm의 두께로 형성되나, 두꺼워지면 광투과율이 감소하는 문제점이 존재한다. 발명의 실시예에서는 상기 윈도우층(600)을 100nm 내지 150nm의 얇은 두께로 형성함으로써 광 투과율을 향상시키고, 윈도우층의 두께가 얇아짐으로써 전기전도성이 감소하는 문제는 상기 불순물 도핑층(700)에 의해 개선될 수 있다.In general, the window layer is formed to a thickness of 800nm to 1000nm for the electrical conductivity, but there is a problem that the light transmittance is reduced when thick. In an embodiment of the present invention, the window layer 600 is formed to have a thin thickness of 100 nm to 150 nm to improve light transmittance, and the thickness of the window layer is reduced so that the electrical conductivity is reduced to the impurity doping layer 700. Can be improved.

상기 윈도우층(600)이 BZO로 형성되고, 상기 불순물 도핑층(700)이 MZO의 화학식을 갖도록 형성되는 경우, 상기 윈도우층(600)의 텍스처링 상면에 불순물 도핑층(700)이 형성될 수 있으므로 텍스처링을 갖는 상부 윈도우층의 제작이 가능하다. 이에 따라 광의 흡수율을 향상시킬 수 있다.When the window layer 600 is formed of BZO, and the impurity doping layer 700 is formed to have a chemical formula of MZO, the impurity doping layer 700 may be formed on the upper surface of the texturing of the window layer 600. It is possible to fabricate an upper window layer with texturing. Thereby, the light absorption rate can be improved.

본 발명의 실시예에 따른 태양전지에 따르면, 윈도우층을 얇게 형성하여 높은 투과율과 전기전도성을 갖는 윈도우층을 제공할 수 있다. 또한 버퍼층과 윈도우층의 밴드갭 격차를 감소시켜 광-전 변환 효율이 향상될 수 있다.According to the solar cell according to the embodiment of the present invention, the window layer may be thinly provided to provide a window layer having high transmittance and electrical conductivity. In addition, the photoelectric conversion efficiency may be improved by reducing the band gap gap between the buffer layer and the window layer.

지지기판 상에 형성된 배리어층에 의해 금속물질을 포함하는 지지기판 내에 포함되는 금속물질이 광 흡수층으로 확산되어 효율이 감소되는 것을 개선할 수 있어, 소자의 신뢰성이 향상될 수 있다.
By the barrier layer formed on the support substrate, it is possible to improve that the metal material included in the support substrate including the metal material is diffused into the light absorbing layer to reduce the efficiency, thereby improving the reliability of the device.

도 2 내지 도 5는 실시예에 따른 태양전지의 제조방법을 도시한 단면도들이다. 본 제조방법에 관한 설명은 앞서 설명한 태양전지에 대한 설명을 참고한다. 앞서 설명한 태양전지에 대한 설명은 본 제조방법에 관한 설명에 본질적으로 결합될 수 있다.2 to 5 are cross-sectional views illustrating a method of manufacturing a solar cell according to an embodiment. For a description of the present manufacturing method, refer to the description of the solar cell described above. The description of the solar cell described above may be essentially combined with the description of the present manufacturing method.

도 2를 참조하면, 지지기판(100) 상에 이면전극층(200)이 형성된다. 상기 이면전극층(200)은 몰리브덴을 사용하여 증착될 수 있다. 상기 이면전극층(200)은 스퍼터링(Sputtering)의 방법으로 형성될 수 있다. 또한, 상기 지지기판(100) 및 이면전극층(200) 사이에 확산방지막 등과 같은 추가적인 층이 개재될 수 있다.Referring to FIG. 2, the back electrode layer 200 is formed on the support substrate 100. The back electrode layer 200 may be deposited using molybdenum. The back electrode layer 200 may be formed by a sputtering method. In addition, an additional layer such as a diffusion barrier may be interposed between the support substrate 100 and the back electrode layer 200.

도 3을 참조하면, 상기 이면전극층(200) 상에 광 흡수층(300)이 형성된다. 상기 광 흡수층(300)은 예를 들어, 구리, 인듐, 갈륨, 셀레늄을 동시 또는 구분하여 증발(evaporation)시키면서 구리-인듐-갈륨-셀레나이드계(Cu(In,Ga)Se2;CIGS계)의 광 흡수층(300)을 형성하는 방법과 금속 프리커서 막을 형성시킨 후 셀레니제이션(Selenization) 공정에 의해 형성시키는 방법이 폭넓게 사용되고 있다.Referring to FIG. 3, a light absorbing layer 300 is formed on the back electrode layer 200. For example, the light absorbing layer 300 may be formed of copper-indium-gallium-selenide (Cu (In, Ga) Se2; CIGS) while simultaneously evaporating copper, indium, gallium, and selenium. A method of forming the light absorbing layer 300 and a method of forming a metal precursor film and then forming it by a selenization process are widely used.

이와는 다르게, 상기 구리 타겟, 인듐 타겟, 갈륨 타겟을 사용하는 스퍼터링 공정 및 상기 셀레니제이션 공정은 동시에 진행될 수 있다. 또한, 구리 타겟 및 인듐 타겟 만을 사용하거나, 구리 타겟 및 갈륨 타겟을 사용하는 스퍼터링 공정 및 셀레니제이션 공정에 의해서, CIS계 또는 CIG계 광 흡수층(300)이 형성될 수 있다.Alternatively, the copper target, the indium target, the sputtering process using the gallium target, and the selenization process may be performed simultaneously. In addition, a CIS-based or CIG-based light absorbing layer 300 may be formed by a sputtering process and a selenization process using only a copper target and an indium target, or using a copper target and a gallium target.

다음으로, 상기 광 흡수층(300) 상에 버퍼층(400)이 형성된다. 상기 버퍼층(400)은 CdS의 화학식으로 형성될 수 있으며, PVD(Physical Vapor Deposition) 또는 MOCVD (Metal-Organic Chemical Vapor Deposition)의 방법으로 형성될 수 있고, 이에 대해 한정하는 것은 아니다.Next, a buffer layer 400 is formed on the light absorbing layer 300. The buffer layer 400 may be formed by the chemical formula of CdS, and may be formed by a method of physical vapor deposition (PVD) or metal-organic chemical vapor deposition (MOCVD), but is not limited thereto.

도 4를 참고하면, 상기 버퍼층(400) 상에 고저항 버퍼층(500)이 형성된다. 상기 고저항 버퍼층(500)은 ZnO의 화학식으로 형성될 수 있다.Referring to FIG. 4, a high resistance buffer layer 500 is formed on the buffer layer 400. The high resistance buffer layer 500 may be formed of a chemical formula of ZnO.

다음으로, 상기 고저항 버퍼층(500) 상에 윈도우층(600)이 형성된다. 상기 윈도우층(600)은 투명한 도전물질, 예를 들어, 알루미늄 도핑된 징크 옥사이드(Al doped zinc oxide;AZO), 징크 옥사이드(zinc oxide), 인듐 틴 옥사이드(induim tin oxide;ITO), 인듐 징크 옥사이드(induim zinc oxide;IZO), 갈륨 도핑된 징크 옥사이드(Ga doped zinc oxide;GZO) 및, BZO (ZnO:B) 중의 적어도 하나의 화학식으로 형성될 수 있으며, 스퍼터링의 방법으로 증착될 수 있다.Next, the window layer 600 is formed on the high resistance buffer layer 500. The window layer 600 may be a transparent conductive material, for example, aluminum doped zinc oxide (AZO), zinc oxide, zinc tin oxide, indium tin oxide (ITO), or indium zinc oxide. (induim zinc oxide; IZO), gallium doped zinc oxide (Ga doped zinc oxide; GZO), and BZO (ZnO: B) may be formed by a chemical formula, and may be deposited by sputtering.

상기 윈도우층(600)은 100nm 내지 150nm의 두께로 형성될 수 있다. 상기 윈도우층(600)의 저항은 상기 이면전극층(200)의 저항보다 높다.The window layer 600 may be formed to a thickness of 100nm to 150nm. The resistance of the window layer 600 is higher than that of the back electrode layer 200.

도 5를 참고하면, 상기 윈도우층(600) 상에 불순물 도핑층(700)이 형성된다. 상기 불순물 도핑층(700)은 스퍼터링의 방법으로 형성될 수 있으며, 이에 대해 한정하지는 않는다. 상기 불순물 도핑층(700)은 징크 옥사이드(ZnO) 또는 인듐 틴 옥사이드(induim tin oxide;ITO)를 포함할 수 있으며, 불순물로 몰리브덴(Mo)을 포함할 수 있다. 상기 불순물 도핑층(700)은 120nm 내지 200nm의 두께로 형성될 수 있다.Referring to FIG. 5, an impurity doping layer 700 is formed on the window layer 600. The impurity doped layer 700 may be formed by a sputtering method, but is not limited thereto. The impurity doping layer 700 may include zinc oxide (ZnO) or indium tin oxide (ITO), and may include molybdenum (Mo) as an impurity. The impurity doped layer 700 may be formed to a thickness of 120nm to 200nm.

이상에서 실시예를 중심으로 설명하였으나 이는 단지 예시일 뿐 본 발명을 한정하는 것이 아니며, 본 발명이 속하는 분야의 통상의 지식을 가진 자라면 본 실시예의 본질적인 특성을 벗어나지 않는 범위에서 이상에 예시되지 않은 여러 가지의 변형과 응용이 가능함을 알 수 있을 것이다. 예를 들어, 실시예에 구체적으로 나타난 각 구성 요소는 변형하여 실시할 수 있는 것이다. 그리고 이러한 변형과 응용에 관계된 차이점들은 첨부된 청구 범위에서 규정하는 본 발명의 범위에 포함되는 것으로 해석되어야 할 것이다.While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood that various modifications and applications are possible. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

Claims (11)

지지기판;
상기 지지기판 상에 형성된 이면전극층;
상기 이면전극층 상에 형성된 광 흡수층;
상기 광 흡수층 상에 복수개로 형성되는 버퍼층;
상기 버퍼층 상에 형성된 윈도우층; 및,
상기 윈도우층 상에 형성된 불순물 도핑층을 포함하고 ,
상기 불순물 도핑층은 Mo를 포함하는 태양전지.A support substrate;
A back electrode layer formed on the support substrate;
A light absorbing layer formed on the back electrode layer;
A plurality of buffer layers formed on the light absorbing layer;
A window layer formed on the buffer layer; And
An impurity doping layer formed on the window layer ;
The impurity doped layer includes Mo. 제1항에 있어서,
상기 버퍼층과 윈도우층 사이에 형성되는 고저항 버퍼층;을 더 포함하는 태양전지.The method of claim 1,
And a high resistance buffer layer formed between the buffer layer and the window layer. 제2항에 있어서,
상기 고저항 버퍼층은 ZnO의 화학식으로 형성되는 태양전지.3. The method of claim 2,
The high resistance buffer layer is a solar cell formed of the chemical formula of ZnO. 제1항에 있어서,
상기 윈도우층은 100nm 내지 150nm의 두께로 형성되는 태양전지.The method of claim 1,
The window layer is a solar cell formed to a thickness of 100nm to 150nm. 제1항에 있어서,
상기 불순물 도핑층은 120nm 내지 200nm의 두께로 형성되는 태양전지.The method of claim 1,
The impurity doped layer is a solar cell formed to a thickness of 120nm to 200nm. 삭제delete 제1항에 있어서,
상기 불순물 도핑층의 에너지 밴드갭은 3.2eV 내지 3.6eV의 범위로 형성되는 태양전지.The method of claim 1,
The energy band gap of the impurity doped layer is formed in the range of 3.2eV to 3.6eV. 제1항에 있어서,
상기 윈도우층의 상면은 텍스처링의 구조로 형성되는 태양전지.The method of claim 1,
An upper surface of the window layer is formed of a texturing structure. 지지기판 상에 이면전극층을 형성하는 단계;
상기 이면전극층 상에 광 흡수층을 형성하는 단계;
상기 광 흡수층 상에 버퍼층을 형성하는 단계;
상기 버퍼층 상에 윈도우층을 형성하는 단계; 및,
상기 윈도우층 상에 Zn, O 및 Mo를 포함하는 불순물 도핑층을 형성하는 단계;를 포함하는 태양전지의 제조방법.Forming a back electrode layer on the support substrate;
Forming a light absorbing layer on the back electrode layer;
Forming a buffer layer on the light absorbing layer;
Forming a window layer on the buffer layer; And
Forming an impurity doping layer comprising Zn, O, and Mo on the window layer. 삭제delete 제9항에 있어서,
상기 윈도우층은 100nm 내지 150nm의 두께로 형성되고, 상기 불순물 도핑층은 120nm 내지 200nm의 두께로 형성되는 태양전지의 제조방법.10. The method of claim 9,
The window layer is formed to a thickness of 100nm to 150nm, the impurity doping layer is formed of a thickness of 120nm to 200nm.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101091319B1 (en) 2009-06-30 2011-12-07 엘지이노텍 주식회사 Solar cell and method of fabricating the same
KR20120012324A (en) * 2010-07-30 2012-02-09 엘지이노텍 주식회사 Solar cell and method of fabricating the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101091319B1 (en) 2009-06-30 2011-12-07 엘지이노텍 주식회사 Solar cell and method of fabricating the same
KR20120012324A (en) * 2010-07-30 2012-02-09 엘지이노텍 주식회사 Solar cell and method of fabricating the same

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