KR101381597B1 - Pattern-aware management system for multi-channel ssd and method therefor - Google Patents

Abstract

A pattern-based SSD management system according to the present invention includes: a write buffer; a flash conversion layer unit; and a NAND flash memory unit. The write buffer includes: a pattern detection module which determines the pattern of the data to be written in the NANA flash memory unit; a singular victim selection module which selects and evicts one victim block when the pattern of the data to be written is sequential according to the determination results of the pattern detection module; and a multi-victim selection module which selects and evicts multiple victim blocks when the pattern of the data to be written is random according to the determination results of the pattern detection module. [Reference numerals] (AA) Comparative example 1; (BB) Example 1

Description

Pattern-based management system and method of multi-channel SSD {Pattern-Aware Management System for Multi-Channel SSD and Method therefor}

The present invention relates to a pattern-based management system and method for a multichannel SSD. More specifically, the present invention relates to a pattern-based write buffer for multichannel SSD and an integrated management technique of FTL.

Recently, as processing speeds of main memory devices such as processors and RAMs used in many electronic products have been increased, bottlenecks in which computational processing speeds of electronic products are determined by processing speeds of auxiliary memory devices have increased. have. Existing auxiliary memory devices have been mainly used magnetic storage devices such as HDD (Hard Disk Drive), or optical disk devices (ODD: Optic Disk Drive) such as CD or DVD. Optical disk devices have a disadvantage in that data input / output is limited and data output speed is very slow. Magnetic storage devices are also faster than optical disk devices, but still cause bottlenecks. Moreover, the magnetic storage device may be easily damaged or lost due to external impact.

Accordingly, attention has been paid to solid state drives (SSDs) composed of semiconductor devices using a conventional MOSFET structure. SSDs are faster than HDDs and provide random access to devices that store data, allowing high-speed data input and output without searching. In addition, the mechanical point or failure rate is significantly low, and the data damage rate from external shock is very low. In addition, SSDs consume less power and can run with lower heat, lower noise and lower power without the need for additional machinery. therefore. Compared to HDD, the final product including SSD can be miniaturized and quantified.

SSDs generally include NOR flash memory and NAND flash memory. Among them, NAND flash memory is connected in series, and the circuit density is high, so that a large capacity is easily manufactured and the read and / or write speed is high. In addition, NAND flash memory is used as a large capacity SSD because of its excellent data storage capability.

The SSD interior consists of several NAND flash memories, a Flash Translation Layer (FTL), and a write buffer. In SSDs, the main storage medium is NAND flash memory, which is composed of multi-channel and multi-way to increase performance by increasing input / output (I / O) parallelism.

In general, increasing the I / O parallelism of writes and reads can increase garbage collection (GC) overhead.

Accordingly, there is an increasing need for a method and system capable of reducing garbage collection overhead while increasing I / O parallelism in a multichannel SSD to improve performance of a multichannel SSD.

Korean Laid-Open Publication No. 2008-0059461 (2008.06.27)

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art, by adaptively applying the write buffer and FTL policy in consideration of the pattern characteristics, while increasing the read and write I / O parallelism of the multi-channel SSD while the garbage collection (GC) The present invention provides a pattern-based management system and method of a multichannel SSD that can reduce SSD overhead to improve SSD performance.

The technical objects to be achieved by the present invention are not limited to the above-mentioned technical problems, and other technical subjects which are not mentioned can be clearly understood by those skilled in the art from the description of the present invention .

The pattern-based management system of a multi-channel SSD according to an embodiment of the present invention includes a write buffer, a flash translation layer unit, and a NAND flash memory unit, wherein the write buffer: determines a pattern of data to be written to the NAND flash memory unit. A pattern detection module; A single big team selecting module for selecting and extracting one big team block when the pattern of the data to be written is a sequential pattern as a result of the determination of the pattern detecting module; And a multi-victim selection module for selecting and extracting a plurality of Victim blocks when the pattern of the data to be written is a random pattern as a result of the determination of the pattern detection module.

According to an embodiment of the present invention, a method of managing a pattern-based management system for a multichannel SSD including a write buffer, a flash translation layer unit, and a NAND flash memory unit may include: a pattern detection module included in the write buffer; Determining a pattern of data to be written; Selecting and extracting one Victim block when the pattern of the data to be written is a sequential pattern as a result of the determination of the pattern detection module; And selecting and evicting a plurality of Victim blocks when the pattern of the data to be written is a random pattern as a result of the determination of the pattern detection module.

According to the present invention, by applying the write buffer and FTL policy in consideration of the pattern characteristics of the data to be written, SSD by reducing the garbage collection (GC) overhead while increasing the read and write I / O parallelism of the multi-channel SSD It is possible to provide a pattern-based management system and method of a multi-channel SSD that can improve performance.

1 is a structural diagram of a pattern-based management system for an SSD according to an embodiment of the present invention.
2 illustrates a write and erase process of a NAND flash memory.
3 illustrates a garbage collection process in a NAND flash memory.
4 illustrates sequential pattern management in a pattern based management system for an SSD according to an embodiment of the present invention.
5 illustrates a memory write process of a multichannel FTL.
6 illustrates random pattern management in a pattern based management system for an SSD according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a detailed description of preferred embodiments of the present invention will be given with reference to the accompanying drawings. However, the embodiments of the present invention may be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below. The shape and the size of the elements in the drawings may be exaggerated for clarity of explanation and the same reference numerals are used for the same elements and the same elements are denoted by the same quote symbols as possible even if they are displayed on different drawings Should be. In the following description, well-known functions or constructions are not described in detail to avoid unnecessarily obscuring the subject matter of the present invention.

1 is a structural diagram of a pattern-based management system 100 for a multi-channel SSD according to an embodiment of the present invention. As shown in FIG. 1, the pattern-based management system 100 for an SSD according to an exemplary embodiment of the present invention may include a write buffer 200, a flash translation layer unit 300 (FTL), and a NAND flash memory unit 400. It may include.

First, the general functions of the NAND flash memory, the FTL, and the write buffer included in the SSD according to an embodiment of the present invention will be described first.

In general, NAND flash memory is composed of several blocks, and one block is composed of several pages. For example, one block may consist of 64 pages, one block may be 128KB in size, and one page may be 2KB in size.

There are three basic operations of NAND flash memory: read, write and erase. Reads and writes to NAND flash memory occur in pages and erases occur in blocks.

2 illustrates a write and erase process of a NAND flash memory. Fig. 2 shows the "Erase-before-write" characteristic of the NAND flash memory. That is, in NAND flash memory, in order to update data of a specific page, it is not possible to directly write to the position, but after erasing one block. As shown in FIG. 2A, a case in which data A needs to be updated to A * on the first page of one block is illustrated. For this purpose, as shown in Fig. 2B, the entire block including the data A must be erased. Thereafter, as shown in FIG. 2C, A * may be written to the corresponding page.

Each of the first memories 410 through n-th memory 4n0 included in the NAND flash memory 400 illustrated in FIG. 1 may be a NAND flash memory.

The flash translation layer (FTL) is a configuration for using a block device interface used by a hard disk drive (HDD) in an SSD. The flash translation layer can solve the above-described write erase problem of the NAND flash memory by converting a virtual address into a physical address through address mapping.

The flash translation layer (FTL) performs a garbage collection (GC) operation. This garbage collection operation is designed to collect inactive pages to make free space, which greatly affects SSD performance.

3 illustrates a garbage collection process in a NAND flash memory. As shown in Fig. 3 (a), when trying to update A and B, update data A * and B * are written to another position of the same block K1 without updating directly on the page where A and B are located. . In this case, the page where the conventional A and B are stored is deactivated. As shown in Fig. 3B, A * and B * data are read from the conventional block K1 and written into a new block K2. Finally, as shown in Fig. 3C, the conventional block k1 containing the deactivated data A and B is erased. At this time, the process as shown in Figure 3 (b) and (c) may be referred to as a garbage collection process.

The write buffer is used to improve performance by buffering data in which write operations are frequently performed by using RAM to compensate for the slower write operation of the NAND flash memory. The write operation of NAND flash memory is slower than the read operation may be further increased by garbage collection operations. In addition, the write buffer may improve the write performance to the NAND flash memory by converting a random write request into a sequential write request. This conversion can reduce garbage collection operations in NAND flash memory, thereby improving write performance.

To improve SSD performance, it is necessary to take advantage of the multichannel nature of SSD to reduce garbage collection overhead while increasing I / O parallelism. There is a need for an algorithm for the Flash translation layer (FTL) and a write buffer algorithm.

However, there is a trade-off between increased I / O parallelism and reduced garbage collection overhead. For example, using multichannel FTL may increase write and read I / O parallelism to NAND flash memory, but may result in high garbage collection overhead. In addition, when the multi-channel write buffer is used, write I / O parallelism to NAND flash memory is increased and low garbage collection overhead occurs, but read I / O parallelism is reduced.

In other words, when I / O parallelism to NAND flash memory increases, garbage collection overhead also increases.

Therefore, in the embodiment of the present invention, the performance of the SSD may be improved by adaptively using the write buffer and the flash translation layer algorithm according to the pattern characteristic of the data to be written. That is, a sequential pattern and a random pattern can be distinguished, and an algorithm of a write buffer and a flash translation layer suitable for each case can be used.

More specifically, the sequential pattern represents a characteristic of cold data that is not updated frequently. This means less garbage collection operations. Thus, for data with sequential patterns, it may be important to increase read and write I / O parallelism over efforts to reduce garbage collection overhead.

The random pattern represents a characteristic of hot data that is frequently updated. Thus, for data with random patterns, it may be important to reduce garbage collection overhead rather than to increase read and write I / O parallelism.

It is desirable to apply different management policies according to such pattern characteristics of the data to be written. Accordingly, an embodiment of the present invention is to provide an integrated management scheme of a pattern-based write buffer and FTL in a multichannel SSD. According to an embodiment of the present invention, the write buffer and the FTL policy for each of them are differently applied in consideration of the characteristics of sequential patterns and random patterns, thereby increasing read and write I / O parallelism to NAND flash memory and reducing garbage collection overhead. You can. Accordingly, the performance of the multichannel SSD can be improved.

Referring back to Figure 1 looks at in detail with respect to the pattern-based management system 100 and method of the multi-channel SSD according to an embodiment of the present invention. As shown in FIG. 1, the pattern-based management system 100 of a multichannel SSD according to an exemplary embodiment of the present invention uses a NAND flash memory unit using a multichannel FTL 311 and a single big team write buffer in a sequential pattern. Write and read management to the 400 is performed, and in the case of a random pattern, write and read management to the NAND flash memory unit 400 may be performed using the single channel FTL 321 and the multi-team write buffer.

The write buffer 200 according to the embodiment of the present invention includes a pattern detection module 210, a single big team selection module 211, a multi big team selection module 221, a sequential padding module 212 and / or a channel assignment module 222. It may be configured to include). In addition, the flash conversion layer unit 300 according to an embodiment of the present invention may include both a multi-channel flash conversion layer 311 and a plurality of single channel flash conversion layer 321. By configuring the write buffer 200 and the flash conversion layer 300 in this way, it is possible to appropriately manage each of the sequential pattern and the random pattern.

The pattern detection module 210 determines a pattern of a block to be selected as a Victim in the write buffer 200. The write buffer 200 may be managed, for example, in block-level least recently used (LRU) units, and the unit of the big team is a block. The pattern detection module 210 may determine a sequential pattern when the number of consecutive active pages in the Victim block, that is, the number of pages to be written in the NAND flash memory 400 is greater than or equal to a specific threshold. In addition, the pattern detection module 210 may determine a random pattern when the number of consecutive active pages in the Victim block, that is, the number of pages to be written in the NAND flash memory unit 400 is less than a specific threshold value. Here, the threshold may be set differently according to the embodiment according to the garbage collection overhead and the degree of I / O parallelism to be achieved through the system 100. According to the exemplary embodiment of the present invention, the pattern is detected in the write buffer 200, so that accurate pattern determination is possible.

If it is determined that the result of the pattern detection module 210 is a sequential pattern, it is subsequently managed according to the sequential pattern management policy. 4 illustrates sequential pattern management in the pattern-based management system 100 for an SSD according to an embodiment of the present invention.

The sequential pattern has a feature of infrequently updating, so the garbage collection overhead is relatively small. Therefore, I / O parallelism can be increased by using the multichannel FTL 311 to maximize read and write I / O parallelism. In addition, when selecting a big team in the write buffer 200, only one block is selected as a big team and eviction. In this case, the function of selecting and extracting only one block as the big team from the write buffer 200 may be performed through the single big team selecting module 211 shown in FIG. 1.

As shown in FIG. 4, the write buffer 200 may include a plurality of Victim blocks 201,..., 204, which may be arranged according to the block unit LRU. At this time, it is illustrated that the most frequently used block 201 among the plurality of Victim blocks 201, 204, 204 is the lowest. At this time, the data stored in the page has a sequential pattern from 0 to 15 is illustrated. As described above, when the data to be written indicates a sequential pattern, the single big team selecting module 211 selects and removes the block 201 having the lowest frequency of use from the write buffer 200.

In this case, the multi-channel flash translation layer 311 (multi-channel FTL) may distribute the data stored in the block into a plurality of channels to be written to the NAND flash memory unit 400. For example, it may be distributed in separate channels in units of pages constituting the block 201. For example, a page including data 0 may be written to the first memory 410 using the first channel through the multichannel FTL 311, and similarly, a page including data 3 may be written to the multichannel FTL 311. ) Can be written to the nth memory 4n0 using the nth channel.

5 illustrates a memory write process of the multichannel FTL 311. Data (0, 1, 2, 3) stored in each page included in one Victim block 201 is included in the NAND flash memory unit 400 through one of a plurality of channels of the multi-channel FTL 311. The first memory 410 to n-th memory 4n0 may be written. For example, the data 0 stored in the first page of the block 201 may be written to the first memory 410 through the first channel of the multi-channel FTL 311. Similarly, data 1, 2, and 3 may be written to the second memory 420 to the nth memory 4n0, respectively.

As shown in FIG. 1, the write buffer 200 according to the embodiment of the present invention may further include a sequential padding module 212. The sequential padding module 212 reads data from the NAND flash memory unit 400 when the Victim block 201 selected by the single Victim selection module 211 has a sequential pattern but all pages in the block are not activated. Activate all pages in the block. In this way, I / O parallelism can be further maximized by sequentially activating all the pages in the block 2010, and the management overhead in the multi-channel FTL 311 can be reduced. The head can also be reduced.

If it is determined that the data to be written as a result of the pattern detection module 210 has a random pattern, it is subsequently managed according to the random pattern management policy. 6 illustrates random pattern management in a pattern based management system 100 for an SSD according to an embodiment of the present invention.

The random pattern is characterized by frequent updates. Therefore, it is very important to reduce garbage collection overhead. In order to reduce garbage collection overhead, a plurality of single channel FTLs 321 having one channel may be used in an embodiment of the present invention. This reduction in read and write I / O parallelism can be overcome by selecting as many Victims as the number of channels at once when selecting the Victims in the write buffer 200 and assigning them to each channel. When the big team is selected in the write buffer 200, a plurality of blocks are selected as the big team and eviction. In this case, the function of selecting and extracting a plurality of blocks as a big team from the write buffer 200 may be performed through the multi-big team selection module 221 shown in FIG. 1. This reduces read I / O parallelism for one block, but assumes a very small impact because it is a random pattern.

As shown in FIG. 6, the write buffer 200 may include a plurality of Victim blocks 201,..., 204, which may be arranged according to the block unit LRU. In this case, the multi-big team selection module 221 may select and evoke the plurality of big team blocks 201, ..., 204 in order of low frequency of use among the plurality of big team blocks 201, ..., 204. have. At this time, it is illustrated that the data stored in the page has an arbitrary pattern.

The plurality of Victim blocks selected and evicted by the multi-victim selection module 221 of the write buffer 200 are allocated to the single channel FTL 321 through the channel allocation module 222. That is, the Victim block denoted by 201 may be allocated to the first single channel FTL 321_1 to be written to the NAND flash memory unit 400 through the first channel. Similarly, the Victim block denoted by 204 may be allocated to the nth single channel FTL 321_n and written to the NAND flash memory unit 400 through the nth channel.

As described above, the plurality of big teams selected through the multi-big team selection module 221 in the write buffer 200 are allocated to each channel through the channel assignment module 222. In this case, in the case of a new block, wear leveling may be performed by equalizing the number of erasing per channel by assigning the least number of erasing of each channel. In addition, in the case of a block already allocated to the channel, by allocating to the same channel, it is possible to reduce the migration overhead between channels.

Some or all of the write buffer 200 and / or flash translation layer 300 according to an embodiment of the present invention may be implemented as hardware modules and / or software modules that enable the computing system to perform the functions described above. Can be.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. will be. Therefore, it should be understood that the above-described embodiments are to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than the foregoing description, It is intended that all changes and modifications derived from the equivalent concept be included within the scope of the present invention.

100: pattern-based management system of multi-channel SSD
200: write buffer
210: pattern detection module
211: Single Big Team Selection Module
221; Multi-Big Team Selection Module
212: Sequential Padding Module
222: channel allocation module
300: flash conversion layer
311: multichannel FTL
321: single channel FTL
400: NAND flash memory section

Claims (9)

A pattern-based management system of a multichannel SSD including a write buffer, a flash translation layer unit, and a NAND flash memory unit,
The write buffer is:
A pattern detection module that determines a pattern of data to be written to the NAND flash memory unit;
A single big team selecting module for selecting and extracting one big team block when the pattern of the data to be written is a sequential pattern as a result of the determination of the pattern detecting module; And
And a multi-team selection module for selecting and evicting a plurality of big team blocks when the pattern of the data to be written is a random pattern as a result of the determination of the pattern detection module.
Pattern based management system of multi-channel SSD. The method of claim 1,
The flash conversion layer unit:
A multi-channel flash conversion layer for distributing data included in the one big team block selected and evicted by the single big team selection module through a plurality of channels to be written to the NAND flash memory unit; And
And a plurality of single channel flash conversion layers configured to receive the plurality of Victim blocks selected and evicted through the multi-victim selection module one by one and write them to the NAND flash memory through a separate channel.
Pattern based management system of multi-channel SSD. 3. The method of claim 2,
The write buffer is:
And a sequential padding module configured to read data from the NAND flash memory unit and to activate an unactivated page in the one Victim block selected and evicted through the single Victim selection module.
Pattern based management system of multi-channel SSD. The method according to claim 2 or 3,
The write buffer is:
And a channel allocation module for assigning each of the plurality of Victim blocks selected and evicted through the multi-victim selection module to the plurality of single channel flash translation layers.
Pattern based management system of multi-channel SSD. A method of managing a pattern-based management system of a multichannel SSD including a write buffer, a flash conversion layer unit, and a NAND flash memory unit,
Determining a pattern of data to be written to the NAND flash memory unit by a pattern detection module included in the write buffer;
Selecting and extracting one Victim block when the pattern of the data to be written is a sequential pattern as a result of the determination of the pattern detection module; And
Selecting and evicting a plurality of Victim blocks when the pattern of the data to be written is a random pattern as a result of the determination of the pattern detection module;
A method of managing pattern-based management system of multi-channel SSD. 6. The method of claim 5,
After the step of selecting and ousting one Big Team block:
The method may further include distributing data included in the one Victim block through a plurality of channels through the multi-channel flash conversion layer included in the flash conversion layer unit and writing the data to the NAND flash memory unit.
A method of managing pattern-based management system of multi-channel SSD. 6. The method of claim 5,
After selecting and evicting the plurality of Victim blocks:
And receiving the plurality of Victim blocks one by one through a plurality of single channel flash conversion layers included in the flash conversion layer unit and writing the plurality of Victim blocks to the NAND flash memory unit through a separate channel.
A method of managing pattern-based management system of multi-channel SSD. The method according to claim 6,
Before the above write step:
And reading data from the NAND flash memory unit to activate a page that is not activated in the one big block.
A method of managing pattern-based management system of multi-channel SSD. 8. The method of claim 7,
Before the above write step:
Allocating each of the plurality of Victim blocks to the plurality of single channel flash translation layers;
A method of managing pattern-based management system of multi-channel SSD.

Images