KR101363608B1 - Burn-in board test jig - Google Patents

Abstract

The present invention relates to a jig for testing a burn-in board, which can test whether an NC signal line (or NC contact) is short, wherein the NC signal line (or NC contact) is an unused signal line but may be in a memory device and more particularly, to a jig for testing a burn-in board to be measured a parallel short resistance value by a testing device while the signal line is short with the NC signal line by connecting a device jig to the signal line in order to recognize as a single signal by binding only the NC contact and connecting to the extending signal line unused for a BBT tester in order to recognize an NC signal as a single signal line. [Reference numerals] (AA) Signal line

Description

Burn-in board test jig {Burn-in board test jig}

The present invention relates to a burn-in board test jig, and in detail, a burn-in board test jig that can test whether a short of a signal line (NC line or NC contact) present in a memory device but not in use is tested. It is about.

More specifically, the present invention connects the signal line in the device jig so that only the NC contact can be recognized as a single signal, and connected to an extension signal line (NC signal line, hereinafter referred to as "NC signal line") that is not used in the BBT tester. By allowing the NC signal to be recognized as one signal line, when the signal line and the NC signal line are short-circuited, the parallel short-circuit resistance value is related to the one-time board test jig to be measured by the inspection equipment.

In general, a burn-in test for filtering out an initial defect of a memory device was developed to remove the initial defect from a U-curve graph that the defect increases at the time when the memory defect reaches its initial and end of life. In order to filter out the initial defects, the test is performed by creating a stress-induced environment, that is, a burn-in environment, in which the device is subjected to sufficient stress in the high and low temperature environments so that the initial defect can be stressed.

Burn-in test apparatus for burn-in test of the semiconductor memory has been made in various ways depending on the type and size of the memory. For example, a method of mounting a socket on a main board and then soldering it, or a method of mounting a socket on a device under test (DUT) board and then interconnecting a connector on the main board and a connector on the DUT board. In this case, after the DUT board is mounted on the main board, pressure is applied through the jig device so that the connectors on both sides are coupled. As a technology related to such a burn-in test apparatus, there are various technologies including Patent Documents 1 to 3.

Patent document 1 relates to a monitor board monitoring device of a burn-in test apparatus for monitoring a connection state between a drive power supply unit and a monitor board so that a surge voltage is not generated on the burn-in board. The board may include a printed circuit board having wiring for connecting the semiconductor to the test burn-in board; A plurality of sockets attached to a printed circuit board for mounting the plurality of semiconductors; A plurality of soldering holes electrically connected to the terminals of the sockets, the plurality of soldering holes arranged in a vertical direction at both ends of the printed circuit board, and arranged in a straight line in the horizontal direction; And pins fixed to the soldering holes one by one.

In addition, Patent Document 3 is connected to the tester, the main controller for receiving the resistance measurement value of each signal line of the burn-in board from the tester, the driver control means interface for receiving the operating state of the pusher from the drive control means, the drive control means interface If it is confirmed that the push operation by the pusher is completed, the determination unit for confirming whether an error has occurred according to the resistance measurement value of the tester at the preset time point, and if an error occurs as a result of the confirmation of the determination unit, an error signal is generated to generate an error signal. The present invention relates to a burn-in board test apparatus including an error signal generator configured to transmit a signal.

Such a conventional burn-in test apparatus is provided with an address, various clocks, a power supply, a SCAN, and a data signal line for writing / reading a value to an actual device. The address corresponds to the address of each cell of the memory device, the clock is a control signal used to determine whether to read or write the memory, and the SCAN divides the memory area of the burn-in board due to lack of data (I / o). This signal enables the device to be activated and read / written. It is divided into high / low SCAN. The number of SCANs currently available in the system is SCAN0 to SCAN31. Write can be written to all burn-in board at the same time, or can be partially written. Read must be partially read due to lack of data (I / o). In case of read, it determines fail / pass and fail / pass.

In the conventional burn-in test apparatus, as illustrated in FIG. 4, a plurality of DUT boards 200 are mounted on one main board 100, and a memory to be tested is mounted on each DUT board.

This burn-in board is provided with a memory device with contacts, as shown in FIG. 5 in the drawing. This memory device has a plurality of signal lines. That is, as shown in an enlarged view on the right, Arabic numerals 1 to 6 and alphabetical characters A to M represent a signal line arrangement table of the memory device, where Device is a signal of the actual memory device, and System is a burn-in system. The signal line to be supplied is shown.

Such a memory device is mounted in a socket formed in the DUT board 200, and the DUT board is mounted in the main board 100.

However, in the process of manufacturing the burn-in board for the memory test, the burn-in board is normally tested by testing whether the burn-in board is normally operated so that the test of the memory device can be performed normally. Accordingly, a means for testing the burn-in board is required in the manufacture of the burn-in board. That is, the process of testing whether the burn-in board operates normally during the manufacture of the burn-in board should be performed while the memory device is mounted on the DUT board, but the memory device cannot be mounted on the DUT board. Jig is used. That is, the device jig is used to test whether the signal line is short or whether the signal line supplied to the DUT board is open.

Generally, the memory device has a signal called NC (unused signal line), as shown in FIG. 5 in the drawing, which is not a signal line supplied from the system, but a signal line existing only on the socket of the memory device and the DUT board. As shown in FIG. 6, the signal line open test is performed using the device jig 300 in which the contact points of the signal line and the NC line are bundled into one mass.

In general, when the NC line is short, an environment in which the device may generate a defect may be created, but the DUT board is inspected by using the device jig 300 having the contacts grouped in one mass as described above. In this case, there is a problem that can not detect the failure of the device caused by the short-circuit NC line to detect this.

That is, existing device jig cannot short circuit test of NC contact at socket of memory device and DUT board. If NC contact of memory device generates signal and short circuit, device test affects the yield. Ignoring until now, there was a problem that the memory defects due to the short circuit of the NC contact were increased.

Republic of Korea Patent Publication No. 10-1999-0055280. Republic of Korea Patent Publication No. 10-2005-0047928. Korean Utility Model Registration No. 20-0385625.

The present invention was developed to solve the above problems of the prior art, and provides a burn-in board test jig that can test even a short circuit of a signal line (NC line) present in a memory device but not in use. For the purpose of

In more detail, the present invention is used to open test by only connecting the NC line, which is a signal line which exists only on the socket of the DUT board mounted on the burn-in board and the memory device, and the signal is not supplied from the actual system, in one mass. It is an object of the present invention to provide a jig for one-time board test to check the short circuit between the signal line and the NC line.

The burn-in board test jig according to the present invention for achieving the above object is a device jig used to test the burn-in board for testing the memory device, comprising a plurality of contacts corresponding to the contact of the memory device, By separating only the contact corresponding to the NC contact into a signal contact, and by testing only the NC contact as one, it is characterized in that it is possible to determine whether a short circuit between the signal contact and the NC contact.

The NC contacts may be divided into at least two or more groups so that they can be checked for each group.

Burn-in board test jig according to the present invention constitutes a test device jig to recognize only one NC contact by at least one signal line to recognize as a signal, and connected to an extension signal line of the BBT tester does not use the NC signal When the signal line and the NC signal line are short-circuited, the resistance value can be measured by the BBT tester, so that even the NC contact can be inspected, thereby reducing the defect rate of the burn-in board for memory test. It can be effective.

1 is a configuration diagram showing an example of a burn-in board test jig according to the present invention.
Figure 2 is a configuration diagram showing another example of the burn-in board test jig according to the present invention.
Figure 3 is a circuit diagram showing the principle of detecting the short circuit of the NC contact using a burn-in board test jig according to the present invention.
Figure 4 is a plan view showing a burn-in board in a conventional burn-in test apparatus.
5 is a contact structure diagram of a conventional memory device.
6 is a configuration diagram of a test jig in a conventional burn-in test apparatus.

Hereinafter, a burn-in board test jig according to the present invention will be described in detail with reference to the accompanying drawings.

The present invention is intended to test whether a short of a signal line (NC line) that is present in a memory device but is not used, and only the corresponding one of the contacts of the burn-in board test jig corresponds to the NC contact of the memory. It is possible to check whether the NC contact is short-circuited by separating and tying it together and connecting it to the spare signal line of BBT.

That is, the conventional burn-in board test jig could not check the NC contact, but the present invention connects only the NC contact among at least one group of the contacts formed in the test jig to the extension signal line for extension of the burn-in board. The short-circuit between the signal contact and the NC contact can be checked.

The NC contacts were separated into at least two groups, and signal lines were connected to each group so as to be connected to an extension signal line of the burn-in board.

When explaining the conventional burn-in board test jig in order to help the understanding of the present invention, in general, it is necessary to check whether the burn-in board is normal in the manufacturing process of the burn-in board, but the test is performed by mounting the actual memory device on the burn-in board. Can not. Accordingly, a test jig for burn-in board testing is used.

The main board inspection method using the test jig determines whether the short circuit between the signal lines is short and whether the signal lines supplied to each DUT board are open based on the resistance value. It is detected by the BBT tester.

However, the conventional test jig has a check corresponding to each contact point of the memory device as described above, but since they are grouped together, only an open test of the signal line can be performed, and thus, between the device and the DUT board socket. It is not possible to check whether the NC contact (NC signal line) that exists only in the circuit is shorted. However, even when the NC contact is short-circuit, the memory device may be defective, so it should be able to be inspected. However, the conventional test jig could not test the NC contact short-circuit on the burn-in board.

Accordingly, the present invention is to separate the signal contact and the NC contact in the test jig, and to monitor the short circuit between the NC contact in the open test (Open test).

In the test jig of the present invention, as shown in Figs. 1 and 2, the NC contact of the bottom (solder surface) surface is separated from the signal contact, the NC contact is connected to one, and the signal line of the spare signal line of the BBT tester. By making the connection, it is possible to check the short circuit between the other signal line and the NC contact.

In order to connect the BBT tester to the NC contact signal line, the NC contact signal line should be connected to the extension margin signal line on the burn-in board.

The NC contact may be pressed into at least two groups, as shown in FIG. 2 in the drawing. That is, in FIG. 2, when the "A-area" NC contact is bundled and bundled with any signal line existing in the B-area, the signal line of the "A-area" NC contact is not shorted with the A-area signal line. If the signal line of the contact is bundled and bundled with any signal line existing in the area A, it can be confirmed that the "B area" NC contact signal line is not short-circuited with the B area signal line. In other words, if the NC contact of the set area is connected with the signal line of the unrelated area, the short circuit of the NC contact can be checked.

In order to detect the short-circuit of the NC contact as described above, it can be made by adding only a function for detecting the short-circuit of the NC contact as described above in the program of the existing BBT tester, and a detailed description thereof will be omitted.

In addition, Figure 3 is a circuit diagram showing the principle of detecting the short circuit of the NC contact by using the burn-in board test jig, as shown, each signal line present in the burn-in board through the points A and B, respectively This signal line is connected to the DUT board via an isolation resistor 3 present at each DUT board, which is connected to the memory device.

However, in the manufacture of a normal burn-in board, instead of mounting a memory device, a test jig that replaces the role of the memory device is mounted to measure the combined value of the signal line resistance group (C) and the insulation resistance to short and open the circuit. The open resistance value is measured by the BBT tester.

In the short test, each signal line is open, but a certain value is measured because the BBT tester connects a random value to GND, and if there is a short circuit in the DUT board, it is between the shorted signal lines. Becomes a structure in which parallel values are connected based on GND, and existing values are represented as parallel values. In other words, if two are Short, a value of 1/2 appears.

On the other hand, the open test (open test) is made by measuring the value of the combined signal line resistance group (C) and the insulation resistance by taking the entire signal of the DUT board to GND by the test jig manufactured and mounted, This test process is similar to the conventional burn-in board test process, and a detailed description thereof will be omitted.

In the test process of the burn-in board made by such a process, the present invention detects a signal of a signal line bounded only by NC contacts, and connects it to an extension signal line not used by a BBT tester to recognize the NC contact signal as one signal line. When the signal line and the NC contact signal line are shorted in this way, their parallel composite resistance value is measured by the BBT tester to test whether the signal line and the NC contact signal line are shorted.

100: mainboard
200: DUT board

Claims (3)

In the device jig for testing the burn-in board,
A plurality of contacts corresponding to the contacts of the memory device are provided, but only the contacts corresponding to the NC contacts of the memory device are separated into signal contacts, and the NC contacts are bundled into one to test whether the short circuit between the signal contacts and the NC contacts can be checked. ,
The NC contacts are divided into at least two groups, and each group has a signal line connected to each group for checking the burn-in board test jig.
delete The method of claim 1,
Burn-in board test jig, characterized in that the signal line connected to the NC contacts are connected to the spare signal line for the extension of the burn-in board.

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