KR101319589B1 - Method for distinguishing write data of solid state drive and controller thereof - Google Patents

Abstract

According to an embodiment of the present invention, a write data classification method of an SSD may include a file in the write data classification method of a solid state drive (SSD) including a plurality of single-level cells (SLC) and a plurality of multi-level cells (MLC). Receiving a first write command from the system; Verifying a first logical address of the received first write command; And classifying data of the first write command into write data of any one of the single level cell and the multi-level cell based on the identified first logical address, and further, the one write data. The step of classifying into a step may include determining whether there is a predetermined regularity between the first logical address and a second logical address of a second write command received from the file system prior to the first write command; And dividing the data of the first write command into the write data of the multi-level cell when the regularity exists between the first logical address and the second logical address. The overall performance of the applied device can be improved.

Description

Method for distinguishing write data of solid state drive and controller about

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid state drive (SSD), and more particularly, to a single level cell (SLC) for writing data of a write command transferred from a file system to a hybrid SSD. -Classification of write data of SSD that can improve performance of hybrid SSD by classifying according to characteristics of Cell, hereinafter referred to as "SLC") and multi-level cell (MLC: Multi-Level-Cell, hereinafter referred to as "MLC"). It relates to a method and a controller thereof.

Recently, a new hybrid SSD has been developed that combines SLC and MLC flash memory. SLC chips are fast but expensive, and MLC chips are low cost but relatively low.

Hybrid SSDs are a new storage medium that uses both SLC and MLC chips to compensate for the shortcomings of both chips. Since the storage medium is composed of two types of chips, an efficient algorithm for classifying information and storing the information in an SLC chip and an MLC chip is required. In addition, since the read / write unit of the hybrid SSD is 4 to 16 times larger than the read / write unit of the file system, the write operation must be performed on the hybrid SSD by reconfiguring data transmitted from the file system into a register.

Hybrid SSDs include multiple planes of SLCs and multiple planes of MLCs. In this case, one register may be disposed in each plane. The size of the register may be determined depending on whether the plane is an SLC plane or an MLC plane. The register size of the SLC plane and the register size of the MLC plane may be different, but the SLC planes have registers of the same size, and the MLC planes have registers of the same size.

When information is transmitted with a write command in a file system, the hybrid SSD determines whether the information is attribute information (or random information) or user information (sequential information) according to the size of the information. Attribute information is stored in the SLC register and user information is stored in the MLC register. Since the performance of the SLC chip is higher than that of the MLC chip, it is suitable for storing attribute information that frequently updates information. Since the MLC chip is a low-cost chip, it is suitable for storing a large amount of user information.

Hybrid SSDs with such systems require algorithms that can clearly determine attribute information and user information.

In the method of determining the attribute information and the user information according to the conventional technique, it is determined whether the attribute information or the user information is simply stored according to the size of the information and stored in each register.

However, such a prior art may cause inaccurate classification of information, which may cause attribute data to be stored in the MLC chip, thereby lowering the overall performance of the hybrid SSD. In addition, this problem may have a greater impact on the overall performance of the hybrid SSD as the capacity of the hybrid SSD increases.

Accordingly, there is a need for a method of accurately classifying attribute information and user information to improve the performance of a hybrid SSD.

Korean Registered Patent Publication No. 0875539 (Registered 2008.12.16)

Chang, L.P. et al., "A Hybrid Approach to NAND-Flash-Based Solid-State Disks", IEEE Computer Society, pp. 1337-1349 (public date 2010. 08).

The present invention was derived to solve the above problems of the prior art, and provides a write data classification method of a SSD and a controller thereof, which can improve performance of a hybrid SSD by accurately classifying attribute information and user information of a file system. For the purpose of

In order to achieve the above object, a write data classification method of an SSD according to an embodiment of the present invention is a solid state drive (SSD) including a plurality of single-level cells (SLC) and a plurality of multi-level cells (MLC) CLAIMS What is claimed is: 1. A method of classifying write data, the method comprising: receiving a first write command from a file system; Verifying a first logical address of the received first write command; And classifying data of the first write command into write data of any one of the single level cell and the multi-level cell based on the identified first logical address.

The classifying into any one write data may include determining whether there is a predetermined regularity between the first logical address and a second logical address of a second write command received from the file system prior to the first write command; And dividing data of the first write command into write data of the multi-level cell when the regularity exists between the first logical address and the second logical address.

The classifying into any one write data may include determining whether there is a predetermined regularity between the first logical address and a third logical address stored in a first register for the multi-level cell; And when the regularity exists between the first logical address and the third logical address, dividing the data of the first write command into the write data of the multi-level cell, and further, the first logical address. And dividing the data of the first write command into write data of the single level cell when there is no regularity between and the third logical address.

The classifying into any one write data may include receiving a fourth write command from the file system; Confirming a fourth logical address of the received fourth write command; Determining whether there is a predetermined regularity between the first logical address and the fourth logical address; And dividing the data of the first write command and the data of the fourth write command into write data of the multi-level cell when the regularity exists between the first logical address and the fourth logical address. The method may further include classifying data of the first write command into write data of the single level cell when there is no regularity between the first logical address and the fourth logical address.

The classifying into any one write data may include determining whether a first logical address and a fifth logical address of a fifth write command received from the file system prior to the first write command are the same; And when the first logical address and the fifth logical address are the same, determine the data of the first write command as update data for the data of the fifth write command, and determine the data of the first write command in the single level cell. And classifying into write data.

The SSD controller according to an embodiment of the present invention is a controller of a solid state drive (SSD) including a plurality of single-level cells (SLC) and a plurality of multi-level cells (MLC), the first write command from the file system Receiving unit for receiving; A confirmation unit to confirm a first logical address of the received first write command; And a classification unit classifying data of the first write command into write data of any one of the single level cell and the multi-level cell based on the identified first logical address.

According to the present invention, the overall performance of the hybrid SSD can be improved by clearly classifying the attribute information and the user information of the file system and storing information corresponding to each characteristic in the SLC and the MLC constituting the hybrid SSD.

In detail, when the logical address of the write command received from the file system has a certain regularity, the data of the corresponding write command is determined as user information. When the write command having the same logical address is received, the data of the corresponding write command is frequently checked. By judging from the attribute information to be updated, the attribute information and the user information can be clearly distinguished.

In addition, the present invention is applicable to all devices that can use the hybrid SSD, for example, mobile phones, tablet PCs, notebooks, MP3 players, PDAs, portable computers (portable computer), the possibility of application as the capacity of the hybrid SSD increases This can be high.

The present invention can improve the performance of a device using a hybrid SSD by improving the overall performance of the hybrid SSD.

Figure 1 shows an embodiment configuration for a device having an SSD controller of the present invention.
2 illustrates a configuration of an SSD controller according to an embodiment of the present invention.
3 illustrates an example of a first buffer, a first register, and a second register storage state for explaining an operation of the SSD controller according to the present invention.
4 illustrates a first buffer, a first register, and a second register storage state of another example for explaining the operation of the SSD controller according to the present invention.
5 illustrates a first buffer, a first register, and a second register storage state of another example for explaining the operation of the SSD controller according to the present invention.
6 illustrates a first buffer, a first register, and a second register storing state for explaining an operation of the SSD controller according to the present invention.
7 illustrates a first buffer, a first register, and a second register storage state of another example for explaining the operation of the SSD controller according to the present invention.
8 is a flowchart illustrating an operation of classifying write data of an SSD according to an embodiment of the present invention.
FIG. 9 shows a further operational flowchart after step S830 shown in FIG. 8.

Other objects and features of the present invention will become apparent from the following description of embodiments with reference to the accompanying drawings.

Preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

However, the present invention is not limited to or limited by the embodiments. Like reference symbols in the drawings denote like elements.

Hereinafter, a write data classification method of a solid state drive and a controller thereof according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 to 9.

Figure 1 shows an embodiment configuration for a device having an SSD controller of the present invention.

Referring to FIG. 1, a device includes a controller 110, a first buffer 130, and a hybrid SSD 150.

The controller 110 is an SSD controller according to the present invention. The controller 110 receives a write command from a file system, checks a logical address included in the received write command, and writes data of the write command based on the determined logical address. It is determined whether the data is attribute information of the file system or the write data of MLC, that is, user information.

Here, the controller 110 may perform regularity between the logical address of the received write command and the logical address of data previously received from the file system and stored in the first buffer 130, the first register 155, and the second register 157. Alternatively, by determining whether the data is the same, it is possible to discriminate whether the data of the write command currently received is write data of the SLC or write data of the MLC.

In addition, when all data is stored in the storage space of the first register 155, the controller 110 writes the data stored in the first register 155 to the MLC 151, and the storage space of the second register 157. If all the data is stored in the second register 157 to write the data stored in the SLC (153). Of course, the controller 110 may write data to the MLC 151 or the SLC 153 at the time when all the data is stored in the storage space of the first register 155 or the second register 157, but a certain number of times. After receiving a write command and determining whether or not the regularity or the like, and may write data to the MLC (151) or SLC (153).

The first buffer 130 is a means for storing data and logical addresses which are not classified as write data of the SLC and write data of the MLC among data of a write command currently received from the file system.

That is, the first buffer 130 stores data and a logical address of a write command first received from the file system, or stores data and logical addresses that cannot be distinguished from attribute information or user information of the file system.

In this case, the first buffer 130 may be RAM or SRAM, and the first buffer 130 may be formed between the controller 110 and the hybrid SSD 150, but may also be formed inside the controller 130. have.

The size of the first buffer 130 may be determined in consideration of the performance of the hybrid SSD 150 and the device, and may have a size corresponding to two sectors of the file system.

When the first buffer 130 is included in the controller 110, the logical address and data stored in the first buffer 130 are controlled from the first buffer 130 by the control of the controller 110. ) Or the second register 157. Alternatively, when the first buffer 130 is located between the controller 110 and the hybrid SSD 150, the logical address and data stored in the first buffer 130 may be separated from the first buffer 130 by a separate controller. It may be stored in the first register 155 or the second register 157.

The hybrid SSD 150 includes a first register 155, a second register 157, a plurality of SLCs 153, and a plurality of MLCs 151, and stores data stored in the first register 155 as a corresponding logical address. The data stored in the second register 157 is stored in the corresponding space of the MLC 151 having the corresponding logical address.

The first register 155 is a means for storing data and a logical address of a write command classified as write data of the MLC, and is a register for the MLC in which data classified as user information is stored by the controller 110.

In this case, the first register 155 may be a RAM that temporarily stores data for writing (program) to the MLC 151. The size of the first register 155 may be determined in consideration of the performance of the hybrid SSD 150 and the device, and may have, for example, a size corresponding to one page of the MLC.

The second register 157 stores data and logical addresses of write commands classified as write data of the SLC, and is a register for the SLC in which data classified as attribute information of the file system is stored by the controller 110. .

In this case, the second register 157 may be a RAM that temporarily stores data for writing to the SLC 153. The size of the second register 157 may be determined in consideration of the performance of the hybrid SSD 150 and the device, and may have a size corresponding to one page of the SLC.

A detailed configuration of the SSD controller according to the present invention will be described with reference to FIG. 2.

2 illustrates a configuration of an SSD controller according to an embodiment of the present invention, which corresponds to the controller illustrated in FIG. 1.

Referring to FIG. 2, the controller 110 includes a receiver 210, a checker 230, a determiner 250, and a separator 270.

The receiver 210 receives a write command from the file system.

Here, the write command received from the file system includes a write command, a logical address of the data, and data to be stored in the hybrid SSD.

The receiver 210 may receive a write command and store it in a temporary storage space, or may store data and a logical address of the write command in the first buffer 130. That is, the first buffer 130 may also be used as a temporary storage space for separating write data of MLC and SLC.

The confirming unit 230 confirms the logical address of the write command received and received by the receiving unit 210 temporarily.

That is, the verification unit 230 confirms a logical address as a reference for dividing the data of the write command currently received into the write data of the MLC and the SLC.

The determination unit 250 may include a logical address of the write command received by the receiving unit 210, the first buffer 130, the first register 155, and the second register based on the logical address confirmed by the confirming unit 230. It is determined whether there is a predetermined regularity among at least one logical address previously stored in 157.

Here, the regularity is the same as whether the logical addresses are sequential or the interval between the logical addresses has a predetermined rule, for example, a predetermined period, and is a criterion for determining whether the data of the received write command is user information. will be. That is, the regularity is for determining whether the data of the received write command is user information.

The determination unit 250 may determine the regularity between the logical addresses of the received write command and the logical addresses stored in the first register 155 as the write data of the MLC. Regularity may be determined between at least one logical address that is not classified as write data stored in the first buffer 130.

In this case, only the data and the logical address of the write command received by the receiver 210 are stored in the first buffer 130 and there is no regularity with the logical addresses stored in the first register 155. The next write command is received through the receiving unit 210.

Further, the determination unit 250 is a logical address of the received write command and the logical address of the data previously received from the file system and stored in the first buffer 130, the first register 155, and the second register 157. Determine if the same logical address exists.

This is to determine whether the data of the received write command is update data.

The classification unit 270 may include a logical address of the write command received as a result of the determination by the determination unit 250 and at least one or more logics previously stored in the first buffer 130, the first register 155, and the second register 157. When there is regularity between the addresses, the data of the received write command is classified into the write data of the MLC, and the logical address and data of the received write command are stored in the first register 155.

The classification unit 270 is previously received from the file system and the logical address of the write command received as a result of the determination by the determination unit 250, and thus the first buffer 130, the first register 155, and the second register 157 are used. If the same logical address exists among the logical addresses of the data stored in the data, the data of the received write command is judged as update data, the data of the received write command is classified as the write data of the SLC, and the write received in the second register 157. Stores the logical address and data of the command.

The classification unit 270 rules between the logical address of the received write command and the logical addresses stored in the first buffer 130, the first register 155, and the second register 157 as a result of the determination by the determination unit 250. If a plurality of data, for example, two or more data are stored in the first buffer 130 without the same or the same logical address does not exist, the first received data among the data stored in the first buffer 130 is SLC. The data is classified into write data of the data and stored in the second register 157. Of course, the first received data among the data stored in the first buffer 130 is deleted after being stored in the second register 157.

An operation of the controller 110 having such a configuration will be described with reference to FIGS. 3 to 7.

When the four write commands ① to ④ are sequentially received as shown in the example shown in FIG. 3, the controller 110 checks the logical addresses of the write commands ① to ④, that is, 0, 1, 2, 9, and 0, 1, The data A, B, and C having sequential logical addresses of 2 are judged as user information, and the logical addresses and data (0, A), (1, B), and (2, C) of the write commands ① to ③ are MLC. And a logical address and data (9, D) of the write command (4), which are not classified as write data of MLC or SLC, in the first buffer 130.

Here, in the write command (w x y), w means a write command, x means a logical address, and y means data.

As shown in the example shown in FIG. 4, the controller 110 has a write command ⑤ in the state where the logical address and data are stored in the first buffer 130, the first register 155, and the second register 157 as shown in FIG. 3. When received, check logical address 3 of write command ⑤, check that logical address 3 is sequential with the logical addresses stored in the first register, classify data of write command ⑤ into write data of MLC, and then logical address of write command ⑤. And data (3, E) are stored in the first register.

5 illustrates an example of a case where update data is received, and the controller 110 is shown in FIG. 5 in a state where logical addresses and data are stored in a first buffer, a first register, and a second register as shown in FIG. 4. As shown in the example, when the write command ⑥ is received, the logical address 9 of the write command ⑥ is checked. Since the same as the logical address 9 of the data D stored in the first buffer, the data F is regarded as the update data of the data D. Store the logical address and data (9, F) in the second register. That is, the controller 110 classifies data that frequently occurs in update as attribute information of the file system and stores the update data in a second register for SLC.

Of course, in the case of FIG. 5, since the data of the logical address 9 is classified as the write data of the SLC, the data of the logical address 9 stored in the first buffer is deleted.

When the controller 110 receives the write commands ⑦ and ⑧ sequentially, as shown in the example shown in FIG. 6 in the state as shown in FIG. 5, the controller 110 performs regularity between the logical addresses 24 and 16 of the write commands ⑦ and ⑧ and the first and second registers. Determine regularity or equality among logical addresses stored in. As shown in FIG. 6, since no regularity or identity exists between the logical addresses, the controller 110 stores the logical addresses of the write commands ⑦ and ⑧ and the data (24, G) and (16, H) in the first buffer. Store in

In addition, when the write command ⑨ is received as shown in the example shown in FIG. 7, the controller 110 stores the logical address 17 of the write command ⑨ and the logic stored first in the first buffer because there is no empty storage space in the first buffer. Determine regularity or equality between addresses 24 The controller distinguishes the logical address 24 and the data G as write data of the SLC and stores them in the second register because they are not regular or identical between the logical address 17 and the logical address 24 of the write command ⑨.

In addition, since the two logical addresses stored in the first buffer have sequential regularity, the controller 110 may classify them as write data of the MLC. Therefore, two logical addresses and data (16, H) and (17, I) must be stored in the first register. Since there is no storage space in the first register, the data stored in the first register is stored in the MLC. After that, it is preferable to store (16, H) and (17, I) in the first register. Of course, when the controller determines the regularity between three or more logical addresses, the logical address and data stored in the first buffer of FIG. 7 are not stored in the first register but are stored in the first buffer as they are.

4 to 7 illustrate that all data is stored in the first register, but when a certain number of write commands are received after a point where all data is stored in the first register or after a point where all data is stored in the first register. Allows the data stored in the first register to be written to the MLC.

As described above, the SSD controller according to the present invention is based on the logical address of the received write command and the logical address of the data previously stored in the first buffer, the first register, and the second register. Data stored in the buffer can be classified as write data of MLC or write data of SLC. In other words, the present invention can improve the write performance of an SSD by accurately classifying the attribute information and user information of the file system using a logical address before storing the MLC or SLC, and further improve the overall performance of the device using the SSD. You can also

8 is a flowchart illustrating an operation of classifying write data of an SSD according to an embodiment of the present invention. FIG. 8 is an operation of the controller shown in FIG. 1 and shows an operation flowchart for regularity.

Referring to FIG. 8, the controller receives a write command transmitted from a file system and checks logical addresses included in the received write command (S810 and S820).

In this case, the write command may include a write command, a logical address of data and data, and the received write command may be stored in the first buffer, the first register, and the second register shown in FIG. 110 may be stored in a separate storage means provided therein, or may be stored in a separate storage means located between the file system and the controller.

If the logical address of the currently received write command is confirmed, it is determined whether a logical address of a previously written write command received from the file system prior to the currently received write command exists (S830).

Here, the logical address of the previous write command means at least one logical address stored in the first buffer, the first register, and the second register of FIG. 1.

As a result of the determination in step S830, if at least one logical address, that is, the logical address of the previous write command does not exist in the first buffer, the first register, and the second register, whether the data of the currently received write command is the write data of the MLC, the write of the SLC. Since the data cannot be distinguished from each other, the logical address and data of the currently received write command are stored in the first buffer (S840).

After performing step S840, the process of receiving a next write command from the file system is performed again.

Therefore, when the logical address and the data of the write command are stored in the first buffer by the step S840, the logical address becomes the logical address of the previous write command.

On the contrary, when the determination result of step S830 indicates that at least one logical address exists in the first buffer, the first register, and the second register, the previous address previously stored in the logical address of the currently received write command and the first buffer, the first register, and the second register It is determined whether regularity exists between logical addresses of the write command (S850 and S860).

Here, the regularity may include all rules of logical addresses for user information transmitted from the file system to the hybrid SSD, such as when the logical addresses are sequential or the logical addresses are at regular intervals.

As a result of the determination in step S860, if regularity exists between the logical address of the currently received write command and the logical address of the previous write command, the data of the received write command is classified as the write data of the MLC to determine the logical address and data of the received write command. It is stored in the first register for MLC (S890).

The regularity determination in steps S850 and S860 may be regularity between the logical address of the currently received write command and the logical address stored in the first register shown in FIG. 1, or the logical address of the currently received write command and FIG. 1. There may also be regularity between logical addresses stored in the first buffer shown in FIG.

On the other hand, if it is determined in step S860 that there is no regularity between the logical address of the currently received write command and the logical address of the previous write command, it is determined whether the space for storing the logical address of the currently received write command and data exists in the first buffer. (S870).

As a result of the determination in step S870, if the logical address and data of the currently received write command exist in the first buffer, the logical address and data are stored in the first buffer and the process is performed again from step S810.

On the other hand, if the logical address of the currently received write command and the space to store the data are not present in the first buffer, that is, when the storage space of the first buffer is filled with other data, the stored result is stored in the first buffer. The first stored data, for example, data G of logical address 24 in FIG. 6 is classified as write data of the SLC and stored in a second register for SLC (S880).

FIG. 9 shows a further operational flowchart after step S830 shown in FIG. 8. 9 is a flowchart illustrating the operation of whether the data is the same to determine update data.

Referring to FIG. 9, if the logical address of the previous write command exists in the first buffer, the first register, and the second register, the logical address of the currently received write command and the logical address of the previous write command, It is determined whether the logical addresses previously stored in the first buffer, the first register, and the second register are the same (S910, S920). That is, it is determined whether the data to be updated with the data of the write command currently received exists in the first buffer, the first register, and the second register through whether the logical addresses are the same. Here, the controller can determine whether data to be updated exists in the first buffer or the second register.

As a result of the determination in step S920, if the logical address of the previous write command that is the same as the logical address of the currently received write command exists, the data of the received write command is determined as update data and classified as write data of the SLC (S950). Of course, the logical address and data of the write command classified as SLC write data are stored in a second register for SLC.

On the other hand, if it is determined in step S920 that the logic of the previous write command that is the same as the logical address of the currently received write command does not exist, it is determined whether there is a space for storing the logical address and data of the currently received write command in the first buffer (S930). ).

As a result of the determination in step S930, when the logical address and data of the currently received write command exist in the first buffer, the corresponding logical address and data are stored in the first buffer and the process is performed again from step S810.

On the other hand, if the logical address of the currently received write command and the space in which the data is to be stored are not present in the first buffer, in step S930, the first stored data among the data stored in the first buffer is classified as the write data of the SLC, and the It is stored in the second register (S880).

The write data classification method of the solid state drive according to an exemplary embodiment of the present invention may be implemented in the form of program instructions that may be executed by various computer means, and may be recorded in a computer readable medium. The computer readable medium may include program instructions, data files, data structures, etc. alone or in combination. The program instructions recorded on the medium may be those specially designed and constructed for the present invention or may be available to those skilled in the art of computer software. Examples of computer-readable media include magnetic media such as hard disks, floppy disks and magnetic tape; optical media such as CD-ROMs and DVDs; magnetic media such as floppy disks; Magneto-optical media, and hardware devices specifically configured to store and execute program instructions such as ROM, RAM, flash memory, and the like. Examples of program instructions include machine language code such as those produced by a compiler, as well as high-level language code that can be executed by a computer using an interpreter or the like. The hardware devices described above may be configured to operate as one or more software modules to perform the operations of the present invention, and vice versa.

As described above, the present invention has been described by specific embodiments such as specific components and the like, but the embodiments and the drawings are provided only to help a more general understanding of the present invention, and the present invention is not limited to the above embodiments. For those skilled in the art, various modifications and variations are possible from these descriptions.

Accordingly, the spirit of the present invention should not be construed as being limited to the embodiments described, and all of the equivalents or equivalents of the claims, as well as the following claims, belong to the scope of the present invention .

Claims (12)

In the write data classification method of a solid state drive (SSD) including a plurality of single-level cells (SLC) and a plurality of multi-level cells (MLC),
Receiving a first write command from the file system;
Verifying a first logical address of the received first write command; And
Classifying the data of the first write command into one of the single-level cell and the multi-level cell based on the identified first logical address;
Lt; / RTI >
The step of fractionating
A logical address previously stored in a first buffer for discriminating the identified first logical address and the write data of the multi-level cell and the single-level cell, a logical address previously stored in a first register for the multi-level cell, When there is no predetermined regularity or the same logical address does not exist between the logical addresses stored in the second register for the single level cell, the first received data among the plurality of data stored in the first buffer is written to the single level cell. To classify write data on a solid state drive. The method of claim 1,
The step of classifying into any one of the write data is
Determining whether there is regularity between the first logical address and a second logical address of a second write command received from the file system prior to the first write command; And
Classifying data of the first write command into write data of the multi-level cell when the regularity exists between the first logical address and the second logical address.
Write data classification method of a solid state drive comprising a. The method of claim 1,
The step of classifying into any one of the write data is
Determining whether the regularity exists between the first logical address and a third logical address stored separately in the first register; And
Partitioning data of the first write command into write data of the multi-level cell when the regularity exists between the first logical address and the third logical address.
Write data fractionation method of a solid state drive comprising a. The method of claim 3,
The step of classifying into any one of the write data is
Storing data of the first write command in the first buffer when there is no regularity between the first logical address and the third logical address
Write data classification method of the solid state drive, characterized in that it further comprises. The method of claim 1,
The step of classifying into any one of the write data is
Receiving a fourth write command from the file system;
Confirming a fourth logical address of the received fourth write command;
Determining whether the regularity exists between the first logical address and the fourth logical address; And
Classifying data of the first write command and data of the fourth write command into write data of the multi-level cell when the regularity exists between the first logical address and the fourth logical address.
Write data fractionation method of a solid state drive comprising a. The method of claim 5,
The step of classifying into any one of the write data is
Classifying data of the first write command into write data of the single level cell when there is no regularity between the first logical address and the fourth logical address.
Write data classification method of the solid state drive, characterized in that it further comprises. The method of claim 1,
The step of classifying into any one of the write data is
Determining whether a first logical address and a fifth logical address of a fifth write command received from the file system prior to the first write command are the same; And
When the first logical address is the same as the fifth logical address, the data of the first write command is determined to be updated data with respect to the data of the fifth write command, and the data of the first write command is written to the single level cell. Segmentation by Data
Write data fractionation method of a solid state drive comprising a.
In a solid state drive (SSD) controller comprising a plurality of single level cells (SLC) and a plurality of multi-level cells (MLC),
A receiving unit to receive a first write command from the file system;
A confirmation unit to confirm a first logical address of the received first write command; And
A classification unit for classifying the data of the first write command into write data of any one of the single level cell and the multi-level cell based on the identified first logical address.
Lt; / RTI >
The fractionation unit
A logical address previously stored in a first buffer for discriminating the identified first logical address and the write data of the multi-level cell and the single-level cell, a logical address previously stored in a first register for the multi-level cell, When there is no predetermined regularity or the same logical address does not exist between the logical addresses stored in the second register for the single level cell, the first received data among the plurality of data stored in the first buffer is written to the single level cell. Solid state drive controller discerned by. 9. The method of claim 8,
Determination unit for determining whether the regularity between the first logical address and the third logical address stored in the first register for each period;
Further comprising:
The fractionation unit
When the regularity exists between the first logical address and the third logical address, data of the first write command is classified into write data of the multi-level cell, and between the first logical address and the third logical address. And if there is no regularity, storing the data of the first write command in the first buffer. 9. The method of claim 8,
Determination unit for determining the regularity between the logical addresses of the write commands received through the receiving unit
Further comprising:
The receiving unit
Receive a fourth write command from the file system,
The confirmation unit
Confirm a fourth logical address of the received fourth write command,
The determination unit
Determine whether the regularity exists between the first logical address and the fourth logical address;
The fractionation unit
When there is the regularity between the first logical address and the fourth logical address, the data of the first write command and the data of the fourth write command are classified into write data of the multi-level cell, and the first logical address And the data of the first write command are classified into write data of the single level cell when there is no regularity between the controller and the fourth logical address. 9. The method of claim 8,
Determination unit for determining whether the first logical address and the fifth logical address of the fifth write command received from the file system prior to the first write command is the same
Further comprising:
The fractionation unit
When the first logical address is the same as the fifth logical address, the data of the first write command is determined to be updated data with respect to the data of the fifth write command, and the data of the first write command is written to the single level cell. Solid state drive controller characterized in that it is classified by data.
A computer-readable recording medium in which a program for executing the method of any one of claims 1 to 7 is recorded.

Images