KR101308046B1 - Capacitor-less Dynamic semiconductor memory device and method of operating of the same - Google Patents

Abstract

The present invention discloses a capacitor-less dynamic semiconductor memory device. The device comprises memory cells each having a floating body transistor having gates connected to a word line, drains connected to each of the plurality of bit lines, and sources connected to each of the plurality of source lines, a gate connected to the word line and a first A first dummy cell having a floating body transistor having a drain connected to a dummy bit line and a source connected to a first dummy source line, and having a data “1” stored therein; a gate connected to a word line and a drain connected to a second dummy bit line; A second dummy cell having a floating body transistor having a source connected to the two dummy source lines and having a data “0”; an equalization transistor and bit line equalizing the first dummy bit line and the second dummy bit line in response to an equalization signal. In response to the selection signal, one of the plurality of bit lines is selected and connected to the sense bit line. A bit line selector, a dummy bit line connection unit configured to select one of the first and dummy bit lines to connect to the inversion sense bit line in response to each of the first and second dummy bit line selection signals; It consists of a sensing unit that senses and amplifies the voltage difference of the inversion sensing bit line.

Description

Capacitor-less dynamic semiconductor memory device and method of operating of the same

1 shows a write operation voltage of a typical NMOS floating body transistor.

2A and 2B illustrate a conventional capacitorless dynamic semiconductor memory device.

3 is a conceptual diagram illustrating the technical idea of the present invention.

4 is a detailed circuit diagram according to a preferred embodiment of the present invention.

The present invention relates to a dynamic semiconductor memory device, and more particularly, to a capacitorless dynamic semiconductor memory device having a capacitorless memory cell having a floating body transistor and a method of operating the same.

In the conventional general dynamic semiconductor memory device, one access transistor and one capacitor constitute one unit memory cell. However, in accordance with the demand for high integrity and high density of semiconductor memory devices, a unit memory cell structure having a capacitor has a problem in that required capacitance cannot be secured.

In order to overcome the above problems, recently, techniques using a floating body transistor as a dynamic memory cell have been introduced. In the paper titled “Capacitorless Dynamic Semiconductor Memory Device” introduced in 2002 by the IEEE, a technique for storing data “1” or “0” by accumulating a large number of carriers or emitting a large number of carriers in the body of a floating body transistor is disclosed. It is. (Takashi Ohsawa et al., [Memory Design Using a One-Transistor Gain Cell on SOI,] IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 11, NOV. 2002.)

1 shows the structure and write operating voltage of a typical NMOS floating body transistor. Referring to FIG. 1, the SOI substrate includes a silicon substrate Si and a buried oxide, and the floating body transistor FBT is connected to a bit line (not shown) on top of the SOI substrate. And a source S connected to a source line (not shown) and a gate G connected to a word line (not shown) and positioned together with an insulating layer on an upper portion of the region between the source S and the drain D and the source S. And a body B formed under the gate G and electrically floating.

First, in order to write data “1” to the floating body transistor, a voltage relationship in which a gate induced drain leakage (GIDL) phenomenon may occur in the gate G and the drain D, that is, the gate G, respectively. A positive voltage (1.5 V) is applied to the negative voltage (-1.5 V) and the drain (D) to accumulate holes in the body (B), and to the gate (G) and the drain (D), respectively. There is a method of accumulating holes in the body B by using an impact ionization phenomenon by applying a positive voltage (1.5V). That is, as holes are accumulated in the body B, the body voltage of the floating body transistor increases, which lowers the threshold voltage Vth1, and defines this state as storing the data “1”. In addition, the method using the GIDL phenomenon has a smaller write current than the method using the impact ionization phenomenon.

Next, in order to write data “0” to the floating body transistor FBT, a positive voltage (1.5 V) is applied to the gate G and the drain D so that a forward bias condition occurs between the body B and the drain D. And the negative voltage (-1.5V) is applied to discharge the hole of the body (B) to the drain (D) to lower the body voltage, which raises the threshold voltage (Vth0), this state is stored data "0" Define as one state. In addition, the method of writing data “0” may emit holes in the body by a coupling effect using voltages applied to the gate G and the source S. FIG.

2A and 2B each show a circuit diagram of a conventional capacitorless dynamic semiconductor memory device. The capacitorless dynamic semiconductor memory device of FIGS. 2A and 2B is disclosed in US Patent Publication No. 2003-231524. Referring to FIGS. 2A and 2B, in the conventional capacitorless dynamic semiconductor memory device, data “0” and “1” are respectively placed in regions where a dummy word line RWL is intersected with a bit line to generate a reference signal of a bit line sense amplifier. And a dummy cell for storing. The capacitorless dynamic semiconductor memory device of FIG. 2B includes dummy cells which store data “0” and “1” in regions intersecting word lines with dummy bit lines to generate a reference signal of a bit line sense amplifier. . That is, in a conventional capacitorless semiconductor memory device, a dummy word line or a dummy bit line is formed to make a reference voltage of a bit line sense amplifier, the current flowing through the dummy cells is divided by 1/2, and the current is copied again. By using a method of converting the voltage into a reference voltage, a more complicated circuit such as a reference voltage generator (Vref Gen.) is required and a layout area for them is required.

An object of the present invention is to provide a capacitorless dynamic semiconductor memory device of a floating body transistor having a dummy cell for generating a reference voltage of a bit line sense amplifier.

Another object of the present invention is to provide a method of operating a capacitorless dynamic semiconductor memory device for achieving the above object.

The technical problem of the present invention is not limited to the technical problem mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

According to another aspect of the present invention, a capacitorless dynamic semiconductor memory device may include gates connected to a word line, drains connected to each of a plurality of bit lines, and sources connected to each of a plurality of source lines. And a floating body transistor having memory cells each having a floating body transistor, a gate connected to the word line, a drain connected to a first dummy bit line, and a source connected to a first dummy source line, and storing data “1”. A second dummy cell having a floating body transistor having a dummy cell, a gate connected to the word line, a drain connected to a second dummy bit line, and a source connected to a second dummy source line, and storing data “0”; Responsive to the first dummy bit line and the second dummy bit line An equalization transistor, a bit line selector configured to select one of the plurality of bit lines in response to a bit line selection signal, and to connect to a sense bit line, respectively, in response to each of the first and second dummy bit line selection signals. And a dummy bit line connection unit configured to select one of the dummy bit lines to connect to the inversion sensing bit line, and a sensing unit for sensing and amplifying a voltage difference between the sensing bit line and the inversion sensing bit line. .

According to another aspect of the present invention, a capacitorless dynamic semiconductor memory device may include gates connected to a word line, drains connected to each of a plurality of bit lines, and sources connected to each of a plurality of source lines. And a floating body transistor having a first memory cell each having a floating body transistor, a gate connected to the word line, a drain connected to a first dummy bit line, and a source connected to a first dummy source line. And a floating body transistor having a first dummy cell stored therein, a floating body transistor having a gate connected to the word line, a drain connected to a second dummy bit line, and a source connected to a second dummy source line, and storing a data “0”. A memory block, the first detection bit being located at one side of the memory block A first sensing unit for sensing a voltage difference between a line and a first inversion sensing bit line, and a second sensing positioned at the other side of the memory block and sensing a voltage difference between a second sensing bit line and a second inversion sensing bit line A first bit line selector positioned between the memory block and the first sensing unit and configured to select one of first bit lines among a plurality of bit lines of the memory block in response to an activated first bit line selection signal; A second bit line selector positioned between the memory block and the second sensing unit and selecting one of second bit lines among the plurality of bit lines of the memory block in response to a second bit line selection signal; First and second dummy bit line selectors that select one of the first and second dummy bit lines of the memory block in response to each of the second dummy bit line selection signals, the first bit line selection; A first block connection switch positioned between the first sensing unit and the first sensing bit line, the first block connection switch connecting the selected first bit line of the memory block to the first sensing bit line in response to a block selection signal; And a first dummy bit line connection unit connecting the selected first dummy bit line of the block to the first inversion sensing bit line.

According to another aspect of the present invention, there is provided a method of operating a capacitorless dynamic semiconductor memory device having gates connected to a word line, drains connected to each of a plurality of bit lines, and sources connected to each of a plurality of source lines. Memory cells each having a floating body transistor, a floating body transistor having a gate connected to the word line, a drain connected to a first dummy bit line, and a source connected to a first dummy source line, and having a data “1” stored therein; A capacitor having a dummy cell, a floating body transistor having a gate connected to the word line, a drain connected to a second dummy bit line, and a source connected to a second dummy source line, and having a second dummy cell in which data “0” is stored. In a method of operating a leased dynamic semiconductor memory device, Applying a source voltage to the source of the first and second dummy cells and activating the word line to turn on the memory cells and the first and second dummy cells; a first dummy bit line and a second dummy bit Equalizing a voltage of a line, selecting at least one bit line of the plurality of bit lines and connecting the sense bit line, selecting one of the first and second dummy bit lines and inverting sense bits Connecting to a line, and sensing and amplifying a voltage difference between the sense bit line and the inverted sense bit line.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout.

As used herein, “and / or” includes each and all combinations of one or more of the items mentioned.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

3 is a conceptual diagram of a semiconductor memory device illustrating the technical spirit of the present invention.

Referring to FIG. 3, a semiconductor memory device may include a memory block 310, bit line selectors 321-1 and 321-2, dummy bit line connectors 331-1 and 331-2, and voltage sensing amplifiers. 340-1 and 340-2, and precharge circuits 350-1 and 350-2.

The memory block 310 includes the normal cells NCs of the floating body transistors positioned at the intersections of the word line WL and the plurality of bit lines BL1 to BLn, the word line, and the first dummy bit line DBL0. Dummy cell DC0 of the floating body transistor located at the intersection region of the circuit) and the data “0” stored therein, and the floating body transistor of the floating body transistor located at the intersection region of the word line and the second dummy bit line DBL1. The micelle DC1 and the equalization transistor EQT connect the first dummy bit line DBL0 and the second dummy bit line DBL1 in response to the equalization signal PAVGi.

The bit line selector 321-1 selects one of the odd bit lines in response to one bit line selection signal that is activated among the odd bit line selection signals BLS1 to BLS (n-1). It is connected to the sense bit line SBL2 which is the first input of the sense amplifier 340. In addition, the bit line selector 321-1 selects the odd-numbered source lines SL1 to SL (n−1) corresponding to each of the selected odd-numbered bit lines together and selects a source voltage SLP suitable for an operation condition. Applies to the selected source line. Similarly, the bit line selector 321-2 selects one of the even-numbered bit lines in response to one bit line selection signal that is activated among the even-numbered bit line selection signals BLS2 to BLSn and the voltage sensing amplifier. A detection bit line SBL1, which is a first input of 340-2, is connected. In addition, the bit line selector 321-2 selects even-numbered source lines SL2 to SLn corresponding to each of the selected even-numbered bit lines together and applies a source voltage SLP suitable to an operation condition to the selected source line. do. In addition, the bit line selectors 321-1 and 321-2 supply a predetermined precharge voltage to the corresponding bit line and the source line when the corresponding bit line selection signal is inactive. The source voltage SLP may be greater than the precharge voltage.

The dummy bit line connection unit 331-1 selects the second dummy bit line DBL1 in response to the dummy bit line selection signal DBLS1 and inverts a sensing bit which is a second input of the voltage sensing amplifier 340-1. Connect to line SBL2B. The dummy bit line connection unit 331-1 selects the dummy source line DSL1 corresponding to the dummy bit line DBL1 together and applies the source voltage SLP suitable for the operation condition to the dummy source line DSL1. The dummy bit line connection unit 331-2 selects the first dummy bit line DBL0 in response to the dummy bit line selection signal DBLS0 and inverts the sensing bit line as the second input of the voltage sensing amplifier 340-2. To (SBL1B). The dummy bit line connection unit 331-2 selects the dummy source line DSL1 corresponding to the dummy bit line DBL1 together and applies the source voltage SLP suitable for the operation condition to the dummy source line DSL1. In addition, the dummy bit line connection units 331-1 and 331-2 apply the precharge voltage to the dummy source line and the dummy bit lines when the dummy bit line selection signals DBLS1 and DBLS0 are inactivated.

The voltage sensing amplifier 340 receives the first input of the bit line selector and the second input of the dummy bit line connection unit to sense and amplify the voltage difference. The voltage sensing amplifier may be configured in a latch form consisting of NMOS transistors and PMOS transistors.

The precharge circuits 350-1 and 350-2 precharge the sense bit line SBL and the inversion sense bit line SBLB with a precharge voltage.

That is, the capacitorless dynamic memory device according to the present invention activates one word line and supplies a source voltage SLP suitable for an operating condition to a source of dummy cells DC0 and DC1 through a source line, thereby providing dummy cells DC0. The voltage obtained by equalizing the voltages of the dummy bit lines DBL0 and DBL1 formed by the threshold voltage of DC1 is used as the reference voltage. Therefore, the configuration for generating the reference voltage is simplified, thereby reducing the layout area.

4 is a detailed circuit diagram of a memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 4, a memory device includes memory blocks 411 and 412, sensing blocks 421 and 422, first and second bit line selectors 431 and 432, and first and second dummy bit lines. Connectors 441 and 442 and first and second block selection switches 451 and 452. Each of the sensing blocks 421 and 422 includes a sense amplifier SA and a precharge circuit PRE. For convenience of description, the bit line selector and the voltage sensing amplifier formed under the memory block 412 are not shown, but this is obvious to those skilled in the art.

Each of the memory blocks 411 and 412 is formed of the normal cells NC and the word line WLn of the floating body transistor positioned at the intersection of the word line WLn and the plurality of bit lines BL1 to BLn. The dummy cell DC1 of the floating body transistor in which the first dummy bit line DBL0 is located and the data “0” is stored, and the data “is located in the intersection area of the word line WLn and the second dummy bit line DBL1. An equalization transistor connecting the first dummy bit line DBL0 and the second dummy bit line DBL1 in response to the dummy cell DC1 of the floating body transistor having 1 ″ stored therein and the equalization signals PAVGi and PAVGj. EQT).

The voltage sensing amplifier SA of each of the sensing blocks 421 and 422 is positioned between the first and second memory blocks 412 and 412 and a NMOS sense amplifier and a PMOS including NMOS transistors N1 and N2. It is configured in a general latch form including a PMOS sense amplifier composed of transistors P1 and P2, and the precharge circuit PRE is composed of NMOS transistors N3, N4 and N5.

Each of the first and second bit line selectors 431 and 432 is positioned between the corresponding memory block and each of the sensing blocks 421 and 422, respectively, and responds to the corresponding bit line selection signals BLS1 to BLSn. NMOS transistors N6 and N7. In addition, each of the first and second bit line selectors 431 and 432 may correspond to one of bit lines of a corresponding memory block and a source line corresponding to the selected bit line in response to the bit line selection signals BLS1 to BLSn being activated. Are selected together and a source voltage SLP suitable for the operating condition is applied to the source line corresponding to the selected bit line. Each of the first and second bit line selectors 431 and 432 supplies a predetermined precharge voltage to the corresponding bit line and the source line when the corresponding bit line selection signal is inactive. In addition, the NMOS transistors N6 and N7 constituting the bit line selectors may be composed of one transistor.

Each of the first and second dummy bit line couplers 441 and 442 includes NMOS transistors N8 and N9, and the memory blocks 411, and in response to the dummy bit line select signals DBLS0 and DBLS1. One of the dummy bit lines DBL0 and DBL1 of 412 is selected.

The first and second block selection switches 451 and 452 have an NMOS transistor N10 and are located between the corresponding bit line selector and the sensing block and in response to the corresponding block selection signals PISOi and PIOSj. The selected bit line of each memory block is connected to a first input of the sensing block. Of course, only the block selection signal of the memory block in which the word line is activated among the block selection signals is activated and connected to the first input of the sensing block.

That is, the semiconductor memory device has a configuration in which a sensing block is shared by two memory blocks, wherein odd bit lines of the bit lines of the memory block are assigned to the bit line selector 431 and even bit lines of the bit line selector 432. In this structure, data of two normal cells connected to the activated word line can be output. First, an operation of writing data “0” and data “1” to the dummy cells DC0 and DC1 will be described. As follows.

The bit line selectors and the dummy bit line connectors apply the precharge voltage precharged by the precharge circuit PRE to all the bit lines and the dummy bit lines while the word lines in each memory block are inactive. Precharge all bit lines, dummy bit lines, all source lines, and all dummy source lines to a precharge voltage level by applying a source voltage SLP equal to the precharge voltage to the lines and dummy source lines. .

In response to the active command, a voltage (for example, 0V in FIG. 1) is applied to the selected word line WLn of the selected memory block among the memory blocks 411 and 412, and the dummy bit line selection signal DBLS0 is activated. In response, the dummy bit line connector 441 selects the dummy bit line DBL0 and applies the voltage (for example, 1.5V in FIG. 1) to the source voltage SLP and selects the dummy bit line DBL0. The source voltage is applied to the dummy source line DSL0 corresponding to the source voltage.

When data “1” is transmitted to the sense bit line SBL1 and data “0” is transmitted to the inverted sense bit line SBL1B, the voltage sensing amplifier SA senses in response to the sensing control signals LA and LAB. Data amplification of the bit line SBL1 and the inversion sensing bit line SBL1B is performed.

When the block selection signal PISOi is activated, a voltage (for example, 0V in FIG. 1) corresponding to the amplified “0” data of the inversion detection bit line SBL1B is transferred to the dummy bit line DBL0 to dummy. Data "0" is stored in the cell DC0.

In a similar manner, data "1" is stored in the dummy cell DC1.

Data “0” is stored in the dummy cell DC0, data “1” is stored in the dummy cell DC1, and the word line WLn, the bit line BL1, and the source line SL1 of the memory block 411 are stored. If data "0" is stored in the normal cell NC connected to), and data "1" is stored in the normal cell NC connected to the word line WLn, bit line BL2, and source line SL2, the data is stored. Explain how to read.

First, the bit line selectors and the dummy bit line connectors apply the precharge voltage precharged by the precharge circuit PRE to all the bit lines and the dummy bit lines while the word lines in each memory block are inactive. Applying a source voltage SLP equal to the precharge voltage to all the source lines and the dummy source lines, preload all bit lines, dummy bit lines, all source lines, and all dummy source lines to the precharge voltage level. Occupy.

In response to the active command, a voltage (for example, 1.5V in FIG. 1) is applied to the word line WLn, and the bit line selector 431 responds to the bit line selection signal BLS1 that is activated. BL1) is selected and a voltage (for example, 1.5V of FIG. 1) is applied to the source voltage SLP to apply the source voltage to the source line SL1 corresponding to the selected bit line. At this time, the bit line selector 432 also selects the bit line BL2 and applies a voltage (for example, 1.5V of FIG. 1) to the corresponding source line SL2. Similarly, the dummy bit line connector 441 selects one of the dummy bit lines DBL0 in response to the activated dummy bit line selection signal DBLS0 and selects the voltage (for example, the corresponding dummy source line DSL0). 1, 1.5V) is applied. In this case, the dummy bit line connector 442 also selects the dummy bit line DBL1 and applies a voltage (for example, 1.5V of FIG. 1) to the corresponding source line DSL1.

Thereafter, the word line WLn of the first memory block 411 is activated to turn on the normal cell NC and the floating body transistors of the dummy cells DC0 and DC1. The selected bit lines BL1 and BL2 generate bit line voltages reflecting threshold voltages according to data stored in a normal cell. That is, the voltage corresponding to the value obtained by subtracting the threshold voltage Vth1 of the data “1” is generated in the bit line of the normal cell in which the data “1” is stored, and the word line voltage in the bit line in which the data “0” is stored. The voltage corresponding to the value obtained by subtracting the threshold voltage Vth0 is generated.

Similarly, dummy bit lines DBL0 and DBL1 may generate dummy bit line voltages reflecting threshold voltages corresponding to data of dummy cells. That is, the voltage of the subtracted voltage Vth1 of the word line voltage minus the threshold voltage Vth1 is generated in the dummy bit line DBL1 connected to the dummy cell DC1 storing the data “1” and the data “0” is stored. The dummy bit line DBL1 connected to the dummy cell DC1 generates a voltage having the word line voltage minus the threshold voltage Vth0 of the data “0”.

Thereafter, the equalization signal is activated to turn on the equalization transistor to equalize the voltages of the first dummy bit line and the second dummy bit line. Then, an equalization voltage of ((gate voltage-Vth1) + (gate voltage-Vth0)) / 2 is generated in the dummy bit line. This equalizing voltage becomes a reference voltage of the voltage sensing amplifier SA.

Thereafter, the block selection signal PISOi is activated to connect the bit line BL1 and the sensing bit line SBL1, which is the first input of the sensing block 421, to turn on the block selection switch. The sensing bit line SBL2, which is the first input of the sensing block 422, is connected, and the dummy bit line DBL0 is connected to the inversion sensing bit line SBL1B, which is the second input of the sensing block 421. The dummy bit line DBL1 is connected to an inversion detection bit line SBL2B which is a second input of the sensing block 421. The voltage difference between the sense bit line SBL1 and the inversion sense bit line SBL1B and the voltage difference between the sense bit line SBL2 and the inversion sense bit line SBL2B are ΔVth (= Vth1 + Vth0) / 2 and Vth1. It will be a voltage difference of ΔVth (= Vth1 + Vth0) / 2 and Vth0, and the voltage sensing amplifier SA detects and amplifies this difference and reads out data. Since the operation of the voltage sensing amplifier is a matter of course for those skilled in the art, detailed description thereof will be omitted.

That is, the read operation of the capacitorless dynamic memory device according to the present invention reflects the threshold voltages of the dummy cells in which data “0” and “1” are stored in the dummy bit line and equalizes the threshold voltages to use the reference voltage of the voltage-assisted amplifier.

First, embodiments of the present invention have been described with reference to the accompanying drawings, but a person of ordinary skill in the art to which the present invention pertains may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. I can understand that you can. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

As described above, unlike the conventional memory device, the capacitorless dynamic semiconductor memory device of the present invention does not use a dummy word line, and thus, additional time for refreshing the dummy cells is not required. In addition, since the reference voltage of the bit line voltage sensing amplifier is directly generated by using the threshold voltage difference of the dummy cells in the memory block, circuits for generating the reference voltage are simplified, thereby reducing the layout area.

Claims (15)

Memory cells each having a floating body transistor having gates connected to a word line, drains connected to each of the plurality of bit lines, and sources connected to each of the plurality of source lines; A first dummy cell having a floating body transistor having a gate connected to the word line, a drain connected to a first dummy bit line, and a source connected to a first dummy source line, and storing data “1”; A second dummy cell having a floating body transistor having a gate connected to the word line, a drain connected to a second dummy bit line, and a source connected to a second dummy source line and storing data “0”; An equalization transistor for equalizing the first dummy bit line and the second dummy bit line in response to an equalization signal; A bit line selector configured to select one of the plurality of bit lines and connect it to a sense bit line in response to a bit line selection signal; A dummy bit line connection unit configured to select one of the first and second dummy bit lines to connect to the inversion sensing bit line in response to each of the first and second dummy bit line selection signals; And And a sensing unit configured to sense and amplify a voltage difference between the sense bit line and the inversion sense bit line. The method of claim 1, wherein the sensing unit A precharge circuit for precharging the sense bit line and the inversion sense bit line to a precharge voltage level; And And a voltage sensing amplifier configured to sense and amplify a voltage difference between the sense bit line and the inversion sense bit line. The method of claim 1, And when at least one bit line selection signal of the bit line selection signals is activated during a read operation, one of the first and second dummy bit line selection signals is activated together. 4. The equalization transistor of claim 3, wherein the equalizing transistor Equalizing the voltage obtained by adding the voltage of the first dummy bit line and the voltage of the second dummy bit line to a voltage level divided by 2 during the read operation; The voltage of the first dummy bit line is a voltage obtained by subtracting the threshold voltage of the first dummy cell from the voltage applied to the word line, and the voltage of the second dummy bit line is the second voltage from the voltage applied to the word line. A capacitorless dynamic semiconductor memory device, characterized in that the voltage minus the threshold voltage of the dummy cell. 3. The bit line selector of claim 2, wherein the bit line selector Connect the plurality of bit lines and the sense bit line and connect the first and second dummy bit lines to the inverted sense bit line during the precharge operation; The precharge circuit is And precharging the plurality of bit lines and the first and second dummy bit lines to the precharge voltage level during the precharge operation. delete First memory cells each having a floating body transistor having gates connected to a word line, drains connected to each of a plurality of bit lines, and sources connected to each of a plurality of source lines, a gate connected to the word line, and a first memory cell; A first dummy cell having a floating body transistor having a drain connected to a dummy bit line and a source connected to a first dummy source line, and storing data “1”, and a drain connected to the gate and second dummy bit lines connected to the word line; And a memory block having a floating body transistor having a source connected to the second dummy source line and having a second dummy cell in which data “0” is stored; A first sensing unit positioned at one side of the memory block to sense a voltage difference between a first sensing bit line and a first inverting sensing bit line; A second sensing unit positioned on the other side of the memory block to sense a voltage difference between a second sensing bit line and a second inverting sensing bit line; A first bit line selector positioned between the memory block and the first sensing unit and configured to select one of first bit lines among a plurality of bit lines of the memory block in response to an activated first bit line selection signal; A second bit line selector positioned between the memory block and the second sensing unit and selecting one of second bit lines among the plurality of bit lines of the memory block in response to a second bit line selection signal; First and second dummy bit line selectors that select one of the first and second dummy bit lines of the memory block in response to each of the first and second dummy bit line selection signals; A first block connection switch positioned between the first bit line selector and the first sensing unit and configured to connect the selected first bit line of the memory block to the first sense bit line in response to a block selection signal; And And a first dummy bit line connection unit connecting the selected first dummy bit line of the memory block to the first inversion sensing bit line in response to the block selection signal. 8. The method of claim 7, wherein the capacitorless dynamic semiconductor memory device A second block connection switch located between the second bit line selector and the second sensing unit and connecting the selected second bit line of the memory block to the second sensing bit line in response to the block selection signal; And And a second dummy bit line connection unit connecting the selected second dummy bit line of the memory block to the second inversion sensing bit line in response to the block selection signal. delete 8. The method of claim 7, When at least one bit line selection signal of the bit line selection signals is activated during a read operation, one of the first and second dummy bit line selection signals is activated together. Device. delete delete Memory cells each having a floating body transistor having gates connected to a word line, drains connected to each of the plurality of bit lines, and sources connected to each of the plurality of source lines; A first dummy cell having a floating body transistor having a gate connected to the word line, a drain connected to a first dummy bit line, and a source connected to a first dummy source line, and storing data “1”; And A capacitorless dynamic semiconductor memory having a floating body transistor having a gate connected to the word line, a drain connected to a second dummy bit line, and a source connected to a second dummy source line, and having a second dummy cell in which data “0” is stored. In the method of operation of the device, Applying a source voltage to the source of the first and second dummy cells and activating the word line to turn on the memory cells and the first and second dummy cells; Equalizing the voltages of the first dummy bit line and the second dummy bit line; Selecting at least one bit line of the plurality of bit lines and coupling the sense bit line; Selecting one of the first and second dummy bit lines and connecting the inverted sense bit line; And And sensing and amplifying a voltage difference between the sense bit line and the inverted sense bit line. 14. The method of claim 13, prior to turning on the first and second dummy cells. And precharging the plurality of bit lines, the first and second dummy bit lines, the plurality of source lines, and the first and second dummy source lines to a precharge voltage level. A method of operating a capacitorless dynamic semiconductor memory device. delete

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