KR101286537B1 - Video display device for compensating display defect - Google Patents

Abstract

The present invention relates to an image display apparatus capable of compensating for various display defects and improving image quality. The image display apparatus of the present invention stores first shaped defect information for compensating data to be displayed in a vertical defect region of a display panel. One first memory; A second memory storing second shaped defect information for compensating data to be displayed in a horizontal defect area of the display panel; A vertical line compensator for compensating data to be displayed in the vertical line defect area using the first shaped defect information from the first memory and a horizontal line defect area using the second standard defect information from the second memory; A first compensator including a horizontal compensator for compensating data to be output and a multiplexer for selecting an output of the vertical compensator or the horizontal compensator in response to control information indicating the direction of the vertical or horizontal lines; A second compensator distributing the data compensated by the first compensator spatially and temporally by using frame rate control dithering; A third compensator connected to the second compensator and compensating data to be displayed in a point defect area of the display panel by using point defect information stored in one of the first and second memories; And a driver configured to supply data compensated by the first to third compensators to the display panel.

Description

VIDEO DISPLAY DEVICE FOR COMPENSATING DISPLAY DEFECT}

The present invention relates to a data processing circuit of an image display device, and more particularly, to an image display device capable of improving image quality by compensating for various display defects with data.

Recently, a flat panel display such as a liquid crystal display (LCD), a plasma display panel (PDP), an organic light emitting diode (OLED) display, or the like is mainly used as an image display device. .

The image display apparatus may complete a display panel displaying an image and then go through an inspection process of detecting a display defect. Although the display panel detected as a display defect in the inspection process undergoes a repair process for the defective portion, there exists a display defect that cannot be solved even by the repair process.

The display defect is mainly caused by the variation in the exposure amount due to the overlapping exposure and the aberration of the multi-lenses during the multi exposure of the exposure equipment used in the thin film pattern forming process. Due to the variation in the exposure amount, the width of the thin film pattern is varied, thereby causing parasitic capacitance variation of the thin film transistor, height variation of column spacers maintaining a cell gap, and parasitic capacitance variation between signal lines. This deviation causes luminance deviation in the display image, resulting in display defects. Display defects due to variations in the exposure dose are displayed on the display panel in the form of vertical lines or horizontal lines depending on the scanning direction of the exposure equipment. Such display defects in the form of vertical lines or horizontal lines are not solved through improvement of the process technology.

In addition, the display defect may be displayed as a point defect by a defect pixel into which foreign matter is introduced. The repair process is performed on the defective pixel, but the point defect is also generated by the repaired pixel. For example, when the defective pixel is darkened by the repair process, the darkened pixel may be displayed as a black point defect in the white image. In addition, when the repair process of linking a darkened repair pixel with a neighboring normal pixel is performed, data supplied to the normal pixel needs to be distributed and charged to the repaired pixel linked to each other. May be marked as defective.

Accordingly, in recent years, a method for circuitry compensating for a display defect that cannot be solved in a process has been considered. However, as the horizontal or vertical line display defects due to the difference in exposure doses differ in luminance distribution and defect position information, the conventional circuit compensation method cannot apply the horizontal line data compensation circuit to a display device having vertical line display defects, and conversely, the vertical line data There is a problem that the compensation circuit cannot be applied to a display device having a horizontal display defect. In addition, in the conventional circuit compensation method, the compensation value is not adaptively processed according to the luminance of the defective area. For example, quantifying the compensation value of a defective area by a method of correcting the brightness brighter than the surrounding normal area assuming that the defective area is dark, or by using a method of correcting the brightness brighter than the normal area when the defective area is bright. And there is a problem that is difficult to systemise.

 Accordingly, a conventional image display apparatus requires a data compensation circuit that can be commonly applied without discriminating the image display apparatus having a horizontal line or vertical line display defect and can adaptively add or decrease a compensation value according to the position of the defect region. In addition, a simple configuration of the data compensation circuit is required for cost reduction.

SUMMARY OF THE INVENTION An object of the present invention is to provide an image display device capable of data compensating for various display defects and simplifying a circuit configuration.

An image display device according to the present invention includes a display panel; A first memory storing first shaped defect information for compensating data to be displayed in a vertical defect area of the display panel; A second memory storing second shaped defect information for compensating data to be displayed in a horizontal defect area of the display panel; A vertical line compensator for compensating data to be displayed in the vertical line defect area among the input data by using the first standardized defect information from the first memory, and the input data using the second standardized defect information from the second memory. A first compensation including a horizontal line compensator for compensating data to be displayed in the horizontal defect area and a multiplexer for selecting an output of the vertical line compensator or the horizontal line compensator in response to control information indicating the direction of the vertical line or horizontal line; part; A second compensator distributing the data compensated by the first compensator spatially and temporally by using frame rate control dithering; A third compensator connected to the second compensator and compensating data to be displayed in a point defect area of the display panel by using point defect information stored in one of the first and second memories; And a driver configured to supply data compensated by the first to third compensators to the display panel.

Each of the first and second shaping defect information includes position information of a shaping defect region such as the vertical line or a horizontal line, compensation data according to the position of the shaping defect region, and a gray level for dividing the compensation data into a plurality of gray scale intervals. And section information, wherein the point defect information includes position information of the point defect region, compensation data according to the position of the point defect region, and gray scale section information that divides the compensation data into a plurality of gray scale intervals.

 Each of the vertical line and horizontal line compensators may include a gray scale determination unit configured to output gray scale interval information corresponding to the input data using the gray scale interval information from the corresponding memory; A position determination unit for outputting position information of the defective area corresponding to the input data by using the position information of the shaped defective area from the memory; Compensation data selection for outputting compensation data corresponding to the input data among the compensation data of the defective area from the corresponding memory using the gradation section information from the gradation determination unit and the position information from the position determination unit. Wealth; And an operator configured to compensate the input data by adding or subtracting compensation data from the compensation data selector to the input data.

The control information includes a first bit indicating a direction of the vertical line or a horizontal line, a second bit indicating the presence or absence of the shaped defect area, and a third bit indicating the presence or absence of the point defect area, and the control. The information is stored in one of the first and second memories, or is set by an option pin of a timing controller in which the first to third compensation units are embedded.

Each of the vertical line compensator and the horizontal line compensator compensates the data by dividing the main area of the vertical or horizontal defective area into a boundary area between the main area and the normal area.

The data compensation circuit of the image display device according to the present invention can efficiently compensate for deterioration in image quality due to display defects by simultaneously compensating vertical defects and vertical defects in vertical or horizontal lines. In addition, the data compensation circuit of the image display apparatus according to the present invention may finely compensate the luminance difference between the boundary portions of the shaping defect regions by spatially and temporally distributing the compensation data applied to the shaping defect regions using the second compensation unit. .

1 illustrates a liquid crystal display for compensating for display defects according to an exemplary embodiment of the present invention.

The liquid crystal display shown in FIG. 1 includes a compensation circuit 105 and a timing controller 104, a data driver 101 and a gate driver 102 that drive the liquid crystal panel 103. The compensation circuit 105 may be implemented as one semiconductor chip together with the timing controller 104.

The compensation circuit 105 inputs data (Re, Ge, Be) input from the outside and a plurality of synchronization signals (Vsync, Hsync, DE, DCLK). In the memory of the compensation circuit 105, information on the shape defect area including positional information, gradation information, and compensation data about the shape defect area such as regular horizontal or vertical lines is stored. In addition, the memory stores information on the pointer defect area, including positional information about the point defect, gray level information, and compensation data. The compensation circuit 105 compensates and outputs data to be displayed in the shaping defect area by using the information of the shaping defect area. The compensation circuit 105 divides the shaped defect area into a main area and a boundary area to compensate for data (first compensation step). Subsequently, spatially and temporally distributed compensation data of the defective defect area is finely compensated for using the frame rate control (FRC) dithering method (second compensation step). The compensation circuit 105 compensates and outputs data of the point defect area by using the point defect information (third compensation step). The compensation circuit 105 supplies the compensated data Rc, Gc, Bc and the plurality of synchronization signals Vsync, Hsync, DE, DCLK to the timing controller 104. The compensation circuit 105 supplies the data to be displayed in the normal region to the timing controller 104 without compensation. The detailed configuration of the compensation circuit 105 will be described later.

The timing controller 104 aligns the data Rc, Gc, and Bc input from the compensation circuit 105 and outputs the data to the data driver 101. The timing controller 104 uses a plurality of synchronization signals Vsync, Hsync, DE, and DCLK. A data control signal DDC for controlling the driving timing of the data driver 101 and a gate control signal GDC for controlling the driving timing of the gate driver 102 are generated and output.

The data driver 101 converts the digital data Rc, Gc, and Bc from the timing controller 104 into analog data by using gamma voltage in response to the data control signal DDC of the timing controller 104. Output to the data line of (103).

The gate driver 102 sequentially drives the gate line of the liquid crystal panel 103 in response to the gate control signal GDC of the timing controller 104.

The liquid crystal panel 103 displays an image through a pixel matrix in which a plurality of pixels are arranged. Each pixel implements a desired color by a combination of red, green, and blue sub-pixels that adjust the light transmittance by varying the liquid crystal array according to the data signal. Each subpixel includes a thin film transistor TFT connected to a gate line 17 and a data line 16, a liquid crystal capacitor Clc and a storage capacitor Cst connected in parallel with the thin film transistor TFT. The liquid crystal capacitor Clc charges the difference voltage between the data signal supplied to the pixel electrode through the thin film transistor TFT and the common voltage Vcom supplied to the common electrode, drives the liquid crystal according to the charged voltage, . Orthogonal defect regions, such as vertical lines or horizontal lines, which can be included in the liquid crystal panel 103 in the process, and point defect regions display data compensated by the compensation circuit 105. Therefore, since the luminance difference between the normal region and the defective region is prevented in the liquid crystal panel 103, the image quality can be improved.

On the other hand, the information of the shaping defect area and the information of the point defect area to be stored in advance in the memory of the compensation circuit 105 are set as follows.

The display defects can be classified into regular defects in which vertical or horizontal defects are regularly displayed due to variations in exposure dose, and point defects in which point defects are irregularly displayed due to inflow of foreign matter. The atypical defects and the point defects are detected in the process of inspecting the image display apparatus, and compensation data for compensating for the detected stereotype defects and compensation data for compensating for the point defects are set in the memory of the compensation circuit 105. Stored.

First, when a shaping defect such as a vertical line or a horizontal line is detected through the luminance test of the image display device, the width of the segmentation section and the position information of the boundary region according to the type of the shaping defect and the degree of spotting of the shaping defect area are set, and the shaping is performed. The compensation data for compensating for the measured luminance difference or color difference is set by measuring the degree of blemish of the defective area, that is, the luminance difference or color difference between the normal area and the defective area.

For example, a regular vertical line defect area may be detected as shown in FIG. 2 or a regular horizontal line defect area may be detected as shown in FIG. As shown in FIG. 4, each of the vertical line defect regions is long in the vertical direction and has a constant luminance, and a boundary region in which the luminance is gradually symmetrically positioned on both sides with respect to the main region C1 ( SG1, SG2). In addition, as shown in FIG. 5, each of the horizontal defect regions is also divided into a main region C1 long in the horizontal direction and boundary regions SG1 and SG2 symmetrically positioned at both sides with respect to the main region C1. Can be. The boundary regions SG1 and SG2 of the display defects may be divided into a plurality of boundary sections symmetrical with respect to the main region C1 as a boundary region where the luminance of the main region C1 and the normal region overlap. The boundary regions SG1 and SG2 display luminance closer to the main region C1 toward the main region C1 and luminance closer to the normal region toward the normal region.

In the shaping defect area, the positional information of the main area C1 is set according to the start position and the width of the main area C1. The position information of the boundary regions SG1 and SG2 is automatically set according to the number of division sections and the width of the division sections of the boundary regions SG1 and SG2 based on the position information of the main region C1. The number of divided sections and the width of the divided sections of the boundary areas SG1 and SG2 are equal to the width of the main area C1 and the main area C1 within a range not departing from the rule of the dither pattern for distributing the compensation data spatially and temporally. It may be adjusted according to the size of the corresponding compensation data.

Compensation data a1 for the main region C1 is set to compensate for the luminance difference between the main region C1 and the normal region of the shaped defect region, and the compensation data for the symmetrically located boundary regions SG1 and SG2. b1 to e1 are automatically set to gradually decrease. In addition, since the characteristics of the output gamma voltage are different for each of the divided gradation intervals A, B, C, and D, as shown in FIG. 6, the compensation data a1 to e1 of the defect region are gamma. The characteristics are set to have different compensation values according to different gradation intervals A, B, C, and D. Further, the compensation data a1 to e1 of the shaped defect area may be set differently according to the position of the display defect area.

As such, information about the shaping defects detected in the inspection process, that is, the position information of the shaping defects, the compensation data optimized according to the position of the shaping defects for each gradation section, and the gradation section information indicating the gradation section are stored in the memory. do.

In addition, the inspection process detects the point defect area, sets the position information and the optimal compensation data for the detected point defect area, and stores the set position information and the compensation data in the memory. That is, the compensation data of the point defect area is optimized and stored according to the degree of the display defect for each gray level section in the same manner as the compensation data of the vertical or horizontal line defective area, and the gray level information indicating the gray level section is displayed in the display device. Stored in memory.

For example, when a bright pixel is detected due to the inflow of foreign matter or the like in the inspection process, the bright pixel is separated from the signal line and darkened as shown in FIG. 7, and the dark pixel 10 is separated from the neighboring normal pixel 11. The link is repaired through the link pattern 12. In this case, the point defect may be represented by the link pixels 13 including the normal pixel 11 and the dark point pixel 10 linked to each other. This is because in the link pixels 13, the data supplied to the normal pixel 11 must be distributed and charged to the linked dark spot pixel 10, so that the amount of data charge is increased in comparison with the normal pixels 14 which are not linked with other pixels. Because it decreases. In order to compensate for the point defects caused by the decrease in the amount of data charging, the compensation data measures the luminance difference or chromaticity difference between the normal pixel 14 and the link pixels 13, that is, the point defect region and the normal region, and then the measured luminance. Compensation data that can compensate for the difference or chromaticity difference is set. Further, the compensation data of the point defect area is optimized according to the position of the point defect for each gradation interval, and is stored in the memory together with the position information and the gradation interval information of the point defect.

8 illustrates a compensation circuit of the liquid crystal display according to the first embodiment of the present invention.

The compensation circuit 105 shown in FIG. 8 uses the memory 40 in which the shaping defect information and the point defect information are stored, and the data of the shaping defect area Re, Ge, Be using the shaping defect information from the memory 40. ) And a second compensation that finely compensates by spatially and temporally distributing the data compensated by the first compensation unit 30 and the data (Rm1, Gm1, Bm1) compensated by the first compensation unit 30 using the FRC dithering method. And a third compensator 170 connected to the second compensator 160 and compensating data of the point defect area by using the point defect information from the memory 40. The compensation circuit 105 outputs data of the normal region without data compensation.

As described above, the shaping defect information including the positional information PD1 of the shaping defect area, the gradation section information GD1, and the compensation data CD1 is stored in the memory 40 as described above. The positional information PD1 of the shaping defect area indicates the start and end position information of each defect area in the number of pixels. For example, the position information PD1 of the shaping defect region indicates the main region included in the shaping defect region and the start position information and the end position information of each of the divided sections of the boundary region in the number of pixels. The compensation data CD1 is used to compensate for the luminance difference or chromaticity difference of the defective area with respect to the normal area, and is classified and stored according to the gradation section and the position of the defective area. Compensation data CD1 of the shaping defect area includes the main area of each shaping defect area and correction values optimized for each of the divided sections of the boundary area. The gray scale information GD1 indicates a plurality of gray scale information divided according to the gamma characteristic. The memory 40 also stores point defect information including the position information PD2 for the point defect area, the gradation section information GD2, and the compensation data CD2.

The compensation circuit 105 further includes a bit extension unit 20 that bit-extends the input data R, G, and B from the outside and supplies the bit data to the first compensation unit 30. For example, the bit extension unit 20 adds 3 bits ("000") to 8 bits of input data as the lower bits to bit expand the data into 11 bits, and expands the bit extended data (Re, Ge, Be). Supply to the first compensation unit 30.

The first compensator 30 compensates and outputs input data (Re, Ge, Be) to be displayed in a shaped defect area such as a vertical line or a horizontal line by using the shaped defect information PD1, GD1, and CD1 of the memory 40. do. The first compensation unit 30 compensates the data by adding or subtracting the compensation data PD1 corresponding to the data of the shaping defect area. The first compensator 30 outputs data of the normal region without compensation.

The second compensator 160 finely compensates by spatially and temporally distributing the data Rm1, Gm1, and Bm1 compensated by the first compensator 30 using the FRC dithering method. Compensation data of the boundary region in the shaping defect region is spatially and temporally distributed by the FRC dithering method to finely compensate the luminance difference of the boundary region. For example, the second compensator 160 distributes the lower bit portion to which the compensation data is applied from the data Rm1, Gm1, and Bm1 from the first compensator 30 in a spatial and temporal manner using a dither pattern. Accordingly, the fine luminance difference in the shaping defect region, that is, the boundary luminance difference between the shaping defect region and the normal region can be further finely corrected.

The third compensator 170 compensates for the data Rm2, Gm2, and Bm2 to be displayed in the point defect area by using the point defect information PD2, GD2, and CD2 stored in the memory 40. The third compensator 170 outputs data of the normal region without compensation.

9 illustrates the first compensator 30 and the memory 40 shown in FIG. 8.

The first compensation unit 30 illustrated in FIG. 9 includes a vertical line compensator 70 and a horizontal line compensator 80 to be applied to each display device having vertical line defects or horizontal line defects. A multiplexer (hereinafter referred to as MUX) 90 for selecting an output of the vertical line compensator 70 or the horizontal line compensator 80 according to whether the horizontal line or the horizontal line is provided.

The memory 40 includes a first memory 42V connected to the vertical line compensator 70 and storing vertical line defect information, and a second memory 42H connected to a horizontal line compensator 80 and storing horizontal line defect information. Equipped. The first memory 42V includes an electrically erasable programmable read only memory (EEPROM) 44V storing positional information PD1V, gradation section information GD1V, and compensation data CD1V for a horizontal defective region, and an EEPROM 64V. And a register 46V for temporarily storing the data PD1V, GD1V, and CD1V stored in the circuit and supplying the data PD1V, GD1V, and CD1V to the vertical line compensator 70. The second memory 42H includes an EEPROM 44H storing position information PD1H, gradation section information GD1H, and compensation data CD1H for a horizontal defect area, and data PD1H, stored in an EEPROM 64H. And a register 46H for temporarily storing the GD1H and CD1H and supplying the horizontal line compensator 80 to the horizontal line compensator 80. Two EEPROMs 44V and 44H may be implemented in one, and two registers 46V and 46H may also be implemented in one. Instead of the EEPROMs 44V and 44H, a partial area of an extended display identification data (EDID) ROM storing identification information such as resolution of a display device may be allocated and used. In addition, the specific address of any of the EEPROMs 44V and 44H indicates orientation information of the shape defect area indicating whether the shape defect area is a vertical line defect or a horizontal line defect, and whether or not the shape defect area is compensated for. Control information (CS) including the structured defect compensation information indicating a and point compensation information indicating whether or not to compensate for the point defect area may be stored. For example, each of the three bit data of one byte allocated as the control information CS represents the three pieces of information. The control information CS may be set to values of three option pins of the timing controller 104 in which the compensation circuit 105 is embedded.

The vertical line compensator 70 adjusts the gray scale determiner 72, the position determiner 74, the compensation data selector 76, and the calculator to compensate for the input data Re, Ge, Be displayed in the vertical defect area. 78).

The gray scale determination unit 72 analyzes the gray scale values of the input data Re, Ge, and Be, and input data Re, Ge, Be from the gray scale section information GD1V read from the first memory 42V. The gray level information included in each is selected and output to the compensation data selector 76. For example, the gradation section information (GD1V) is divided into 256 gradations according to a gamma characteristic, and three gradation sections (gradation section 1: 30-70 gradation, gradation section 2: 71-150 gradation, gradation section 3: 151-250 gradation) It can be divided into The gray scale determination unit 72 selects and outputs gray scale section information including gray scale values of the input data Re, Ge, and Be among the three gray scale section information.

 The position determiner 74 uses the input data Re, Ge, or the like by using at least one sync signal among the vertical sync signal Vsync, the horizontal sync signal Hsync, the data enable signal DE, and the dot clock DCLK. The pixel position in the horizontal direction of Be) is determined. For example, the position determiner 74 determines the pixel position in the horizontal direction of the input data Re, Ge, Be while counting the dot clock DCLK in the enable period of the data enable signal DE. . The position determining unit 74 compares the pixel position of the input data Re, Ge, Be with the positional information PD1V of the vertical line defective region read from the first memory 42V, and detects the vertical line defective region. The positional information of the defect area is selected and output to the compensation data selector 76.

The compensation data selecting unit 76 may input input data among the compensation data CD1V from the first memory 42V in response to the gray level information selected by the gray level determining unit 72 and the location information selected by the position determining unit 74. Select and output compensation data corresponding to each of (Re, Ge, Be). In other words, the compensation data selecting unit 76 selects and outputs compensation data according to the position information of the position determining unit 74 within the corresponding gradation section selected according to the gradation section information of the gradation determining unit 72. If the location information indicates the main region of the vertical defect region, compensation data for compensating the main region is selected and outputted. If the division information of the boundary region is indicated, compensation data for compensating each of the divided intervals is selected and output. .

The calculator 78 compensates the input data Re, Ge, Be to be displayed in the vertical defect region by adding or subtracting the compensation data output from the compensation data selector 76 to each of the input data Re, Ge, Be. To print. For example, the compensation data from the compensation data selection unit 76 is added or subtracted to each of 11 bits of the input data Re, Ge, Be, thereby compensating and outputting the input data Re, Ge, Be.

The horizontal line compensator 80 adjusts the gray scale determiner 82, the position determiner 84, the compensating data selector 86, and the calculator to compensate for the input data Re, Ge, Be to be displayed in the horizontal defect area. 88).

The gradation determination unit 82 analyzes gradation values of the input data Re, Ge, Be, and input data Re, Ge, Be from the gradation section information GD1H read out from the second memory 42H. The gray level information included in each is selected and output to the compensation data selector 86.

The position determiner 84 uses the input data Re, Ge, or the like by using at least one sync signal among the vertical sync signal Vsync, the horizontal sync signal Hsync, the data enable signal DE, and the dot clock DCLK. The pixel position in the vertical direction of Be) is determined. For example, the position determining unit 84 counts the horizontal synchronization signal Hsync in the period in which the vertical synchronization signal Vsync and the data enable signal DE are enabled at the same time, and input data Re, Ge, and Be. The pixel position in the vertical direction is determined. The position determining unit 84 compares the pixel position of the input data Re, Ge, Be with the positional information PD1H of the horizontal defective region read from the second memory 42H, and detects the horizontal defective region. The positional information of the defect area is selected and output to the compensation data selector 76.

The compensation data selecting unit 86 inputs the input data of the compensation data CD1H from the second memory 42H in response to the gray level information selected by the gray level determining unit 82 and the position information selected by the position determining unit 84. Select and output compensation data corresponding to each of (Re, Ge, Be). If the location information indicates the main region of the horizontal defect region, compensation data for compensating the main region is selected and outputted. If the segmentation sections of the boundary region are indicated, compensation data for compensating the respective divided regions is selected and outputted. .

The calculator 88 compensates the input data Re, Ge, Be to be displayed in the horizontal defect area by adding or subtracting the compensation data output from the compensation data selector 86 to each of the input data Re, Ge, Be. To print.

The MUX 90 selects output data of the vertical line compensator 70 or the horizontal line compensator 80 in response to the direction information of the shaping defect in the control information CS. That is, the MUX 90 selects and outputs output data of the vertical line compensator 70 when the direction information of the shaping defect indicates a vertical line, and outputs the horizontal line compensator 80 when the direction information indicates a horizontal line. Select and output the data.

As described above, the first compensator 30 compensates and outputs the input data Re, Ge, Be of the shaping defect region such as the vertical line or the horizontal line in response to the control information CS.

10 illustrates the second compensator 160 illustrated in FIG. 8.

The second compensator 160 illustrated in FIG. 10 includes a frame determiner 162, a pixel position determiner 164, a dither value selector 166, and an adder 168.

The frame determiner 162 detects the number of frames by counting the vertical sync signal Vsync among the plurality of sync signals Vsync, Hsync, DE, and DCLK from the first compensator 30, and detects the detected frame number information. Is output to the dither value selector 166.

The pixel position determiner 164 detects pixel positions of the input data Rm1, Gm1, and Bm1 using at least one of the plurality of synchronization signals Vsync, Hsync, DE, and DCLK. For example, by counting the dot clock DCLK in the enable period of the data enable signal DE, the horizontal position of the input data Rm1, Gm1, and Bm1 is sensed, and the vertical synchronization signal Vsync and data enable are enabled. The pixel vertical position of the input data Rm1, Gm1, and Bm1 is detected by counting the horizontal synchronization signal Vsync in a period where the signal DE is simultaneously enabled, and the detected pixel position information is included in the dither value selector 166. Will output

The dither value selector 166 may include a gray level value corresponding to some lower bits of each of the compensation data applied by the first compensation unit 30, that is, the output data Rm1, Gm1, and Bm1 of the first compensation unit 30; By using the frame number information input from the frame determining unit 162 and the pixel position information input from the pixel position determining unit 164, the corresponding dither values Dr, Dg, and Db are selected in the plurality of dither patterns. Output

The dither value selector 166 stores a plurality of dither patterns previously stored by the designer. For example, the dither value selector 166 has a size of 8 * 32 as shown in Figs. 11A to 11D, and 0, 1/8, 2/8, 3/8, 4/8, 5/8. , Dither patterns are arranged in a look-up table form so that the number of pixels having a dither value of "1" (black) gradually increases according to the grayscale values of 6/8, 7/8, and 1 (1 Dither pattern having a gray value of (not shown). Each pixel of the dither patterns has a dither value of "1" (black) or "0", and the gray value of each of the dither patterns is determined in proportion to the number of pixels whose dither value is "1". Also, even for the same gray level value, the dither patterns store a plurality of dither patterns having different positions for each frame, that is, for example, pixels having a pixel position of "1" in each of the plurality of frames FRAME1 to FRAME8. In other words, the dither value selector 166 stores a plurality of dither patterns different for each gray level and for each frame. The size of the dither patterns and the position of the pixel having the dither value of "1" in each of the dither patterns may vary in accordance with the needs of the designer. Because of the dither patterns, compensation data applied to the shaped defect region in the first compensator 30 is spatially and temporally distributed, thereby making it possible to finely compensate for the luminance difference between the shaped defect regions.

When each of the data Rm1, Gm1, and Bm1 output from the first compensator 30 includes 11 bits, the dither value selector 166 selects a dither value using the lower 3 bits of each of the 11 bit data. The remaining 8 bits are output to the adder 168. Here, three bits are portions to which compensation data is applied in the first compensation unit 110, and three bits of data corresponding to the normal region are set to “000”. Then, the dither value selecting unit 166 may include a gray level value corresponding to the lower 3 bits of each of the input data Rm1, Gm1, and Bm1 among the dither patterns shown in FIGS. 11A through 11D, and the frame determination unit 162. One dither pattern corresponding to the frame number information is selected, and 1 corresponding to the pixel position of each of the input data Rm1, Gm1, and Bm1 is selected by using the pixel position information from the pixel position determining unit 164 in the selected dither pattern. The dither values Dr, Dg, and Db by bits are selected and output to the adder 168.

The adder 168 includes the upper 8 bits separated from the lower 3 bits of each of the data Rm1, Gm1, and Bm1 by the dither value selector 166, and the dither values Dr, Dg, and D1 selected by the dither value selector 166. Db) is added and output to the third compensation unit 170.

Accordingly, the second compensator 160 distributes the compensating data portion in the output data Rm1, Gm1, and Bm1 from the first compensator 110 by using the FRC dithering method to spatially and temporally distribute the portion of the fixed defect region. The luminance difference is further finely compensated to prevent deterioration of image quality due to compensation data.

12 illustrates the third compensation unit 170 illustrated in FIG. 8.

The third compensator 170 illustrated in FIG. 12 includes a gray scale determiner 172, a position determiner 174, a compensation data selector 176, and a calculator 178. Point defect information PD2, GD2, and CD2 for compensation of the point defect area are stored in any one of the first and second memories 42V and 42H shown in FIG.

The gray scale determining unit 172 analyzes the gray scale values of the input data Rm2, Gm2, and Bm2 to be supplied to the link pixels in the point defect area, and controls the gray scale values from any one of the first and second memories 42V and 42H. The gray level information including the input data Rm2, Gm2, and Bm2 is selected from the section information GD2 and output to the compensation data selector 178.

The position determiner 174 may input data using at least one of a vertical sync signal Vsync, a horizontal sync signal Hsync, a data enable signal DE, and a dot clock DCLK input from an external system. The pixel position of (Rm2, Gm2, Bm2) is determined. For example, the position determiner 174 detects a horizontal position of the input data Rm1, Rm2, and Rm3 by counting the dot clock DCLK in the enable period of the data enable signal DE, and vertically synchronizes the signal. The pixel vertical position of the input data Rm1, Rm2, and Rm3 is sensed by counting the horizontal synchronization signal Vsync in a period in which Vsync and the data enable signal DE are simultaneously enabled. The position determiner 174 compares the detected pixel position of the input data Rm2, Gm2, and Bm2 with the positional information PD2 of the point defective area from any one of the first and second memories 42V and 42H. When detected as a point defect area, the detected pixel position information is output to the compensation data selector 178.

The compensation data selector 176 is configured to select from one of the first and second memories 42V and 42H in response to the gradation section information selected by the gradation determiner 172 and the positional information selected by the position determiner 174. Among the compensation data CD2, compensation data corresponding to the input data Rm2, Gm2, and Bm2 are selected and output.

The calculator 178 adds or subtracts the compensation data and the input data Rm2, Gm2, and Bm2 output from the compensation data selector 176.

Accordingly, the third compensation unit 170 compensates and outputs the data Rm2, Gm2, and Bm2 of the point defect area.

As described above, in the compensation circuit according to the first embodiment of the present invention, the vertical line compensator 70 and the horizontal line compensator 80 of the first compensator 30 use respective memories 42V and 42H, By selecting the outputs of the compensator 70 and the horizontal line compensator 80 according to the direction information of the shaping defect, the luminance difference of the shaping defect region can be compensated. In addition, the compensation circuit according to the first embodiment of the present invention uses the second compensation unit 160 to disperse the compensation data applied to the data of the shaping defect region in the first compensation unit 30 in a spatial and temporal manner. The luminance difference of the boundary portion of the region may be finely compensated, and the luminance difference of the point defect region may be compensated by using the third compensator 170.

Meanwhile, the data compensation circuit according to the embodiment of the present invention described above may be applied not only to a liquid crystal display but also to other image display devices such as an OLED and a PDP.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

1 is a view showing a liquid crystal display device according to the present invention.

2 is a view showing a vertical line defect region displayed on a liquid crystal panel.

3 is a diagram showing a horizontal defect area displayed on a liquid crystal panel.

FIG. 4 is an enlarged view of one vertical line region shown in FIG. 2; FIG.

FIG. 5 is an enlarged view of one horizontal line region shown in FIG. 3; FIG.

6 is a graph illustrating gamma characteristics of an output voltage according to input data.

7 illustrates a point defect area displayed on a liquid crystal panel.

8 is a diagram illustrating a data compensation circuit according to a first embodiment of the present invention.

FIG. 9 is a diagram illustrating a memory and a first compensator shown in FIG. 8. FIG.

FIG. 10 is a diagram illustrating a second compensator shown in FIG. 8. FIG.

11A to 11D are diagrams illustrating a plurality of dither patterns stored in the dither value selection unit shown in FIG. 10.

FIG. 12 is a diagram illustrating a third compensator shown in FIG. 8. FIG.

Claims (5)

Display panel; A first memory storing first shaped defect information for compensating data to be displayed in a vertical defect area of the display panel; A second memory storing second shaped defect information for compensating data to be displayed in a horizontal defect area of the display panel; A vertical line compensator for compensating data to be displayed in the vertical line defect area among the input data by using the first standardized defect information from the first memory, and the input data using the second standardized defect information from the second memory. A first compensation including a horizontal line compensator for compensating data to be displayed in the horizontal defect area and a multiplexer for selecting an output of the vertical line compensator or the horizontal line compensator in response to control information indicating the direction of the vertical line or horizontal line; part; A second compensator distributing the data compensated by the first compensator spatially and temporally by using frame rate control dithering; A third compensator connected to the second compensator and compensating data to be displayed in a point defect area of the display panel by using point defect information stored in one of the first and second memories; And a driving unit which supplies data compensated by the first to third compensation units to the display panel. The method according to claim 1, Each of the first and second shaped defect information, Location information of the shaping defect region such as the vertical line or the horizontal line, compensation data according to the position of the shaping defect region, and gradation section information dividing the compensation data into a plurality of gradation sections, The point defect information And position information of the point defect area, compensation data according to the position of the point defect area, and gradation section information for dividing the compensation data into a plurality of gradation sections. The method according to claim 2, Each of the vertical and horizontal line compensators A gray scale determination unit configured to output gray scale interval information corresponding to the input data using the gray scale interval information from the memory; A position determination unit for outputting position information of the defective area corresponding to the input data by using the position information of the shaped defective area from the memory; Compensation data selection for outputting compensation data corresponding to the input data among the compensation data of the defective area from the corresponding memory using the gradation section information from the gradation determination unit and the position information from the position determination unit. Wealth; And a calculator configured to compensate the input data by adding or subtracting compensation data from the compensation data selector to the input data. The method according to claim 1, The control information includes a first bit indicating the direction of the vertical line or the horizontal line, a second bit indicating the presence or absence of the shaped defect area, and a third bit indicating the presence or absence of the point defect area, The control information may be stored in one of the first and second memories, or set by an option pin of a timing controller in which the first to third compensation units are embedded. The method according to claim 1, Each of the vertical line compensator and the horizontal line compensator And the data is compensated by dividing the main region of the vertical or horizontal defect region and a boundary region between the main region and the normal region.

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