KR101270643B1 - Tunneling field effect transistor and manufacturing method thereof - Google Patents

Tunneling field effect transistor and manufacturing method thereof Download PDF

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Publication number
KR101270643B1
KR101270643B1 KR1020120079375A KR20120079375A KR101270643B1 KR 101270643 B1 KR101270643 B1 KR 101270643B1 KR 1020120079375 A KR1020120079375 A KR 1020120079375A KR 20120079375 A KR20120079375 A KR 20120079375A KR 101270643 B1 KR101270643 B1 KR 101270643B1
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South Korea
Prior art keywords
recess
source
gate
drain
region
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KR1020120079375A
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Korean (ko)
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박영준
김희중
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서울대학교산학협력단
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66931—BJT-like unipolar transistors, e.g. hot electron transistors [HET], metal base transistors [MBT], resonant tunneling transistor [RTT], bulk barrier transistor [BBT], planar doped barrier transistor [PDBT], charge injection transistor [CHINT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/7311—Tunnel transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/737—Hetero-junction transistors
    • H01L29/7371—Vertical transistors
    • H01L29/7376—Resonant tunnelling transistors

Abstract

The tunneling field effect transistor according to the present invention comprises a semiconductor substrate having a gate recess having a predetermined depth, a gate formed through a gate insulating layer in the recess, and a first conductive dopant. A drain doped with a source and a second conductivity type dopant formed on one side of the gate recess deeper than the depth of the recess and formed deeper than the depth of the gate recess on the other side of the recess (drain).

Description

Tunneling Field Effect Transistor and Manufacturing Method Thereof}

The present invention relates to a tunneling field effect transistor and a method of manufacturing the same.

Currently, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) continue to be miniaturized and integrated. Following this trend, the channel length of the Field Effect Transistor has been continuously reduced, resulting in drain induced barrier lowering (DIBL), punchthrough, impact ionization and subthreshold leakage currents. Short channel effects such as subthreshold leakage current occur. Power consumption, along with the short channel effect, is one of the other important issues in current nanoelectronics. Scaling the supply reduces the energy required for switching, but in today's integrated circuits an increase in gate voltage of at least 60 mV is required to increase the current by about 10 times at room temperature.

To overcome these limitations, Tunneling Field Effect Transistors (TFETs), which can inject charge carriers into channels using quantum mechanical effects called band-to-band tunneling, are proposed. It became. The operation mechanism of the tunneling field effect transistor will be described with reference to FIG. 1. The band diagram before biasing the n-channel TFET is shown in Figure 1 (a). It is very unlikely that electrons located in the valence band before being biased are injected into the body region by tunneling the band. However, if, for example, a constant potential is applied to the source and the drain and a predetermined potential is applied to the gate, the band of the body is shifted down by a certain amount by the applied potential as shown in FIG. do. Therefore, electrons located in the source side balance band are injected into the body region by tunneling the band. This phenomenon is called Band To Band Tunneling (BTBT), which is the main operating mechanism of the TFET.

Conventional TFETs have a drawback in that the width of the channel through which the current flows is formed in a straight line so that the maximum amount of current that can flow is limited. In order to remedy these shortcomings, a method of using a double gate structure, a vertical pillar nanowire structure, and a group III-V compound semiconductor has been proposed. The disadvantage is that it is difficult.

The present invention is to overcome the above-mentioned disadvantages of the prior art, and to provide a structure of a TFET having improved current driving performance by increasing the width of the channel. Another object of the present invention is to provide a structure of a TFET having improved current driving performance using a conventional MOS process. It is another object of the present invention to provide a method for manufacturing a TFET having an increased channel width and an improved current driving performance. It is another object of the present invention to provide a method of manufacturing a TFET having improved current driving performance by using a current MOS process.

A tunneling field effect transistor according to the present invention includes a semiconductor substrate having a gate recess having a predetermined depth, a gate formed through a gate insulating film in the recess, and a first conductive dopant. Doped with a source and a second conductivity type dopant formed on one side of the gate recess deeper than the depth of the recess and formed deeper than the depth of the gate recess on the other side of the recess. It includes a drain.

In one embodiment, the source and drain have a predetermined thickness and are located between the substrate and the buried insulating film.

In one embodiment, the outer perimeter of the gated recess does not substantially exceed the outer and inner circumferential surfaces of the source.

In one embodiment, the side portions of the gate, the source and the drain are planar, and the bottom portion is formed in a curved surface.

In one embodiment, the side and bottom portions of the source and drain are both planar.

In one embodiment, a channel is formed parallel to the side and bottom portions of the gate recess.

In one embodiment, the source and the drain are each heavily doped.

The tunneling field effect transistor according to the present invention includes a semiconductor substrate in which a plurality of recesses are formed, a gate formed through a gate insulating film inside a gate recess having a first depth, and a recess having a second depth. A drain is formed around the recess in which the source is formed and the gate is formed in a direction opposite to the source, and surrounds another recess having a second depth, and the recess in which the source is formed and the other recess in which the drain is formed. A buried insulating film is included.

The source and drain have a predetermined thickness and are located between the substrate and the buried insulating film.

In one embodiment, the outer perimeter of the gate recess does not substantially exceed the outer and inner circumferential surfaces of the source.

In one embodiment, the side portion of the recess in which the gate recess and the source are formed is planar, and the bottom portion is formed in a curved surface.

In one embodiment, the gate recess, the side portion and the bottom portion of the one recessed source are all formed in a plane.

In one embodiment, a channel is formed along the side and bottom portions of the gate recess.

In one embodiment, the source and the drain are each heavily doped.

The method of manufacturing a tunneling field effect transistor according to the present invention comprises the steps of preparing a semiconductor substrate, implanting dopants of different conductivity types to form a spaced apart source and drain regions, respectively, between the source region and the drain region. Etching the semiconductor substrate to form a gate recess in contact with the source region and the drain region, forming a gate insulating layer in the gate recess, and forming a gate in the gate recess; Etching a portion of the source region and the drain region, respectively, to form a source region recess and a drain region recess, and filling an insulating layer in the source region recess and the drain region recess.

In one embodiment, the step of forming the source region and the drain region, respectively, is performed by injecting a high concentration of dopants of different conductivity types.

In example embodiments, the forming of the gate recess may be performed by etching the semiconductor substrate so as not to deviate from outer peripheral surfaces of the source region and the drain region.

In example embodiments, the forming of the drain region and the forming of the source region by implanting the dopant may be performed such that a doping profile of the bottom surface of the drain region and the bottom surface of the source region is curved.

In example embodiments, the forming of the gate recess may be performed by etching the semiconductor substrate to form a bottom surface of the gate recess.

In an embodiment, the forming of the source and the drain may be performed by injecting the dopants at different concentrations.

According to the present invention, there is provided a tunneling field effect transistor and a method of manufacturing the same, which overcome the disadvantages of the prior art. In other words, the channel width of the tunneling field effect transistor is increased by the recess and the recess bottom part, so that the current driving performance of the tunneling field effect transistor is improved, and a method for manufacturing the tunneling field effect transistor is provided. In addition, the conventional MOS process is provided with the advantage that it is possible to manufacture a tunneling field effect transistor with improved current driving characteristics than the prior art.

1 is a diagram illustrating a band-to-band tunneling mechanism of a tunneling field effect transistor.
2 is a transparent schematic diagram according to an embodiment of the present invention.
3 and 4 are cross-sectional views A-A 'and BB' of FIG. 2, respectively.
5 is a transparent schematic diagram according to another embodiment of the present invention.
6 and 7 are cross-sectional views illustrating the characteristics of one embodiment of the present invention.
8 to 13 are process cross-sectional views showing an outline of a method of manufacturing a tunneling field effect transistor according to an embodiment of the present invention.
14 is a view showing a comparative example according to the prior art for comparison with the embodiment of the present invention.
15 is a diagram illustrating an embodiment of the present invention.
16 is a diagram illustrating an IV characteristic curve of an embodiment of the present invention.

Description of the present invention is only an embodiment for structural or functional description, the scope of the present invention should not be construed as limited by the embodiments described in the text. That is, the embodiments are to be construed as being variously embodied and having various forms, so that the scope of the present invention should be understood to include equivalents capable of realizing technical ideas.

Meanwhile, the meaning of the terms described in the present application should be understood as follows.

The terms "first "," second ", and the like are used to distinguish one element from another and should not be limited by these terms. For example, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

It is to be understood that when an element is referred to as being "on" or "on" another element, it may be directly on top of the other element, but other elements may be present in between. On the other hand, when an element is referred to as being "in contact" with another element, it should be understood that there are no other elements in between. On the other hand, other expressions that describe the relationship between components, such as "intervening" and "intervening", between "between" and "immediately" or "neighboring" Direct neighbors "should be interpreted similarly.

Singular expressions should be understood to include plural expressions unless the context clearly indicates otherwise, and terms such as "include" or "have" refer to features, numbers, steps, operations, components, parts, or parts thereof described. It is to be understood that the combination is intended to be present, but not to exclude in advance the possibility of the presence or addition of one or more other features or numbers, steps, operations, components, parts or combinations thereof.

Each step may occur differently from the stated order unless the context clearly dictates the specific order. That is, each step may occur in the same order as described, may be performed substantially concurrently, or may be performed in reverse order.

The drawings referred to for explaining embodiments of the present disclosure are exaggerated in size, height, thickness, and the like intentionally for convenience of explanation and understanding, and are not enlarged or reduced in proportion. In addition, any component illustrated in the drawings may be intentionally reduced in size, and other components may be intentionally enlarged in size.

All terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs, unless otherwise defined. Terms such as those defined in the commonly used dictionaries should be construed to be consistent with the meanings in the context of the related art and should not be construed as having ideal or overly formal meanings unless expressly defined in this application. .

Hereinafter, with reference to the accompanying drawings will be described embodiments of the present invention. FIG. 2 is a perspective schematic view of a tunneling field effect transistor (TFET) according to an embodiment of the present invention, FIG. 3 is a sectional view taken along line AA ′ of FIG. 1, and FIG. 4 is a sectional view taken along line BB ′ of FIG. 1. to be. For reference, in FIG. 2, the semiconductor substrate 110 is illustrated as transparent for convenience of understanding. 2, 3, and 4, a tunneling field effect transistor according to an embodiment of the present invention includes a semiconductor substrate 110 having a gate recess R having a predetermined depth, and the recess ( The gate insulating layer 120 formed in R, the gate 130 formed through the gate insulating layer 120 in the gate recess R, and the first conductive dopant are doped and are recessed. A drain doped with a source 140 and a second conductivity type dopant formed deeper than the depth of the recess on one side of the drain and formed deeper than the depth of the recess on the other side of the recess R , 150). 2 and 4, the source 140 and the drain 150 are formed to have a predetermined thickness between the semiconductor substrate 110 and each of the buried insulating layers 160S and 160D. do. Through such a structure, gate-to-gate capacitance and gate-to-drain capacitance can be minimized. In another embodiment, as shown in FIG. 5, the source 140 and the drain 150 may have a structure in which the buried insulating layers 160S and 160D are not buried in order to simplify the manufacturing process. The source and drain are heavily doped with opposite conductivity types. In one embodiment, drain 150 is doped with N + if source 140 is doped with P +. In another embodiment, drain 150 is P + doped if source 140 is doped with N +.

In one embodiment, the outer circumferential surface of the gate recess R does not substantially exceed the outer circumferential surface and the inner circumferential surface of the source 140. The fact that the outer circumferential surface of the gate recess R does not substantially exceed the outer circumferential surface and the inner circumferential surface of the source 140 means that the outer circumferential surface of the gate recess R is not physically formed beyond the outer circumferential surface or the inner circumferential surface of the source 140. Rather, when an operating voltage is applied between the source 140 and the drain 150, and a threshold voltage is applied to the gate 130, band to band tunneling (BTBT) does not occur. This means that the outer circumferential surface of the gate recess R is not formed beyond the outer circumferential surface and the inner circumferential surface of the source 140. This will be described with reference to FIGS. 2 and 6. 6 is a cross-sectional view of a surface where the source 140 is in contact with the gate in which the recess R is formed, and according to a relationship between the outer circumferential surface of the gate and the outer circumferential surface and the inner circumferential surface of the source, Shown by dividing). 6 illustrates a gate 130 and a gate insulating layer 120, and a buried insulating layer 160S is positioned toward the source 140 at a corresponding position. The cross section of the outer circumferential surface of the gate recess is denoted by RP, and the inner perimeter of the source 140 is the interface between the source 140 and the buried insulating film 140S, and is represented by SIP, and the outer circumferential surface of the source 140 ( The outer perimeter is indicated by SOP as an interface between the source 140 and the semiconductor substrate 110. In addition, the region where band-to-band tunneling occurs is indicated as TR. Referring to FIG. 6A, the outer circumferential surface RP of the gate-formed recess coincides with the inner circumferential surface SIP of the source. In this case, the region TR where band-to-band tunneling occurs is located between the inner circumferential surface SIP and the outer circumferential surface SOP of the source. In this case, therefore, the outer perimeter of the gate recess does not substantially exceed the outer circumferential surface of the source or the drain. Referring to FIG. 6B, the outer circumferential surface RP of the gate recess R does not coincide with the inner circumferential surface SIP of the source, and the outer circumferential surface RP of the gate recess is physically the inner circumferential surface SIP of the source. It can be seen that, but the band-to-band tunneling occurs in the TR region when the driving voltage is applied to the source 140 and the drain 150 and the threshold voltage is applied to the gate 130. Can be. Accordingly, in the case of FIG. 6B, the outer circumferential surface RP of the gate recess does not substantially exceed the outer circumferential surface SOP of the source or the inner circumferential surface SIP of the source. Referring to FIG. 6C, the outer circumferential surface RP of the gate recess R does not coincide with the inner circumferential surface SIP of the source, but is physically formed beyond the inner circumferential surface SIP of the source. In the case where the driving voltage is applied to the source 140 and the drain 150, and the threshold voltage is applied to the gate 130, band-to-band tunneling does not occur. Therefore, when formed as shown in FIG. 6C, it can be seen that the outer circumferential surface RP of the gate recess substantially exceeds the inner circumferential surface SIP of the source. Referring to FIG. 6 (d), the outer circumferential surface RP of the gate recess R does not coincide with the inner circumferential surface SIP of the source and is physically formed beyond the outer circumferential surface SOP of the source. It can be seen that band-to-band tunneling does not occur when a driving voltage is applied to the source 140 and the drain 150 formed as described above and a threshold voltage is applied to the gate 130. Therefore, in the case of FIG. 6D, it can be seen that the outer circumferential surface RP of the gate recess substantially exceeds the inner circumferential surface SOP of the source.

2 to 3, the bottom portion of the gated recess R, the bottom portion of the gate 130, the bottom portion of the source 140 and the bottom portion of the drain 150 are shown in FIGS. It is formed into a curved surface. As such, the channel width of the source 140, the drain 150, and the gate 130 is increased by the depth of the semiconductor substrate. In addition, the bottom portion of the source 140, the drain 150, and the gate 130 is formed as a curved surface as shown. At this time, considering the cross section of the bottom of the source 140, the drain 150 and the gate 130, as shown in Figure 7 the bottom of the source 140, drain 150 and the gate 130 in a plane It can be seen that the channel width increases when it is formed in a curved surface compared to when formed (dotted line). Increasing the channel width means that the area where band-to-band tunneling takes place increases, which means that the current in the on state of the transistor increases. Therefore, according to one embodiment of the present invention, there is provided an advantage that a tunneling field effect transistor having excellent driving current characteristics can be obtained.

In another embodiment, the bottom portion of the gated recess R, the bottom portion of the gate 130, the bottom portion of the source 140 and the bottom portion of the drain 150 are planar as shown by the dotted lines in FIG. 7. Is formed. According to the present exemplary embodiment, the channel width of the source 140, the drain 150, and the gate 130 is increased by the depth of the semiconductor substrate. Advantages of increasing the channel width by the recessed depth and the bottom portion of the recess R, the bottom portion of the gate 130, the bottom portion of the source 140 and the bottom portion of the drain 150 can be formed in a plane. The benefits of simplicity of process are at the same time.

Next, a method of manufacturing a tunneling field effect transistor according to an embodiment of the present invention will be described with reference to FIGS. 8 to 13. 8 to 13 are cross-sectional views illustrating an outline of a process of manufacturing a tunneling field effect transistor according to an embodiment of the present invention. Referring to FIG. 8, a semiconductor substrate 110 on which a tunneling field effect transistor according to an embodiment of the present invention is formed is prepared. In one embodiment, the semiconductor substrate is a silicon substrate as shown in FIG. 8. In another embodiment, the semiconductor substrate is a silicon substrate on which a buried oxide film is formed although not shown. The dopant is implanted into the semiconductor substrate to form the source region 142 and the drain region 152, respectively. In an embodiment, the step of forming the source region 142 and the drain region 152 is performed by injecting high concentrations of dopants of different conductivity types using a mask process. As an example, when the N type dopant is implanted at a high concentration to form the source region 142, the drain region 152 is formed by implanting the P type dopant at a high concentration. As another example, when the P type dopant is implanted at a high concentration to form the source region 142, the drain region 152 is formed by implanting the N type dopant at a high concentration. In one embodiment, when dopants are implanted to form the source region 142 and the drain region 152, the dopant implantation energy is strongly controlled at the central portions of the source region 142 and the drain region 152, and the source As shown in FIG. 2, the bottom portion of the source region 142 and the drain region 152 may be formed to have a curved surface by slightly adjusting the injection energy toward the periphery of the region 142 and the drain region 152. In another embodiment, bottom portions of the source region 142 and the drain region 152 are formed in a plane. Forming in this way can simplify the manufacturing process. 8 illustrates the formation of the source region 142 by implanting the dopant of the first conductivity type and the formation of the drain region 152 by implanting the dopant of the second conductivity type, which is purely easy to understand. For this purpose, in the actual process, the source region 142 is formed and the drain region 152 is formed. As another example, after forming the drain region 152, the source region 142 is formed.

Referring to FIG. 9, the gate substrate R is formed by etching the semiconductor substrate 110. In one embodiment, as described above, in one embodiment, the outer circumferential surface of the gate recess R does not substantially exceed the outer circumferential surface and the inner circumferential surface of the source 140. The fact that the outer circumferential surface of the gate recess R does not substantially exceed the outer circumferential surface and the inner circumferential surface of the source 140 means that the outer circumferential surface of the gate recess R is not physically formed beyond the outer circumferential surface or the inner circumferential surface of the source 140. Rather, when an operating voltage is applied between the source 140 and the drain 150, and a threshold voltage is applied to the gate 130, band to band tunneling (BTBT) does not occur. This means that the outer circumferential surface of the gate recess R is not formed beyond the outer circumferential surface and the inner circumferential surface of the source 140.

Referring to FIG. 10, a gate insulating layer 120 is formed in the gate recess R. Referring to FIG. The gate insulating film is an important component that determines the performance of the transistor, and it is necessary to form the gate insulating film in high purity. In one embodiment, after the gate recess R is formed, a cleaning process is performed to form a high purity gate insulating film before forming the gate insulating film 120.

Referring to FIG. 11, a gate 130 is formed in the gate recess R on which the gate insulating layer 120 is formed. In an embodiment, the forming of the gate 130 is performed by forming a material layer forming the gate such that the gate recess R is buried, and then performing a planarization process targeting the semiconductor substrate 110. For example, the planarization process is performed by performing chemical mechanical polishing (CMP). In another example, the planarization process is performed by performing an etch back process.

12 and 13 are cross-sectional views taken along line X-X ', unlike FIGS. Referring to FIG. 12, portions of the source region 142 and the drain region 152 are etched to form a source region recess SR and a drain region recess DR. A buried insulating film is formed in the source region recess SR and the drain region recess DR in a later step. Although only the source region recess SR is illustrated in FIG. 13, the drain region recess DR is formed through the same process or another process.

Referring to FIG. 13, a buried insulating layer 160 is formed in the source region recess SR and the drain region recess DR. In one embodiment, the buried insulating layers 160S and 160D are formed in the source region recess and the drain region recess to form the capacitance between the gate 130 and the source 140 and the capacitance between the gate 130 and the drain 150. Can be reduced. In one embodiment, the buried insulating layers 160S and 160D form an oxide film on the entire surface of the semiconductor substrate 110 to fill the source region recess SR and the drain region recess DR, and then the semiconductor substrate 110. It is formed by performing a planarization process to target the front surface of. In one example, the planarization process is performed by performing the above-described chemical mechanical polishing. In another example, the planarization process is performed by performing the above-described etch back process.

Comparative example

14 is a view showing a comparative example, which is a planar tunneling field effect transistor according to the prior art. The characteristics of the device are as follows. Source and drain doping concentration is 9X10 ^ 19 / cm ^ 3, doping concentration in channel region is 1X10 ^ 19 / cm ^ 3, channel length is 30nm, channel width is 60nm, and hafnium oxide (HfO2) as gate insulating film Was used and the thickness was formed at 2 nm. As shown in FIG. 14, the band-to-band tunneling part is shown in orange, and the band-to-band tunneling part is simply formed in a planar shape.

Example

An embodiment of a tunneling transistor according to an embodiment of the present invention will be described with reference to FIGS. 15 to 16. Device characteristics of the tunneling field effect transistor shown in FIG. 15 are as follows. Source and drain doping concentration is 9X10 ^ 19 / cm ^ 3, doping concentration in channel region is 9X10 ^ 19 / cm ^ 3, recess depth is 230nm, channel length is 30nm, channel width is piX30 + 2X200nm, gate Hafnium oxide (HfO2) was used as the insulating film, and the thickness was formed to 2 nm. That is, all other characteristics except the channel width according to the recess are the same as in the comparative example. FIG. 15 is a perspective view showing an orange region of band-to-band tunneling. FIG. It can be seen that the channel is formed along the shape of the cross section of the gate contacting the source. In comparison with FIG. Since band-to-band tunneling is performed, it can be seen that the area difference is large. From this, it is expected that driving current characteristics of the tunneling field effect transistor according to the embodiment of the present invention are superior to those of the comparative example.

16 illustrates I-V characteristics of a tunneling field effect transistor according to a comparative example and a tunneling field effect transistor according to an embodiment of the present invention. The curve shown in blue in FIG. 16 shows the IV characteristics of the tunneling field effect transistor according to the comparative example, and the curve shown in red shows the recess depth of 230 nm and the bottom portion of the recess having a curved surface. IV characteristics of the tunneling field effect transistor according to the present invention are shown. Referring to the enlarged drawings, it appears that the driving current characteristics of the tunneling field effect transistor according to the present invention are approximately 10 times better under the same conditions.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of illustration, It will be appreciated that other embodiments are possible. Accordingly, the true scope of the present invention should be determined by the appended claims.

110: semiconductor substrate 120: gate insulating film
130: gate 140: source
142: source region 150: drain
152: drain region 160: buried insulating film
R: Gate recess SOP: Source peripheral surface
SIP: circumferential surface of the source RP: circumferential surface of the gate recess
TR: Tunneling Zone

Claims (19)

A semiconductor substrate having a gate recess of a predetermined depth;
A gate formed through the gate insulating layer in the recess;
A source doped with a first conductivity type dopant and formed on one side of the gate recess deeper than the depth of the recess; And
A drain doped with a second conductivity type dopant and partially embedded in the other side of the recess with a buried insulating film formed deeper than a depth of the gate recess, wherein the source and the drain are partially filled with the buried insulating film A tunneling field effect transistor formed by being buried. The method of claim 1,
And an outer perimeter of the recess in which the gate is formed does not substantially exceed the outer and inner circumferential surfaces of the source. The method of claim 1,
A tunneling field effect transistor having side surfaces of the gate, the source, and the drain, and a bottom surface thereof is curved. The method of claim 1,
And a side portion and a bottom portion of the source and drain are planar. The method of claim 1,
And a channel is formed in parallel to side and bottom portions of the gate recess. The method of claim 1,
And the source and the drain are each heavily doped. A semiconductor substrate on which a plurality of recesses are formed;
A gate formed through the gate insulating layer in the gate recess having the first depth;
A source shaped around a recess having a second depth;
A drain surrounding another recess having a second depth and positioned in a direction facing the source with respect to the recess in which the gate is formed; And
And a buried insulating film filling a recess in which the source is formed and another recess in which the drain is formed. The method of claim 7, wherein
And the source and the drain have a predetermined thickness and are positioned between the substrate and the buried insulating film. The method of claim 7, wherein
And an outer perimeter of the gate recess does not substantially exceed an outer circumferential surface and an inner circumferential surface of the source. The method of claim 7, wherein
The tunneling field effect transistor of claim 1, wherein a side surface portion of the recess in which the gate recess and the source are formed is planar, and a bottom surface thereof is curved. The method of claim 7, wherein
The tunneling field effect transistor of which the gate recess, the side portion and the bottom surface portion of the recess in which the source is formed are all formed in a plane. The method of claim 7, wherein
And a channel is formed along side and bottom portions of the gate recess. The method of claim 7, wherein
And the source and the drain are each heavily doped. Preparing a semiconductor substrate;
Implanting dopants of different conductivity types to form source and drain regions spaced apart from each other;
Etching the semiconductor substrate between the source region and the drain region to form a gate recess in contact with the source region and the drain region;
Forming a gate insulating film in the gate recess;
Forming a gate in the gate recess;
Etching a portion of the source region and the drain region, respectively, to form a source region recess and a drain region recess, and
A method of fabricating a tunneling field effect transistor comprising embedding an insulating film in a source region recess and a drain region recess. 15. The method of claim 14,
And forming the source region and the drain region, respectively, by implanting different conductive dopants in high concentrations. 15. The method of claim 14,
Forming the gate recess,
And fabricating the semiconductor substrate so as not to deviate from outer peripheral surfaces of the source region and the drain region. 15. The method of claim 14,
And forming the drain region by implanting the dopant and forming the source region, wherein the doping profiles of the bottom surface of the drain region and the bottom surface of the source region are formed to have a curved surface. 15. The method of claim 14,
Forming the gate recess,
And etching the semiconductor substrate such that the bottom surface of the gate recess is curved. 15. The method of claim 14,
The forming of the source and the drain may include performing the implantation of the dopants at different concentrations.
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KR102273935B1 (en) 2019-12-27 2021-07-06 서강대학교산학협력단 Tunnel field-effect transistor based on negative differential transconductance

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