KR101196048B1 - 다수의 프로세서 간 메모리 액세스의 스케줄링 - Google Patents

다수의 프로세서 간 메모리 액세스의 스케줄링 Download PDF

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KR101196048B1
KR101196048B1 KR1020067010659A KR20067010659A KR101196048B1 KR 101196048 B1 KR101196048 B1 KR 101196048B1 KR 1020067010659 A KR1020067010659 A KR 1020067010659A KR 20067010659 A KR20067010659 A KR 20067010659A KR 101196048 B1 KR101196048 B1 KR 101196048B1
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service
request
qos
model
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KR20060111544A (ko
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볼프-디트리히 베버
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소닉스, 인코퍼레이티드
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    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06QINFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q10/00Administration; Management
    • G06Q10/06Resources, workflows, human or project management; Enterprise or organisation planning; Enterprise or organisation modelling
    • G06Q10/063Operations research, analysis or management
    • G06Q10/0639Performance analysis of employees; Performance analysis of enterprise or organisation operations
    • G06Q10/06395Quality analysis or management
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00Traffic control in data switching networks
    • H04L47/10Flow control; Congestion control
    • H04L47/24Traffic characterised by specific attributes, e.g. priority or QoS
    • H04L47/2425Traffic characterised by specific attributes, e.g. priority or QoS for supporting services specification, e.g. SLA
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00Traffic control in data switching networks
    • H04L47/70Admission control; Resource allocation
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00Traffic control in data switching networks
    • H04L47/70Admission control; Resource allocation
    • H04L47/80Actions related to the user profile or the type of traffic
    • H04L47/805QOS or priority aware
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00Traffic control in data switching networks
    • H04L47/70Admission control; Resource allocation
    • H04L47/82Miscellaneous aspects
    • H04L47/821Prioritising resource allocation or reservation requests
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00Traffic control in data switching networks
    • H04L47/70Admission control; Resource allocation
    • H04L47/82Miscellaneous aspects
    • H04L47/827Aggregation of resource allocation or reservation requests

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  • Engineering & Computer Science (AREA)
  • Business, Economics & Management (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Human Resources & Organizations (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Educational Administration (AREA)
  • Development Economics (AREA)
  • Strategic Management (AREA)
  • General Engineering & Computer Science (AREA)
  • Economics (AREA)
  • Entrepreneurship & Innovation (AREA)
  • Tourism & Hospitality (AREA)
  • Quality & Reliability (AREA)
  • General Business, Economics & Management (AREA)
  • Operations Research (AREA)
  • Game Theory and Decision Science (AREA)
  • Marketing (AREA)
  • Software Systems (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Microcomputers (AREA)
KR1020067010659A 2003-10-31 2004-10-27 다수의 프로세서 간 메모리 액세스의 스케줄링 Expired - Fee Related KR101196048B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/698,905 US7665069B2 (en) 2003-10-31 2003-10-31 Method and apparatus for establishing a quality of service model
US10/698,905 2003-10-31
PCT/US2004/035863 WO2005045727A2 (en) 2003-10-31 2004-10-27 Scheduling memory access between a plurality of processors

Publications (2)

Publication Number Publication Date
KR20060111544A KR20060111544A (ko) 2006-10-27
KR101196048B1 true KR101196048B1 (ko) 2012-11-02

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KR1020067010659A Expired - Fee Related KR101196048B1 (ko) 2003-10-31 2004-10-27 다수의 프로세서 간 메모리 액세스의 스케줄링

Country Status (6)

Country Link
US (1) US7665069B2 (https=)
EP (1) EP1678620B1 (https=)
JP (1) JP5144934B2 (https=)
KR (1) KR101196048B1 (https=)
AT (1) ATE514132T1 (https=)
WO (1) WO2005045727A2 (https=)

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US8868397B2 (en) 2006-11-20 2014-10-21 Sonics, Inc. Transaction co-validation across abstraction layers
US9087036B1 (en) 2004-08-12 2015-07-21 Sonics, Inc. Methods and apparatuses for time annotated transaction level modeling

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US8504992B2 (en) * 2003-10-31 2013-08-06 Sonics, Inc. Method and apparatus for establishing a quality of service model
US7665069B2 (en) 2003-10-31 2010-02-16 Sonics, Inc. Method and apparatus for establishing a quality of service model
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US8650270B2 (en) * 2008-07-10 2014-02-11 Juniper Networks, Inc. Distributed computing with multiple coordinated component collections
US9684633B2 (en) 2013-01-24 2017-06-20 Samsung Electronics Co., Ltd. Adaptive service controller, system on chip and method of controlling the same
CN104247354B (zh) 2013-02-19 2018-03-30 松下知识产权经营株式会社 接口装置以及总线系统
US9270610B2 (en) 2013-02-27 2016-02-23 Apple Inc. Apparatus and method for controlling transaction flow in integrated circuits
WO2018165111A1 (en) 2017-03-06 2018-09-13 Sonics, Inc. An operating point controller for circuit regions in an integrated circuit
US11231769B2 (en) 2017-03-06 2022-01-25 Facebook Technologies, Llc Sequencer-based protocol adapter
US10481944B2 (en) * 2017-08-09 2019-11-19 Xilinx, Inc. Adaptive quality of service control circuit
CN113296874B (zh) * 2020-05-29 2022-06-21 阿里巴巴集团控股有限公司 一种任务的调度方法、计算设备及存储介质

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Cited By (2)

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US8868397B2 (en) 2006-11-20 2014-10-21 Sonics, Inc. Transaction co-validation across abstraction layers

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JP5144934B2 (ja) 2013-02-13
WO2005045727A2 (en) 2005-05-19
JP2007510229A (ja) 2007-04-19
US20050096970A1 (en) 2005-05-05
EP1678620B1 (en) 2011-06-22
KR20060111544A (ko) 2006-10-27
ATE514132T1 (de) 2011-07-15
EP1678620A2 (en) 2006-07-12
US7665069B2 (en) 2010-02-16
WO2005045727A3 (en) 2005-10-06

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