KR101151257B1 - Stack package using lead frame - Google Patents

Stack package using lead frame Download PDF

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KR101151257B1
KR101151257B1 KR20100052117A KR20100052117A KR101151257B1 KR 101151257 B1 KR101151257 B1 KR 101151257B1 KR 20100052117 A KR20100052117 A KR 20100052117A KR 20100052117 A KR20100052117 A KR 20100052117A KR 101151257 B1 KR101151257 B1 KR 101151257B1
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stack
package
lead
frame
stack package
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KR20100052117A
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Korean (ko)
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KR20110132665A (en )
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김병진
이상웅
최호
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앰코 테크놀로지 코리아 주식회사
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    • HELECTRICITY
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    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
    • H01L25/10Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
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    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
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    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1029All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being a lead frame
    • HELECTRICITY
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    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047Details of electrical connections between containers
    • H01L2225/1058Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
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    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
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    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

본 발명은 리드프레임을 이용한 적층형 패키지에 관한 것으로서, 더욱 상세하게는 적층을 위한 하부패키지의 적층패드를 리드프레임을 사용하여, 상부패키지와의 적층시 어라인이 정확하게 이루어질 수 있도록 한 리드프레임을 이용한 적층형 패키지에 관한 것이다. The present invention relates to a multi-layer package using the lead frame, and more particularly, to a laminated pad of the bottom package for stacked using a lead frame, Huh during deposition of the upper package, the using a lead frame to be accurately It relates to a stacked package.
즉, 본 발명은 상부패키지의 솔더볼이 융착되는 하부패키지의 볼패드를 별도의 리드프레임을 기판에 부착시켜 형성해줌으로써, 적층용 솔더볼이 볼패드에 정확하게 맞추어(stand-off height)지며 융착될 수 있도록 한 리드프레임을 이용한 적층형 패키지 및, 하부 패키지용 기판의 상면에 형성되는 적층용 볼랜드를 파인피치로 구현하고자 기판의 상면에 하프에칭된 리드프레임을 미리 부착한 후, 하프에칭된 부분을 절단해줌으로써, 적층용 볼랜드의 파인피치를 용이하게 실현할 수 있도록 한 리드프레임을 이용한 적층형 패키지를 제공하고자 한 것이다. That is, so that the invention may be fused to ball pads on the lower packages is the solder ball of the top package fusion becomes exactly (stand-off height) according to the pad may be formed by giving, the stacking solder balls, ball were attached to a separate lead frame to the substrate after one of the stacked package and the lower laminated Borland for being formed on an upper surface of the package substrate for using a lead frame to implement a fine-pitch pre-attached to half-etching the lead frame on an upper surface of the substrate, to cut the half-etched portion by giving , intended to provide the multi-layer package using a lead frame to be easily realize the fine pitch Borland stacking.

Description

리드프레임을 이용한 적층형 패키지{Stack package using lead frame} Multi-layer package using a lead frame package using lead frame Stack {}

본 발명은 리드프레임을 이용한 적층형 패키지에 관한 것으로서, 더욱 상세하게는 적층을 위한 하부패키지의 볼패드를 리드프레임을 사용하여 형성해줌으로써, 상부패키지와의 적층시 어라인이 정확하게 이루어질 수 있고, 볼패드간의 파인피치를 용이하게 구현할 수 있도록 한 리드프레임을 이용한 적층형 패키지에 관한 것이다. The present invention by giving the ball pads on the bottom package for, and more particularly, to laminated relates to a multi-layer package using the lead frame formed with the lead frame, and the laminate when Huh is of the top package can be made accurately, a ball pad between relates to a multi-layer package using a lead frame to be easily implemented for fine pitch.

각종 전자 제품의 경량화, 소형화, 고속화, 다기능화, 고성능화 등을 만족시키기 위하여, 다양한 종류의 반도체 패키지가 제조되고 있는 바, 그 중 하나로서 패키지 위에 패키지를 쌓는 POP(Package On Package) 패키지 및 TMV(Through Mold Via)를 이용한 적층형 패키지 등이 제시되고 있다. In order to satisfy the weight of the various kinds of electronic products, size reduction, high-speed, multi-function, high performance and so on, (Package On Package) POP build a package on package bars it has been manufactured various types of semiconductor packages, as one of its package and TMV ( and the like multi-layer package using the Through Mold Via) is presented.

상기 POP 패키지는 메모리 디바이스인 상부 패키지와, 로직 디바이스(Logic device)인 하부 패키지가 서로 상하로 적층된 것으로서, 첨부한 9를 참조하여 그 구조를 간략하게 살펴보면 다음과 같다. POP as the package is an upper package and a lower package in a memory device, a logic device (Logic device) stacked on each other up and down, with reference to the accompanying 9. Referring to the structure briefly as follows.

상기 상부 패키지(100)는 제1기판(102)상에 실장된 제1반도체 칩(104)과; The top package 100 is a first semiconductor chip 104 mounted on the first substrate (102) and; 상기 제1기판(102)의 상면에 노출된 와이어 본딩용 전도성패턴(106)과 상기 제1반도체 칩(104)의 본딩패드간에 연결된 제1와이어(108)와; The first substrate 102, a first wire 108 connected between the bonding pads of the wire-bonding the conductive pattern 106 and the first semiconductor chip (104) for exposure on the upper surface of the; 상기 제1반도체 칩(104)과 제1와이어(108)를 포함하는 제1기판(102)의 상면 전체에 걸쳐 수지로 몰딩된 제1봉지체(110); The first semiconductor chip 104 and the first plug to the molding resin over the upper surface of the first substrate 102 including the first wire 108, 110; 로 구성되어 있으며, 이때 제1기판(102)의 저면에는 제1적층용 볼랜드(112)가 노출된 상태가 된다. Consists, at this time the lower surface of the first substrate 102 is a state which the first laminated Borland 112 for exposure.

상기 하부 패키지(200)는 제2기판(202)상에 실장된 제2반도체 칩(204)과; The bottom package 200 includes a second semiconductor chip 204 is mounted on the second substrate 202, and; 상기 제2기판(202)의 상면에 노출된 와이어 본딩용 전도성패턴(206)과 상기 제2반도체 칩(204)의 본딩패드간에 연결된 제2와이어(208)와; And a second wire 208 connected between the bonding pads of the second substrate 202. The wire bonding the conductive pattern 206 for exposing the upper surface of the second semiconductor chip (204); 상기 제2반도체 칩(204)과 제2와이어(208)를 포함하는 제2기판(202)의 상면에 걸쳐 수지로 몰딩된 제2봉지체(210); The second semiconductor chip 204 and the second the second plug 210 is molded with the resin over the upper surface of the second substrate 202 comprises a wire 208; 로 구성되며, 특히 상기 제2봉지체(210)의 외둘레면과 인접된 제2기판(202)의 상면에는 제2적층용 볼랜드(212)가 노출되고, 제2기판(202)의 저면에는 입출력단자용 볼랜드(214)가 노출되는 상태가 된다. Consists, in particular, the second upper surface of the plug 210, the outer circumference of the second substrate 202 close to the side of, the second laminated Borland 212 is exposed, the lower surface of the second substrate 202 has It is a state in which the Borland 214 for input and output terminals exposed.

따라서, 상기 하부패키지(200)의 제2기판(202)의 제2적층용 볼랜드(212)와, 상기 상부패키지(100)의 제1기판(102)의 제1적층용 볼랜드(112)간에 적층용 솔더볼(118)이 융착됨에 따라 상부 및 하부패키지(100,200)의 적층이 이루어지고, 상기 제2기판(202)의 입출력단자용 볼랜드(214)에 입출력용 솔더볼(222)이 융착됨에 따라 상부 및 하부 패키지(100,200)가 적층된 POP 패키지가 완성된다. Therefore, the laminated between the first layer Borland 112 for the first substrate 102 of the second laminated Borland 212, the top package 100 for the second substrate 202 of the lower package 200 as for the solder ball 118 is fused as above and a laminate of a lower package (100,200) is made, the second substrate 202 solder balls 222 for input and output is fused to Borland 214 for input and output of the top and the lower package (100,200) are stacked POP package is completed.

첨부한 도 10을 참조하면, 상기 TMV를 이용한 적층형 패키지도 상부 및 하부패키지(100,200)가 적층된 것으로서, 상부 패키지(100)는 제1기판(102)상에 실장된 제1반도체 칩(104)과; When attached to Figure 10, as the stacked-layer type packages with the TMV also the upper and lower package (100,200) laminated, the top package 100 includes a first semiconductor chip 104 mounted on the first substrate (102) and; 상기 제1기판(102)의 상면에 노출된 와이어 본딩용 전도성패턴(106)과 상기 제1반도체 칩(104)의 본딩패드간에 연결된 제1와이어(108)와; The first substrate 102, a first wire 108 connected between the bonding pads of the wire-bonding the conductive pattern 106 and the first semiconductor chip (104) for exposure on the upper surface of the; 상기 제1반도체 칩(104)과 제1와이어(108)를 포함하는 제1기판(102)의 상면 전체에 걸쳐 수지로 몰딩된 제1봉지체(110); The first semiconductor chip 104 and the first plug to the molding resin over the upper surface of the first substrate 102 including the first wire 108, 110; 로 구성되어 있으며, 이때 제1기판(102)의 저면에는 제1적층용 볼랜드(112)가 노출된 상태가 된다. Consists, at this time the lower surface of the first substrate 102 is a state which the first laminated Borland 112 for exposure.

상기 하부 패키지(200)는 제2기판(202)상에 실장된 제2반도체 칩(204)과; The bottom package 200 includes a second semiconductor chip 204 is mounted on the second substrate 202, and; 상기 제2기판(202)의 상면에 노출된 와이어 본딩용 전도성패턴(206)과 상기 제2반도체 칩(204)의 본딩패드간에 연결된 제2와이어(208)와; And a second wire 208 connected between the bonding pads of the second substrate 202. The wire bonding the conductive pattern 206 for exposing the upper surface of the second semiconductor chip (204); 상기 제2반도체 칩(204)의 외둘레면과 인접된 제2기판(202)의 상면에 형성되는 제2적층용 볼랜드(212)와; The second second laminated Borland 212 formed on the upper surface of the semiconductor chip 204, the outer circumference of the second substrate 202 close to the surface of the; 상기 제2반도체 칩(204)과 제2와이어(208), 그리고 제2적층용 볼랜드(212) 등을 포함하는 제2기판(202)의 상면 전체 면적에 걸쳐 수지로 몰딩된 제2봉지체(210); The second semiconductor chip 204 and the second wire 208, and the second laminated Borland 212 including a second molded with resin over the upper surface of the total area of ​​the second substrate 202, the rod including a for delay ( 210); 로 구성되며, 특히 상기 제2봉지체(210)에는 제2적층용 볼랜드(212)까지 레이저 가공에 의하여 관통되는 관통몰드비아(216)가 형성되고, 제2기판(202)의 저면에는 입출력단자용 볼랜드(214)가 노출되는 상태가 된다. Consists, in particular, the second plug 210, the second through the mold via 216 through by means of laser machining laminated to Borland 212 is formed, the bottom surface of the second substrate 202, the input-output terminal is a state in which the Borland 214 for exposure.

따라서, 상기 하부패키지(200)의 관통몰드비아(216)내로 노출된 제2적층용 볼랜드(212)와, 상기 상부패키지(100)의 제1기판(102)의 제1적층용 볼랜드(112)간에 적층용 솔더볼(118)이 융착됨에 따라 상부 및 하부패키지(100,200)의 적층이 이루어지고, 상기 제2기판(202)의 입출력단자용 볼랜드(214)에 입출력용 솔더볼(222)이 융착됨에 따라 상부 및 하부 패키지(100,200)가 적층된 TMV를 이용한 적층형 패키지가 완성된다. Thus, the through-mold via the second laminated Borland 212 exposed into the 216 of the lower package 200, the first lamination Borland 112 for the first substrate 102 of the top package 100 as between the stacked solder ball 118 is fused for as the upper and the lamination of the lower package (100,200) is made, the second substrate 202 solder balls 222 for input and output is fused to Borland 214 for input and output terminals of the the multi-layer package, the upper and lower package (100,200) using a stacked TMV is completed.

그러나, 상기한 POP 및 TMV를 이용한 적층형 패키지는 다음과 같은 문제점이 있다. However, the multi-layer package using the POP and the TMV has the following problems.

상기 POP 패키지의 경우, 하부패키지(200)의 제2기판(202)의 제2적층용 볼랜드(212)과, 상부패키지(100)의 제1기판(102)의 제1적층용 볼랜드(112)가 적층용 솔더볼(18)로 융착되는 바, 제1적층용 볼랜드(112)에 적층용 솔더볼(18)의 상단이 먼저 융착된 후, 이 적층용 솔더볼(18)의 하단부를 협소한 면적의 제2적층용 볼랜드(212)에 정확하게 맞추어(stand-off height) 융착시키는데 어려움이 있었다. The case of the POP package, the first layer Borland 112 for the bottom package 200, the second substrate 202, the second laminated Borland 212 and first substrate 102 of the top package 100, for the after the bar is welded to the laminate for solder ball 18, the the upper end of the laminated solder balls 18 for the Borland 112 for the first laminated first fusion, the the area of ​​the narrow lower ends of the laminate for solder balls 18 2 stacked Borland 212 accurately (stand-off height) fit for the fusion was sikineunde difficulties.

즉, 적층용 솔더볼(18)의 하단부를 제2적층용 볼랜드(212)에 솔더 리플로우 공정에 의하여 솔더링시키며 융착시킬 때, 적층용 솔더볼(18)의 하단부가 협소한 면적을 갖는 제2적층용 볼랜드(212)로부터 다소 벗어난 위치에 융착되는 미스 어라인 현상이 발생되는 문제점이 있었다. That is, for the second stack having an area the lower end of the narrower of the laminate for solder balls 18 the lower end of the second, multilayer solder ball (18) when the stack Borland 212 to soldering sikimyeo fused by solder reflow process of there is a problem in that this phenomenon occurs miss Huh is welded to the position slightly outside from Borland 212.

특히, 상기 제2적층용 볼랜드(212)들은 0.5mm 이하의 파인피치를 이루며 배열되어 있기 때문에 위와 같이 미스 어라인 현상이 발생되면, 적층용 솔더볼(18)끼리 접촉되는 쇼트 현상까지 발생될 소지가 있다. In particular, the second laminate for Borland 212 may otherwise be caused by short circuit phenomenon when the contact miss Huh phenomenon as above occurs because the array forms a fine pitch of 0.5mm or less, the laminated solder ball (18) with each other have.

한편, 상기 TMV를 이용한 적층형 패키지의 경우에는, 하부 패키지(200)의 제2기판(202)의 상면에 형성되는 제2적층용 볼랜드(212)를 0.4mm 이하의 파인피치로 구현하는데 어려움이 있다. On the other hand, in the case of the stacked-layer type packages with the TMV, the second laminated Borland 212 formed on the upper surface of the lower package, the second substrate 202 of (200) it is difficult to implement a fine pitch of 0.4mm or less .

본 발명은 상기와 같은 문제점을 해결하기 위하여 안출한 것으로서, 상부패키지의 솔더볼이 융착되는 하부패키지의 볼패드를 별도의 리드프레임을 기판에 부착시켜 형성해줌으로써, 적층용 솔더볼이 볼패드에 정확하게 맞추어(stand-off height)지며 융착될 수 있도록 한 리드프레임을 이용한 적층형 패키지를 제공하는데 목적이 있다. The invention to fit exactly to as one made in view, are formed by depositing a ball pads on the lower packages is the solder ball of the top package fusing a separate lead frame to the substrate may be formed by giving, the stacking solder balls, ball pads in order to solve the above problems ( becomes stand-off height) aims to provide a multi-layer package using a lead frame so as to be fused.

또한, 본 발명은 하부 패키지용 기판의 상면에 형성되는 적층용 볼랜드를 파인피치로 구현하고자, 기판의 상면에 하프에칭된 리드프레임을 미리 부착한 후, 하프에칭된 부분을 절단해줌으로써, 적층용 볼랜드의 파인피치를 용이하게 실현할 수 있도록 한 리드프레임을 이용한 적층형 패키지를 제공하는데 목적이 있다. The present invention is for then to implement a layered Borland for being formed on an upper surface of the substrate for the bottom package in fine pitch, previously attached to half-etching the lead frame on an upper surface of the substrate, by giving to cut the half-etched portion, the laminate It aims to provide a multi-layer package using a lead frame to be easily realize the fine pitch Borland.

상기한 목적을 달성하기 위한 본 발명의 일 구현예는: 스트립 단위 기판의 상면 중앙부가 몰딩된 하부패키지와, 이 하부패키지의 위에 상부패키지가 솔더볼에 의하여 적층되는 적층형 패키지로서, 상기 하부패키지용 스트립 단위 기판의 상면 테두리에 2열 이상의 볼패드를 형성하는 리드프레임이 부착되고, 상기 상부패키지의 솔더볼이 각 볼패드에 개별적으로 융착되도록 스트립 단위 기판이 개개의 패키지 단위로 소잉되는 소잉공정시, 상기 2열 이상의 볼패드도 독립적으로 분리되도록 한 것을 특징으로 하는 리드프레임을 이용한 적층형 패키지를 제공한다. In one embodiment of the present invention for achieving the above object comprises: an upper surface of a central portion is molded bottom package of a strip unit substrate and, as a multi-layer package is an upper package is laminated by solder balls on top of the bottom package, the strip for the bottom package when sawing process, the strip unit substrate that sawing units each package such that the lead frame to form a two-column or more ball pads attached to the upper surface edge of the unit substrate and, the solder ball of the top package individually welded to each ball pad, and the 2 provides a multi-layer package using the lead frame, it characterized in that the separation such that even independently heat or more ball pads.

본 발명의 일 구현예에서, 상기 리드프레임은 스트립 단위 기판의 소잉라인에 부착되어 소잉공정시 제거되는 사이드프레임과, 스트립 단위 기판의 칩부착영역의 외주부에 부착되는 2열 이상의 볼패드와, 사이드프레임과 각 볼패드를 일체로 연결하는 연결바로 구성된 것을 특징으로 한다. In one embodiment, the lead frame is attached to the sawing line of the strip unit substrate sawing and 2 columns or more ball pad attached to the outer peripheral part of the side frame and a chip attachment area of ​​the strip unit substrate is removed during the process, the side connection for connecting the frame and the respective ball pads integrally characterized in that just configured.

상기한 목적을 달성하기 위한 본 발명의 다른 구현예는: 스트립 단위 기판의 상면 전체가 몰딩된 하부패키지와, 이 하부패키지의 위에 상부패키지가 솔더볼에 의하여 적층되는 적층형 패키지로서, 하부패키지용 스트립 단위 기판의 상면에 2열 이상의 볼패드를 형성하는 리드프레임이 부착되고, 그 위쪽에 몰딩된 몰딩수지에 관통몰드비아를 형성하는 공정 및 상부패키지의 솔더볼이 각 볼패드에 개별적으로 융착되도록 스트립 단위 기판이 개개의 패키지 단위로 소잉되는 소잉공정시, 2열 이상의 볼패드도 독립적으로 분리되도록 한 것을 특징으로 하는 리드프레임을 이용한 적층형 패키지를 제공한다. Another embodiment of the present invention for achieving the above object comprises: a bottom package of the entire upper surface of the molding of the strip unit substrate, a multi-layer package is the top package on the top of the bottom package laminated by solder balls, the bottom package strip of general strip unit substrate and a second lead frame for forming a heat than ball pads on the upper surface of the substrate, the process and the solder ball of the top package for forming a through-mold via the mold resin molded on the top to be individually sealed by a respective ball pads this provides a multi-layer package using the lead frame during the sawing process is sawing into individual package units, characterized in that a separation such that even independently ball pads of two or more columns.

본 발명의 다른 구현예에서, 상기 리드프레임은 스트립 단위 기판의 소잉라인에 부착되어 소잉공정시 제거되는 사이드프레임과, 스트립 단위 기판의 칩부착영역의 외주부에 부착되어 관통몰드비아를 형성하는 공정시 서로 분리되는 2열 이상의 볼패드로 구성된 것을 특징으로 한다. In another embodiment of the invention, the lead frame is attached to the outer peripheral portion of the chip mounting area of ​​the side frame and the strip unit substrate that is removed when attached to the sawing line of the strip unit substrate sawing step during the process of forming the through-mold via characterized in that consists of two or more thermal ball pads are separated from one another.

바람직하게는, 상기 사이드프레임과 볼패드가 연결되는 부분의 저면과, 2열 이상의 볼패드가 연결되는 부분의 저면은 하프 에칭된 것을 특징으로 한다. Preferably, the bottom surface of the bottom portion of the side portion of the frame and a ball connection pads and, two or more thermal ball pads connection is characterized in that the half-etching.

상기한 과제 해결 수단을 통하여, 본 발명은 다음과 같은 효과를 제공한다. Through the above problem solving means, the present invention provides the following effects.

본 발명에 따르면, 하부패키지용 기판에 별도의 리드프레임을 부착하여 2열 이상의 볼패드를 형성해줌으로써, 상부패키지의 적층용 솔더볼이 볼패드에 정확하게 맞추어(stand-off height)지면서 융착될 수 있다. In accordance with the present invention, by giving to form a two-column or more ball pad is attached to a separate lead frame to the lower package substrate for, fit exactly in the laminate for the solder ball of the top package ball pad (stand-off height) As can be fused.

또한, 하부패키지용 기판의 상면에 하프에칭된 리드프레임을 미리 부착한 후, 관통몰드비아를 형성할 때 하프에칭된 부분을 절단하여, 2열 이상의 볼패드를 파인피치로 형성해줌으로써, 상부패키지의 적층용 솔더볼이 관통몰드비아를 통해 연결되는 볼패드를 0.4mm 이하의 파인피치를 용이하게 형성시킬 수 있다. Also, after pre-attaching a half-etching the lead frame on an upper surface for the lower package substrate, by giving to form a half-cut of the etched portion, two rows or more ball pads in forming the through-mold via a fine pitch, the upper package, the laminate for solder ball can be a pad, the ball is connected via the through-via-mold easily form a fine pitch of 0.4mm or less.

도 1은 본 발명에 따른 리드프레임을 이용한 적층형 패키지의 일 실시예를 나타내는 단면도, 1 is a cross-sectional view illustrating one embodiment of a multi-layer package using a lead frame according to the invention,
도 2는 본 발명에 따른 리드프레임을 이용한 적층형 패키지의 일 실시예를 나타내는 평면도, Figure 2 is a plan view of one embodiment of a multi-layer package using a lead frame according to the invention,
도 3은 본 발명에 따른 리드프레임을 이용한 적층형 패키지의 일 실시예를 나타내는 소잉후의 단면도, 3 is a cross-sectional view after the sawing illustrating one embodiment of a multi-layer package using a lead frame according to the invention,
도 4는 본 발명의 일 실시예에 따른 리드프레임을 이용한 적층형 패키지로서 상부패키지가 적층된 것을 나타내는 단면도, 4 is a sectional view showing that the upper package is stacked as a multi-layer package using a lead frame according to one embodiment of the invention,
도 5는 본 발명에 따른 리드프레임을 이용한 적층형 패키지의 다른 실시예를 나타내는 단면도, 5 is a cross-sectional view showing another embodiment of the multi-layer package using a lead frame according to the invention,
도 6은 본 발명에 따른 리드프레임을 이용한 적층형 패키지의 다른 실시예를 나타내는 평면도, 6 is a plan view showing another embodiment of the multi-layer package using a lead frame according to the invention,
도 7은 본 발명에 따른 리드프레임을 이용한 적층형 패키지의 다른 실시예를 나타내는 소잉후의 단면도, Figure 7 is a cross-sectional view after the sawing of another embodiment of the multi-layer package using a lead frame according to the invention,
도 8은 본 발명의 다른 실시예에 따른 리드프레임을 이용한 적층형 패키지로서 상부패키지가 적층된 것을 나타내는 단면도, Figure 8 is a cross-sectional view showing that the upper package is stacked as a multi-layer package using a lead frame according to another embodiment of the present invention,
도 9 및 도 10은 종래의 적층형 패키지를 나타내는 단면도. 9 and 10 are cross-sectional views showing a conventional multi-layer package.

이하, 본 발명의 바람직한 실시예를 첨부도면을 참조로 상세하게 설명하기로 한다. Hereinafter in detail with reference to the accompanying drawings a preferred embodiment of the present invention will be described.

첨부한 도 1 내지 도 3은 본 발명에 따른 리드프레임을 이용한 적층형 패키지의 일 실시예를 나타내는 도면이고, 도 4는 본 발명의 일 실시예에 따른 리드프레임을 이용한 적층형 패키지로서 상부패키지가 적층된 것을 나타내는 단면도이다. FIG attached 1 to 3 is a view showing an example of a multi-layer package using a lead frame according to the invention, Figure 4 is an upper package stacked as multi-layer package using a lead frame according to an embodiment of the present invention a cross-sectional view showing the.

본 발명의 일 실시예에 따른 적층형 패키지는 하부패키지를 구성하고 있는 기판에 리드프레임을 이용한 볼패드를 형성한 점에 특징이 있다. The stacked package in accordance with one embodiment of the present invention is characterized in that the formation of the pad viewed using a lead frame to the substrate constituting the bottom package.

본 발명의 일 실시예에 따른 하부 패키지(20)는 기판(21)상에 실장된 반도체 칩(22)과; The lower package 20 in accordance with one embodiment of the present invention comprises a semiconductor chip 22 mounted on the substrate 21; 상기 기판(21)의 상면에 노출된 와이어 본딩용 전도성패턴(23)과 상기 반도체 칩(22)의 본딩패드간에 연결된 와이어(24)와; And a wire 24 connected between a bonding pad for wire bonding the conductive pattern 23 and the semiconductor chip (22) exposed to the upper surface of the substrate 21; 상기 반도체 칩(22)과 와이어(24)를 포함하는 기판(21)의 상면 중앙부에 걸쳐 몰딩수지로 몰딩된 봉지체(25); A plug molded with the molding resin over the upper surface of the central portion of the substrate 21 including the semiconductor chip 22 and the wires 24 and 25; 로 구성되고, 상기 제2봉지체(25)의 외둘레면과 인접된 기판(21)의 상면에는 적층용 볼랜드(26)가 노출되고, 기판(21)의 저면에는 입출력단자용 볼랜드(27)가 노출되는 상태가 된다. Consists of, the second upper surface of the plug 25. The base plate 21 adjacent to the outer circumferential surface of, the laminated Borland (26) is exposed, the substrate 21, a bottom surface, the Borland 27 for input and output terminals of the It is in a state that is exposed.

여기서, 상기 하부패키지(20)의 기판(21) 즉, 여러개의 반도체 패키지가 한꺼번에 제조될 수 있도록 한 스트립 단위 기판(21)의 상면 테두리 영역에 2열 이상의 볼패드를 형성하는 리드프레임(30)을 부착하게 된다. Here, the lead frame 30 to form the substrate 21. That is, the upper surface border area of ​​two or more columns of a strip unit substrate (21) so that several of the semiconductor package can be manufactured at a time to view the pad of the lower package 20 a is attached.

상기 리드프레임(30)은 스트립 단위 기판(21)의 각 소잉라인에 부착되어 소잉공정시 제거되는 사각틀 형상의 사이드프레임(32)과, 스트립 단위 기판(21)의 칩부착영역의 외주부영역에 부착되는 2열 이상의 직사각형 볼패드(34)와, 상기 사이드프레임(32)과 각 볼패드(34)를 일체로 연결하되 독립적으로 연결하면서 기판(21)상에 함께 부착되는 연결바(36)로 구성된다. The lead frame 30 is attached to the outer periphery region of the chip attachment area of ​​the strip unit substrate 21, the side frame 32, the strip unit board 21 is attached to each sawing line of a rectangular frame shape that is removed during the sawing step of composed of a connecting bar 36 and the two rows or more rectangular ball pads 34 are, but connected to the side frame 32 and each ball pads 34 is integrally attached with the substrate 21 and connected independently do.

이때, 상기 볼패드(34)는 기판(21)의 적층용 볼랜드(26)와 일대일로 대응되며 도전 가능하게 접착되는 상태가 된다. At this time, the ball pads 34 is the state in which the adhesive is conductive to enable one-to-one correspondence with the stack Borland (26) of the substrate (21).

상기 스트립 단위 기판(21)에는 개개의 하부패키지로 분리하는 소잉공정시, 소잉이 이루어지는 소잉라인이 형성되는 바, 이 소잉라인을 따라 블레이드에 의한 소잉이 진행되면, 상기 리드프레임(30)의 사이드프레임(32)이 함께 소잉되어 제거되고, 이에 2열 이상의 볼패드(34)는 서로 분리된 상태가 된다. The strip unit substrate 21, when the sawing of the blade according to the individual during the sawing process for separating a bottom package, a bar which sawing takes place sawing line is formed, the sawing line proceeds, the side of the lead frame 30 and ERASE 32 is sawing with, and thus two or more thermal ball pads 34 is the separated state each other.

한편, 상기 하부패키지(20)의 위쪽에 솔더볼(12)에 의하여 상부패키지(10)가 적층되는 바, 상부패키지(10)의 기판(14) 저면에 융착된 솔더볼(12)의 하단부가 상기와 같이 개별적으로 분리된 각 볼패드(34)에 리플로우 공정에 의한 솔더링에 의하여 용이하게 융착되어진다. On the other hand, the lower end portion of the solder ball 12 is fused on the bottom substrate 14 of the lower package 20 bar, the top package 10 by the top of the solder ball 12 to be the top package (10) laminated to the above as is it is easily fused by individually for each ball pads 34 separated by soldering by the reflow process.

이렇게 상기 하부패키지(20)의 볼패드(34)를 리드프레임을 이용하여 직사각형 면적을 갖는 구조로 형성해줌에 따라, 상부패키지(10)의 솔더볼(12)이 각 볼패드(34)에 정확하게 맞추어(stand-off height)지면서 용이하게 융착될 수 있다. So depending on the form the ball pads 34 of the lower package 20 to the structure using a lead frame having a rectangular area haejum, the solder balls 12 of the upper package 10 to fit exactly in the respective ball pads 34 (stand-off height) as can be easily fused.

첨부한 도 5 내지 도 7은 본 발명에 따른 리드프레임을 이용한 적층형 패키지의 다른 실시예를 나타내는 도면이고, 도 8은 본 발명의 다른 실시예에 따른 리드프레임을 이용한 적층형 패키지로서 상부패키지가 적층된 것을 나타내는 단면도이다. FIG attached 5 to 7 is a view showing another embodiment of the multi-layer package using a lead frame according to the invention, Figure 8 is an upper package stacked as multi-layer package using a lead frame according to another embodiment of the present invention a cross-sectional view showing the.

본 발명의 다른 실시예에 따른 적층형 패키지는 하부패키지를 구성하고 있는 기판에 리드프레임을 이용한 볼패드를 파인피치로 형성한 점에 특징이 있다. The stacked package in accordance with another embodiment of the present invention is characterized in a point forms the pad viewed using a lead frame to the substrate constituting the bottom package in fine pitch.

본 발명의 다른 실시예에 따른 하부 패키지(20)는 기판(21)상에 실장된 제2반도체 칩(22)과; The lower package 20 according to another embodiment of the present invention and the second semiconductor chip 22 is mounted on a substrate 21; 상기 기판(21)의 상면에 노출된 와이어 본딩용 전도성패턴(23)과 상기 반도체 칩(22)의 본딩패드간에 연결된 와이어(24)와; And a wire 24 connected between a bonding pad for wire bonding the conductive pattern 23 and the semiconductor chip (22) exposed to the upper surface of the substrate 21; 반도체 칩(22)의 외둘레면과 인접된 기판(21)의 상면에 형성되는 적층용 볼랜드(26)와; Laminated Borland (26) formed on the top of the substrate 21 adjacent to the outer circumferential surface of the semiconductor chip 22 and the; 반도체 칩(22)과 와이어(24), 그리고 적층용 볼랜드(26) 등을 포함하는 기판(21)의 상면 전체 면적에 걸쳐 수지로 몰딩된 봉지체(25); A semiconductor chip (22) and a plug of a resin molding over the entire area of ​​the upper surface of the substrate 21 including the wire 24, and the laminated Borland (26) (25); 로 구성되며, 특히 상기 봉지체(25)에는 적층용 볼랜드(26)까지 레이저 가공에 의하여 관통되는 관통몰드비아(28)가 형성되고, 기판(21)의 저면에는 입출력단자용 볼랜드(27)가 노출되는 상태가 된다. Consists, in particular, the plug 25 has a bottom surface, the Borland 27 for input and output terminals of the laminated Borland 26 laser through the mold via 28 is formed and a substrate 21 on which the through by the processing up for a It is in a state exposed.

여기서, 상기 하부패키지(20)의 기판(21) 즉, 여러개의 반도체 패키지가 한꺼번에 제조될 수 있도록 한 스트립 단위 기판(21)의 상면 테두리 영역에 2열 이상의 볼패드를 파인피치로 형성하는 리드프레임(30)을 부착하게 된다. Here, the lead frame to form the substrate 21. That is, a number of second heat than ball pads on the upper surface of the border area of ​​a strip unit substrate 21 so that the semiconductor package can be produced at a time of the lower package 20 to the fine pitch It is attached (30).

상기 리드프레임(30)은 스트립 단위 기판(21)의 소잉라인에 부착되어 소잉공정시 제거되는 사이드프레임(32)과, 스트립 단위 기판(21)의 칩부착영역의 외주부에 부착되어 관통몰드비아를 형성하는 공정시 서로 분리되는 2열 이상의 볼패드(34)로 구성되는 바, 상기 사이드프레임(32)과 볼패드(34)의 외측단이 연결되는 부분의 저면과, 2열 이상의 볼패드가 서로 분리 가능하게 연결되는 부분의 저면은 하프 에칭을 하여, 사이드프레임(32)과 볼패드(34)간의 분리, 그리고 볼패드(34)의 간의 분리가 용이하게 이루어질 수 있도록 한다. The lead frame 30 is affixed to the sawing line of the strip unit board 21 is attached to the outer peripheral portion of the chip mounting area of ​​the side frame 32 and a strip unit substrate 21 to be removed during the sawing process, the through-mold via consisting of a step when two rows or more ball pads 34 are separated from one another to form a bar, the bottom surface of the portion that the outer end of the side frame 32 and a ball pad (34) connected to, a second column over ball pads to each other the bottom surface of the part to be detachably connected by a half-etching, so that the side frame 32 and the separation between the ball pad 34, and a ball separation between the pads 34 can be easily performed.

물론, 상기 볼패드(34)는 기판(21)의 적층용 볼랜드(26)와 일대일로 대응되며 도전 가능하게 접착되는 상태가 된다. Of course, the ball pads 34 is the state in which the adhesive is conductive to enable one-to-one correspondence with the stack Borland (26) of the substrate (21).

상기 스트립 단위 기판(21)에는 개개의 하부패키지로 분리하는 소잉공정시, 소잉이 이루어지는 소잉라인이 형성되는 바, 이 소잉라인을 따라 블레이드에 의한 소잉이 진행되면, 상기 리드프레임(30)의 사이드프레임(32)이 함께 소잉되어 제거되고, 이에 사이드프레임(32)과 볼패드(34)는 서로 분리된 상태가 된다. The strip unit substrate 21, when the sawing of the blade according to the individual during the sawing process for separating a bottom package, a bar which sawing takes place sawing line is formed, the sawing line proceeds, the side of the lead frame 30 and frame 32 are removed by sawing together, whereby the side frame 32 and the ball pad (34) is a separate condition from each other.

또한, 상기 하부패키지(20)의 몰딩수지 즉, 봉지체(25)에 관통몰드비아(28)를 레이저 가공에 의하여 형성하는 공정시, 또는 상기와 같은 소잉 공정시 봉지체(25) 및 그 아래쪽의 볼패드(34)간을 연결하고 있는 하프에칭된 부분을 절단해줌으로써, 볼패드(34)는 파인피치를 이루는 서로 분리되어 2열 이상의 독립된 배열을 이루게 된다. In addition, the molding resin of the lower package 20. That is, the step during which formed by a through-mold via 28 in the laser processing in the plug (25), or sawing process when the plug 25 and the bottom, such as the of ball pads 34 is half-etched, cut off portion by giving the ball pads 34 that are connected to the liver are separated from each other forming a fine pitch are formed to separate the array of two or more columns.

이때, 서로 분리된 볼패드(34)는 관통몰드비아(28)와 상하 일치되어 관통몰드비아(28)를 통해 노출되는 상태가 된다. At this time, the ball pads 34 are separated from each other in keeping the upper and lower molds and the through via 28 is in a state that is exposed through the through-mold via 28.

한편, 상기 하부패키지(20)의 위쪽에 솔더볼(12)에 의하여 상부패키지(10)가 적층되는 바, 상기와 같이 개별적으로 분리된 각 볼패드(34)에 상부패키지(10)의 기판(14) 저면에 융착된 솔더볼(12)의 하단부가 리플로우 공정에 의한 솔더링에 의하여 용이하게 융착되어진다. On the other hand, a substrate (14 of the upper package 10 to each ball pads 34 a by the top of the solder ball 12, the top package 10 are laminated bar, the individually separated as described above that of the lower package 20 ) is the lower end of the solder ball 12 is welded to the bottom surface is sealed to facilitate, by soldering by the reflow process.

이와 같이, 상기 하부패키지(20)의 볼패드(34)를 리드프레임을 이용하여 0.4mm 이하의 파인피치로 형성해주고, 관통몰드비아(28)를 통해 노출된 각 볼패드(34)에 상부패키지(10)의 솔더볼(12)을 안정적으로 적층 부착시킬 수 있다. In this way, by using a lead frame, a ball pads 34 of the lower package 20 haejugo formed with fine pitch of 0.4mm or less, an upper package in each ball pad 34 exposed through the through-mold via 28 the laminate can be stably attached to the solder balls 12 of 10.

10: 상부패키지 12 : 솔더볼 10: Top 12 Package: solder balls,
14 : 상부패키지의 기판 20 : 하부패키지 14: substrate 20 of the package top: bottom package
21 : 하부패키지의 기판 22 : 반도체 칩 21: substrate 22 of the lower package: a semiconductor chip
23 : 전도성패턴 24 : 와이어 23: conductive pattern 24: wire
25 : 봉지체 26 : 적층용 볼랜드 25: plug 26: laminate for Borland
27 : 입출력단자용 볼랜드 28 : 관통몰드비아 27: Borland for input-output terminal 28: through-mold via
30 : 리드프레임 32 : 사이드프레임 30: lead frame 32: the side frame
34 : 볼패드 36 : 연결바 34: 36 pads see: Connecting bars

Claims (5)

  1. 스트립 단위 기판(21)의 상면 중앙부가 몰딩된 하부패키지(20)와, 이 하부패키지(20)의 위에 상부패키지(10)가 솔더볼(12)에 의하여 적층되는 적층형 패키지로서, 상기 하부패키지용 스트립 단위 기판(21)의 상면 테두리에 2열 이상의 볼패드(34)를 형성하는 리드프레임(30)이 부착되고, 상기 상부패키지(10)의 솔더볼(12)이 각 볼패드(34)에 개별적으로 융착되도록 스트립 단위 기판(21)이 개개의 패키지 단위로 소잉되는 소잉공정시, 상기 2열 이상의 볼패드(34)도 독립적으로 분리되도록 한 것을 특징으로 하는 리드프레임을 이용한 적층형 패키지. Strip unit substrate of the lower package 20 has an upper surface central part molding 21, a multi-layer package is an upper package 10 is laminated by solder balls (12) on top of a lower package (20), the strip for the bottom package on the upper surface edge of the unit substrate 21, second lead frame 30 to form a heat than ball pad 34 is attached, the solder balls 12 of the top package (10) individually to each ball pads 34 the multi-layer package strip unit substrate 21 such that the fusing with the lead frame, characterized in that the sawing step so that also separated independently when the two or more thermal ball pads 34 is sawing into individual package units.
  2. 청구항 1에 있어서, 상기 리드프레임(30)은, The method according to claim 1, wherein the lead frame (30),
    스트립 단위 기판(21)의 소잉라인에 부착되어 소잉공정시 제거되는 사이드프레임(32)과, 스트립 단위 기판(21)의 칩부착영역의 외주부에 부착되는 2열 이상의 볼패드(34)와, 사이드프레임(32)과 각 볼패드(34)를 일체로 연결하는 연결바(36)로 구성된 것을 특징으로 하는 리드프레임을 이용한 적층형 패키지. And it is attached to the sawing line of the strip unit substrate 21 sawing process when removing the side frames 32, the strip unit substrate 2 columns or more ball pads 34 attached to the outer peripheral portion of the chip mounting area 21 on which, side frame 32 and the multi-layer package using the lead frame, characterized in that consisting of a connecting bar (36) connecting each ball pad 34 as one body.
  3. 스트립 단위 기판(21)의 상면 전체가 몰딩된 하부패키지(20)와, 이 하부패키지(20)의 위에 상부패키지(10)가 솔더볼(12)에 의하여 적층되는 적층형 패키지로서, 하부패키지용 스트립 단위 기판(21)의 상면에 2열 이상의 볼패드(34)를 형성하는 리드프레임(30)이 부착되고, 그 위쪽에 몰딩된 몰딩수지인 봉지체(25)에 관통몰드비아(28)를 형성하는 공정 및 상부패키지(10)의 솔더볼(12)이 각 볼패드에 개별적으로 융착되도록 스트립 단위 기판(21)이 개개의 패키지 단위로 소잉되는 소잉공정시, 2열 이상의 볼패드(34)도 서로 독립적으로 분리되도록 한 것을 특징으로 하는 리드프레임을 이용한 적층형 패키지. Strip unit substrate overall the lower package 20 molding the top surface of 21 and, as a multi-layer package is an upper package 10 is laminated by solder balls (12) on top of the lower package 20, the bottom package strip of general the lead frame 30 to form a second row or more ball pads 34 on the upper surface of the substrate 21 is attached, to form a through-mold via 28 in the plug 25, the molded resin molding to the top process and the solder ball 12, the process when, 2 columns or more ball pads 34 sawing that sawing of a strip unit substrate 21, the unit of the individual packages to be individually welded to each ball pads of the upper package 10 is also independent of each other multi-layer package using the lead frame, characterized in that the so separated.
  4. 청구항 3에 있어서, 상기 리드프레임(30)은, The method according to claim 3, wherein the lead frame (30),
    스트립 단위 기판(21)의 소잉라인에 부착되어 소잉공정시 제거되는 사이드프레임(32)과, 스트립 단위 기판(21)의 칩부착영역의 외주부에 부착되어 관통몰드비아(28)를 형성하는 공정시 서로 분리되는 2열 이상의 볼패드(34)로 구성된 것을 특징으로 하는 리드프레임을 이용한 적층형 패키지. Is attached to the sawing line of the strip unit substrate 21 sawing process when attached to the outer peripheral portion of the chip mounting area of ​​the side frame 32 and a strip unit substrate 21 on which the removal process during forming the through-mold via 28 multi-layer package using the lead frame, characterized in that consists of two or more thermal ball pads 34 are separated from one another.
  5. 청구항 4에 있어서, The method according to claim 4,
    상기 사이드프레임(32)과 볼패드(34)가 연결되는 부분의 저면과, 2열 이상의 볼패드(34)가 연결되는 부분의 저면은 하프 에칭된 것을 특징으로 하는 리드프레임을 이용한 적층형 패키지. The bottom surface of the portion of the side frame 32 and the ball pad 34 and a bottom surface, two or more thermal ball pads 34 of the portion connected to the connection multi-layer package using the lead frame, characterized in that the half-etching.
KR20100052117A 2010-06-03 2010-06-03 Stack package using lead frame KR101151257B1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020065737A (en) * 2001-02-07 2002-08-14 주식회사 칩팩코리아 Structure of lead frame for fabricating semiconductor package
US6674156B1 (en) 2001-02-09 2004-01-06 National Semiconductor Corporation Multiple row fine pitch leadless leadframe package with use of half-etch process
KR20080007893A (en) * 2006-07-18 2008-01-23 삼성전자주식회사 Stack type semiconductor package and method of fabricating the same
US7662672B2 (en) 2006-10-13 2010-02-16 Chipmos Technologies (Bermuda) Ltd. Manufacturing process of leadframe-based BGA packages

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020065737A (en) * 2001-02-07 2002-08-14 주식회사 칩팩코리아 Structure of lead frame for fabricating semiconductor package
US6674156B1 (en) 2001-02-09 2004-01-06 National Semiconductor Corporation Multiple row fine pitch leadless leadframe package with use of half-etch process
KR20080007893A (en) * 2006-07-18 2008-01-23 삼성전자주식회사 Stack type semiconductor package and method of fabricating the same
US7662672B2 (en) 2006-10-13 2010-02-16 Chipmos Technologies (Bermuda) Ltd. Manufacturing process of leadframe-based BGA packages

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