KR101131919B1 - Memory system and signal transmitting and receiving method of the same - Google Patents

Abstract

The present invention discloses a memory system and a method of transmitting and receiving a signal thereof. The system includes a memory controller, and first and second memory modules for transmitting and receiving data to and from the memory controller, each of the first and second memory modules having a first memory and a second memory, wherein the first memory includes: The control signal applied from the memory controller is relayed to the second memory, and the second memory receives read data output from the first memory and outputs the read data to the memory controller, and the control signal output from the memory controller is controlled through the control signal line. Transferring the first and second memory modules to the first memory in common, transferring read data output from the second memory of the first memory module to the memory controller through the first lead data line, and The read data output from the second memory may be transmitted to the memory controller through the second lead data line. Thus, the loading of the signal transmission line is reduced to enable high speed data transmission.

Description

Memory system and signal transmission and reception method of the same

Fig. 1 shows the configuration of a conventional memory system.

Fig. 2 shows the construction of the first embodiment of the memory system of the present invention.

Fig. 3 shows the data format of the embodiment to be transmitted in write data, command and address signal lines of the memory system of the present invention.

4 is an operation timing diagram when the memory control unit transmits a signal having the data format B of FIG. 3 at a double data rate. FIG. 5 is a configuration of an embodiment inside the first memory and the second memory shown in FIG. To indicate.

6A and 6B are operation timing diagrams for explaining the read operation of the first memory and the read operation of the second memory of the first and second memory modules of the memory system of the present invention shown in FIG.

Fig. 7 shows the construction of the second embodiment of the memory system of the present invention.

Fig. 8 shows the construction of the third embodiment of the memory system of the present invention.

The present invention relates to a memory system and a signal transmission / reception method thereof.

A general memory system includes a memory controller and memory modules, and stores data in the memory modules under the control of the memory controller, and reads the data stored in the memory modules.

1 illustrates a configuration of a conventional memory system, and includes a memory controller 10 and memory modules 20-1 and 20-2, and each of the memory modules 20-1 and 20-2. Is composed of memories M1 to Mn. In FIG. 1, connection tabs TAP are disposed at lower portions of each of the memory modules 20-1 and 20-2 to be inserted into respective slots (not shown) disposed on a board of the memory system.

A connection structure of the memory system shown in FIG. 1 will now be described.

The first command and address signal lines C / A1 are disposed between the memory control unit 10 and the memory module 20-1, and the second command is between the memory control unit 10 and the memory module 20-2. And address signal lines C / A2 are disposed. Data lines DQ1 to DQn shared between the memory controller 10 and the memory modules 20-1 and 20-2 are disposed.

A data transfer method of the memory system shown in FIG. 1 will now be described.

When data is input and output between the memory control unit 10 and the memory module 20-1, the memory control unit 10 sends the first command and address signal lines C / A1 to the memory module 20-1. A command and an address are applied through the data line, and data is input and output to / from the memories M1 to Mn of the memory module 20-1 through the data lines DQ1 to DQn.

When data is input and output between the memory control unit 10 and the memory module 20-2, the memory control unit 10 sends the second command and address signal lines C / A2 to the memory module 20-2. Commands and addresses are applied through the data lines, and data is input and output to / from the memories M1 to Mn of the memory module 20-2 through the data lines DQ1 to DQn.

In the conventional memory system illustrated in FIG. 1, when the number of memories included in one memory module is n, n memories are commonly connected to each of the command and address signal lines C / A1 and C / A2. Therefore, the line loading of the command and address signal lines C / A1 and C / A2 is increased. In addition, in the conventional memory system, when two memory modules are provided, the memory of each of the memory modules, that is, the lines of the data lines DQ1 to DQn because the two memories share the data lines DQ1 to DQn. The loading will increase. As the loading of the signal transmission line increases, it acts as a factor that delays the signal during signal transmission, which is not suitable for a high speed memory system.

An object of the present invention is to provide a memory system that enables high-speed data transmission by reducing the loading of signal transmission lines.

Another object of the present invention is to provide a signal transmission / reception method of a memory system for achieving the above object.

A first aspect of the memory system of the present invention for achieving the above object comprises a memory controller, and first and second memory modules for transmitting and receiving data with the memory controller, each of the first and second memory modules And a first memory and a second memory, wherein the first memory relays a control signal applied from the memory controller to the second memory, and the second memory stores read data output from the first memory. Inputting and outputting the control signal to the memory control unit, and commonly transmitting the control signal from the memory control unit to the first memory of the first and second memory modules through a control signal line; The read data output from the second memory is transmitted to the memory controller through a first lead data line, and the second memory And the read data output from the second memory of the module characterized in that the transfer to the memory controller via the second read data lines.

In an embodiment, the first memory and the second memory may be disposed on the same surface of each board of the memory modules. In another embodiment, each of the memory modules includes a plurality of the first memory and the second memory, and the plurality of first memory and the plurality of second memories are disposed on both sides of a board of the memory module. And arranged on the same surface of both surfaces of the board of the memory module.

The control signal line may be arranged on the board of the system from the memory controller to the first memory module and extended to the second memory module. In another exemplary embodiment, the control signal line may be arranged on the board of the system to a branch point, and branched from the branch point to the first memory module and the second memory module.

The control signal line, the first lead data line and the second lead data line are disposed on a board of the system, and one side of the first memory module is connected to the control signal line and the first lead data line. The control signal transmitted through the control signal line is transmitted to the first memory and the other side of the first memory module of the first memory module, and one side of the second memory module is connected to the second lead data line. And the control signal transmitted through the other side of the first memory module is transmitted through the other side of the second memory module. The memory system may further include a connection unit. And the other side of the second memory module.

The first memory includes a first repeater for outputting a control signal applied from the memory control unit to the second memory, and the second memory inputs read data output from the first memory to control the second memory control unit. It characterized in that it comprises a second repeater for outputting.

A second aspect of the memory system of the present invention for achieving the above object comprises a memory controller, and first and second memory modules for transmitting and receiving data with the memory controller, wherein the first memory module is at least two first And a second memory module having at least two second memories, wherein the at least two first memories input a control signal applied from the memory control unit and output the control signals to the at least two second memories. And the at least two second memories input read data output from the at least two first memories and output the read data to the memory controller, wherein the control signal output from the memory controller is controlled through a control signal line. Applying in common to said at least two first memories of modules, said at least two of said first memory modules Read data output from the first memory are respectively transmitted to the at least two second memories of the second memory module through a first lead data line, and output from each of the at least two second memories of the second memory module. The second read data is transmitted to the memory controller through the second read data line.

In example embodiments, the first memory may be disposed on the same surface of the board of the first memory module, and the second memory may be disposed on the same surface of the second memory module. In another embodiment, the first memory module includes a plurality of first memories, the second memory module includes a plurality of second memories, and the plurality of first memories includes a plurality of first memories of a board of the first memory module. Arranged on both sides and disposed on the same side of the both sides of the first memory module, and the plurality of second memories are arranged separately on both sides of the board of the second memory module and the same of both sides of the second memory module It is arrange | positioned on the surface.

The control signal line is disposed on a board of the system, characterized in that the control signal transmitted through the control signal line is commonly applied to the at least two first memory on the surface of the first memory module. .

The first lead data line and the second lead data line are arranged on a board of the system.

One side of the first memory module is connected to the control signal line, and the control signal transmitted through the control signal line is commonly applied to the at least two first memories of the first memory module, and the at least two Control signals output from the first memory modules are transmitted to the other side of the first memory module, and one side of the second memory module is connected to the first lead data line and the second lead data line, and the first memory The control signal output through the other side of the module is transmitted to the at least two second memory of the second memory module through the other side of the second memory module, the memory system further comprises a connection means The other side of the first memory module and the other side of the second memory module are connected.

The at least two first memories include a first repeater for inputting a control signal applied from the memory controller and outputting the control signal to the at least two second memories, wherein the at least two second memories include the at least two first memories. And a second repeater for inputting read data output from the memory and outputting the read data to the memory controller.

The control signal of the first and second types of memory systems includes a command signal, an address signal, write data, and an identification signal, wherein the identification signal is determined whether the control signal is a signal related to the first memory or a second memory. Characterized in that it is a related signal, characterized in that the control signal is transmitted serially by a predetermined bit through a predetermined number of the control signal line.

A first aspect of a signal transmission / reception method of a memory system of the present invention for achieving the another object includes a memory controller, and first and second memory modules for transmitting and receiving data with the memory controller, wherein the first and second memory modules are provided. A data transmission method of a memory system in which each of the memory modules includes a first memory and a second memory, wherein the memory controller transmits the control signal to the first memory of each of the modules in common when the control signal is transmitted. The first memory of each of the modules transmits the control signal to the second memory of the corresponding module, and when read data is output from the first memory of each of the modules at the time of read data transmission, A first memory transfers read data to the second memory of the module, and the second memory exits from the first memory of the module Outputting read data to the memory controller, and when read data is output from the second memory of each of the modules, read data output from the second memory of each of the modules is transmitted to the memory controller. do.

A second aspect of the signal transmission and reception method of the memory system of the present invention for achieving the above another object comprises a memory control unit, and first and second memory modules for transmitting and receiving data with the memory control unit, the first memory module A data transfer method of a memory system having at least two first memories, and wherein the second memory module includes at least two second memories, wherein the memory control unit is configured to transmit the control signal to the first memory module. Transmitting control signals to at least two first memories in common, wherein the at least two first memories of the first memory module transmit the control signals to the at least two second memories of the second memory module, respectively; When the read data is output from the first memory during read data transfer, the at least two first memos of the first memory module. Transmit read data to the at least two second memories of the second memory module, respectively, and the read data output from the at least two second memories by the at least two second memories of the second memory module, respectively. And transmitting read data output from the at least two second memories to the memory controller when the read data is output from the at least two second memories of the second memory module. .

The control signal of the first and second types of signal transmission and reception methods includes a command signal, an address signal, write data, and an identification signal, wherein the identification signal is a signal related to the first memory or a second memory. The control signal is serially transmitted by a predetermined bit through a predetermined number of the control signal and the write data line.

Hereinafter, referring to the accompanying drawings, a memory system and a signal transmitting / receiving method of the present invention will be described.

FIG. 2 shows a configuration of a first embodiment of a memory system of the present invention, which is comprised of a memory controller 100 and memory modules 200-1 and 200-2, and memory modules 200-1 and 200-. 2) Each is composed of memory pairs (M11, M12) to (M (n / 2) 1, M (n / 2) 2) including a first memory and a second memory. 20-1 and 20-2, a lower portion of each of the plurality of slots (not shown) is inserted into each of the slots (not shown) disposed on the board of the memory system is connected to the tab (TAP) is disposed.

A connection structure of the memory system shown in FIG. 2 will now be described.

Write data, command, and address signal lines of the first to (n / 2) th groups between the memory controller 100 and each of the memory modules 200-1 and 200-2 (WD / C / A1). WD / C / A (n / 2)) has a point-to-point connection structure, and read data lines between the memory controller 100 and each of the memory modules 200-1 and 200-2. RD1 to RDn have a point-to-point connection structure. The write data, command, and address signal lines WD / C / A1 to WD / C / A of the first group to the (n / 2) group between the memory controller 100 and the memory module 200-1 ( n / 2)), and the signal lines WD / C / A1 to WD / C / A (n / 2) extend to the memory module 200-2. Odd-numbered read data lines RD1 to RD (n-1) are disposed between the memory controller 100 and the memory module 200-1, and between the memory controller 100 and the memory module 200-2. Even-numbered read data lines RD2 to RDn are disposed.

A signal transmission method of the memory system shown in FIG. 2 will now be described.

In Fig. 2, each write to the first memories M11 to M (n / 2) 1 of each of the memory pairs (M11, M12) to (M (n / 2) 1, M (n / 2) 2). When write data, command, and address signals are applied through the data, command, and address signal lines WD / C / A1 to WD / C / A (n / 2), the first memory M11 to M (n / 2) 1) Each of the write data, command, and address signals is input and relayed to the corresponding second memories M12 to M (n / 2) 2 through the internal repeater R. The memory pairs (( The second memories M12 to M (n / 2) 2 of each of M11 and M12 to M (n / 2) 1 and M (n / 2) 2 correspond to the corresponding first memories M11 to M (n). 2) Input read data output from 1) and output to the corresponding read data lines RD1 to RDn through the internal repeater R. Although not shown, the memory pairs (M11 and M12) to When write data, command and address signals are applied to the first memories M11 to M (n / 2) 1 of each of the M (n / 2) 1 and M (n / 2) 2, the first memory M11 To Each M (n / 2) 1 may input write data, command, and address signals as they are without the repeater R, or may be input through the repeater R.

After a write command is applied from the memory controller 100, a memory cell array (not shown) of the first memories M11 to M (n / 2) 1 and the second memories M12 to M (n / 2) 2. If the data is to be written to the memory cell array (not shown) at the same time, a delay element may be added to the first memories M11 to M (n / 2) 1.

Although not shown, read data output from the second memories M12 to M (n / 2) 2 may be output through the internal repeater R or may be output to the outside as it is. In any case, after a read command is applied from the memory controller 100 to the first memories M11 to M (n / 2) 1, the reads output from the first memories M11 to M (n / 2) 1 are read. The timing at which the data is output to the corresponding read data line and the timing at which the read data output from the second memories M12 to M (n / 2) 2 are output to the corresponding read data line may be the same. To this end, a delay element may be added to the second memories M12 to M (n / 2) 2.

The memory system of the present invention shown in FIG. 2 can reduce line loading because write data, command, and address signal lines are commonly connected to two memories, and read data lines are connected to one memory. Referring to the memory system shown in FIG. 2 in comparison with the conventional memory system shown in FIG. 1, the write data, command, and address signal lines of the memory system shown in FIG. Are connected to one memory, but the command and address signal lines of the conventional memory system shown in FIG. 1 are commonly connected to n memories, and data lines are commonly connected to two memories. Thus, it can be seen that the line loading of the signal transmission line can be reduced as compared with the conventional memory system shown in FIG.

In the memory system of FIG. 2, n groups of write data, command, and address signal lines WD / C / A1 to WD / C / An are written to the write data lines, command signal lines, and addresses for each group. Separate signal lines. In this case, when the number of write data lines, command signal lines, and address signal lines increases, the number of signal lines arranged on the system board increases. Thus, a signal in the form of a packet may be transmitted using a predetermined number of signal lines without separately separating the write data lines, the command signal lines, and the signal lines for applying the address signal lines of the n groups. have.

Figure 3 illustrates the packet format of an embodiment transmitted in write data, command and address signal lines of the memory system of the present invention.

In Fig. 3, A denotes an active command format, where the active command format consists of one packet data consisting of an identification signal 1, a command signal, and a row address signal, and the identification signal 1 is composed of two memory modules 200-. 1 and 20-2) may be composed of one bit of data for distinguishing whether the instruction is for the first memory or the second memory. The command signal may consist of predetermined bits for specifying an active command. For example, when the command signal consists of an inverting chip select signal, an inverted write enable signal, an inverted column address strobe signal, and an inverted row address strobe signal, the command signal may include four bits of data. The row address signal is a signal for selecting a word line (not shown) of a memory cell array (not shown) of the first or second memory. When the memory cell array is composed of a plurality of banks, the row address signal is banked together with the row address signal. The address signals may be applied together.

B denotes a write command format, wherein the write command format is composed of three packet data, the first packet data is composed of an identification signal 1, a command signal, and a column address signal, and the second packet data and the third packet data. Is composed of the identification signal 2 and the write data. The identification signal 1 is data for distinguishing the first memory from the second memory and may be formed of 1 bit. The identification signal 2 is data for distinguishing the memory module 200-1 and the memory module 200-2 and may be formed of 1 bit. The write data is write data stored in the memory module 200-1 when the identification symbol 2 designates the memory module 200-1, and write data is stored in the memory module 200-2 when the memory module 200-2 is designated. The write data is stored. Therefore, even though write data to be stored in the memory module 200-1 and write data to be stored in the memory module 200-2 are transmitted together, the memory of the memory module 200-1 and the memory of the memory module 200-2 are identified. The write data may be distinguished using the signal 1 and the identification signal 2. The column address is a signal for specifying a column select signal line (not shown) of the memory cell array of the first or second memory, and the bit line (not shown) of the memory cell array is selected by specifying the column select signal line. .

In the above-described embodiment, the case where the write command format is composed of three packet data is shown. However, when the number of bits of the write data is small, the write command format may be composed of two packet data.

C denotes a read command format. The read command format is composed of one packet data, like the active command format, and is composed of an identification symbol 1, a command signal, and a column address signal.

When the write command format of B is applied, write data is written to a memory cell connected between the selected word line and the selected bit line of the memory cell array. When the read command format of C is applied, the selected word line and the selected word line of the memory cell array are selected. Data stored in memory cells (not shown) connected between bit lines is read.

FIG. 4 is an operation timing diagram when the memory controller transmits a signal having the data format B of FIG. 3 at a double data rate, and includes write data, command and address signal lines WD / C / A1 to WD / C. / An) shows an operation timing diagram when six lines are configured.

In FIG. 4, in the period T1, the memory controller 100 first transmits the identification signal 1 and the command signal together with the clock signal CLK, and in the period T2, transmits the column address signal, and in the period T3. The identification symbol 2 and the write data are transmitted, and the identification symbol 2 and the write data are transmitted in the period T4. Here, transmitting at a double data rate means transmitting data in response to the rising edge and the falling edge of the clock signal CLK.

As shown in Fig. 4, when the write data, the command signal, and the address signal are transmitted through a predetermined number of identical lines, the number of write data lines, command signal lines, and address signal lines is reduced. Accordingly, the memory system of the present invention has an additional advantage that the loading of the signal lines is reduced as well as the number of signal lines arranged on the system board is reduced.

FIG. 5 shows the configuration of the embodiment inside the first memory and the second memory shown in FIG. 2, wherein the first memory M11 is a repeater composed of an input buffer B1, an internal circuit 50, and a buffer B2. The second memory M12 is composed of R and an output buffer B3, and the second memory M12 is a repeater R composed of input buffers B4 and B6, an internal circuit 52, an output buffer B5, and a buffer B7. It consists of).

An operation in which the write data, the command, and the address signal wd / c / a1 applied to the first memory M11 are transmitted to the second memory M12 will be described below.

The write data, command and address signal wd / c / a1 applied to the first memory M11 is buffered by the input buffer B1 and the buffer B2, and the buffered write data, command and address signal rwd / c / a). The write data, command and address signals iwd / c / a1 buffered by the input buffer B1 are also applied to the internal circuit 50 of the first memory M11. The buffered write data, command, and address signals rwd / c / a applied to the second memory M12 are buffered by the input buffer B4 and buffered write data, command, and address signals (iwd / c / a2). Will occur). That is, the write data, the command and the address signal wd / c / a1 applied to the first memory M11 are applied to the internal circuit 50 through the input buffer B1 and at the same time through the repeater R. It is also output to the memory M12.

When output data dout1 is generated from the internal circuit 50 of the first memory M11, the output data dout1 is buffered by the output buffer B3 to generate the buffered output data DO1. The buffered output data DO1 is applied to the second memory M12, and the buffered output data DO1 applied to the second memory M12 is buffered through the input buffer B6 and the buffer B7. Generates data DO2. The output data dout1 generated from the internal circuit 52 of the second memory M12 is buffered by the output buffer B5 to generate the buffered output data DO2. The buffered output data DO2 is transmitted to the memory controller 100 through the read data line RD1. When a read operation is performed on the first memory M11 to generate output data DO1 buffered from the first memory M11, the output buffers B3 and the second memory M12 of the first memory M11 may be generated. The data is output to the read data line RD1 through the input buffer B6 and the repeater R, and a read operation is performed on the second memory M12 to output data from the internal circuit 52 of the second memory M12. When dout2 is generated, it is output to the read data line RD1 through the output buffer B5. Since the read operation is performed only in one of the first memory M11 and the second memory M12, a data collision between the output data of the output buffer B5 and the output data of the repeater R does not occur.

The other memory pairs (M21, M22) to (Mn1, Mn2) composed of the first memory and the second memory also have the configuration of the first memory and the second memory of FIG. 5 and perform the same operation.

FIG. 6A is a timing diagram illustrating the read operation of the first memory of the first and second memory modules of the memory system of FIG. 2, and FIG. 6B is an operation timing diagram for explaining the read operation of the second memory. / a1 indicates write data, command and address signals input to the first memory, rwd / c / a indicates ride data commands and address signals output from the first memory, and DO1 indicates read data output from the first memory. DO2 represents read data output from the second memory.

Referring to FIG. 6A, the read data format C of FIG. 3 is converted into the first memory M11 of the first memory module 200-1 and the first memory M21 of the second memory module 200-2. And a signal (wd / c / a1) in which the identification signal 1 designates a read operation for the first memory is applied, the first memories M11 and M21 read in response to the signal wd / c / a1. An operation is performed to output read data DO1 after a delay by the read latency period Tr.

In addition, the first memories M11 and M21 respectively input signals wd / c / a1 and delay the delay time Tp to generate signals rwd / c / a, respectively. M12 and M22 input signals rwd / c / a, respectively, so that the signal rwd / c / a is a read command to the first memories M11 and M21, and thus does not perform a read operation. The read data DO1 output from the memories M11 and M21 are respectively input and delayed by the delay time Tp to output the read data DO2.

Referring to FIG. 6B, the read data format C of FIG. 3 is converted into the first memory M11 of the first memory module 200-1 and the first memory M21 of the second memory module 200-2. And a signal (wd / c / a1) indicating that the identification signal 1 specifies a read operation for the second memory is applied, the first memories (M11, M21) store this signal (wd / c / a1) as a delay time ( Delays by Tp to generate the signals rwd / c / a, respectively, and the first memories M11 and M21 perform read operations because the signals wd / c / a1 are not read commands to the first memory. Do not do it. Since the signals rwd / c / a are read commands for the second memory, the second memories M12 and M22 generate the read data DO2 after a delay by the read latency period Tr since the read operation is performed. .

In Figs. 6A and 6B, the delay time Tp is the time taken to pass through the buffer B1 and the repeater R in the first memories if each of the first and second memories is configured as shown in Fig. 5; The time taken to pass the buffer B6 and the repeater R in the two memories.

Therefore, when write data, a command, and an address are applied to the first memories of the first and second memory modules 200-1. Write data and commands to the first memories of the first and second memory modules 200-1 and 200-2 during the time until the read data DO2 is output and during the read operation with respect to the second memories. And the time until the read data DO2 is output from the second memories after the address is applied is the same.

FIG. 7 shows a configuration of a second embodiment of a memory system of the present invention, which is comprised of a memory controller 100, memory modules 200-1 ′, 200-2 ′, and a connection board 300. Each of the modules 200-1 ′, 200-2 ′ is a memory pair (M11, M12) to (M (n / 2) 1, M (n / 2) 2).

In FIG. 7, a lower portion of each of the memory modules 200-1 ′ and 200-2 ′ is a portion inserted into each of slots (not shown) disposed on a board of the memory system, and connection tabs TAP are disposed. Connection tabs TAP are disposed on each of the memory modules 200-1 ′ and 200-2 ′, and connectors (not shown) disposed on left and right sides of the connection board 300 are inserted.

In the memory system illustrated in FIG. 7, the write data, command and address signal lines WD / C / A1 to WD / C / An have a first memory module 200-1 ′ and a second memory module 200 on a system board. Write data, command, and address signal lines WD / C / A1 to WD / C / An are branched on the board of the first memory module 200-1 '. It is connected to the second memory module 200-2 ′ through lines arranged on the connection board 300. The lines branched on the board of the first memory module 200-1 ′ are connected to the connection tabs disposed on the upper portion of the first memory module 200-1 ′, and through the lines arranged on the connection board 300. It is connected to the connection tab disposed on the upper portion of the second memory module 200-2 '. From the first memory module 200-1' to the second memory module 200-2 'on the connection board 300. Lines for transmitting the transmitted signal are arranged. The memory system shown in Fig. 7 can also reduce line loading like the memory system shown in Fig. 2 because two memories are connected to the write data, command and address signal lines and one memory is connected to the read data lines. have.

Since the data transfer method of the memory system shown in FIG. 7 is the same as the data transfer method of the memory system of FIG. 2 described above, it will be easily understood with reference to the description of FIG.

FIG. 8 shows a configuration of a third embodiment of a memory system of the present invention, which is comprised of a memory controller 100, memory modules 200-1 ", 200-2", and a connection board 300 '. The memory module 200-1 ″ is composed of first memories M11 to Mn1, and the memory module 200-2 ″ is composed of second memories M12 to Mn2.

In FIG. 8, a lower portion of each of the memory modules 200-1 "and 200-2" is inserted into each of slots (not shown) disposed on a board of a memory system, and connection tabs TAP are disposed. Connection tabs TAP are disposed on each of the memory modules 200-1 ″ and 200-2 ″, and inserted into a connector (not shown) disposed above and below the connection board 300 ′. In the memory system shown in FIG. 8, write data, command, and address signal lines WD / C / A1 to WD / C / An are disposed on a system board, so that the first memory of the first memory module 200-1 " (M11 to Mn1) and the first memories (M11 to Mn1) repeat the write data, the command and the address signal by the internal repeater R and output the first memory module 200-1. Write data, command, and address signals output from the first memories M11 to Mn1 of "" are transferred to the second memories M12 of the second memory module 200-2 through lines on the connection board 300 '. ~ Mn2. Also, read data output from the first memories M11 to Mn1 of the first memory module 200-1 ″ is transmitted through the lines on the connection board 300 ′. Is applied to the second memories M12 to Mn2 of the second memory module 200-2 ". The read data output from the second memories M12 to Mn2 of the second memory module 200-2" is a system. It is transmitted through the read data lines RD1 to RDn arranged on the board. Signals transmitted from the first memory module 200-1 ″ to the second memory module 200-2 ″ are connected to connection tabs disposed above the memory module 200-1 ″, and connected to the connection board 300 ′. ) Are connected to the connection tabs disposed above the memory module 200-2 ″. As a result, a signal, a write data, a command and an address signal, and a first memory transmitted from the first memory module 200-1 ″ to the second memory module 200-2 ″ are connected on the connection board 300 ′. Lines for transmitting read data output from M11 to Mn1 are arranged.

The memory system shown in FIG. 8 can also reduce line loading like the memory system shown in FIG. 2 because two memories are connected to the write data, command and address signal lines, and one memory is connected to the read data lines. have.

Since the data transfer method of the memory system shown in FIG. 8 is the same as the data transfer method of the memory system of FIG. 2 described above, it will be easily understood with reference to the description of FIG.

In the above-described embodiments, the memories disposed in the memory modules are shown to be arranged in the plane of one side of the board, but in some cases, some memories are arranged in the plane of one side and the remaining memories in the plane of the other side. You may arrange.

In addition, in the above-described embodiments, the connection boards 300 and 300 'may be in the form of cables rather than boards. That is, it does not matter what form is configured if data can be transferred between the memory modules.

In the above-described embodiment, a memory system having two memory modules has been described as an example, but it is possible to apply the method of the present invention to a memory system having three or more memory modules.

In the memory system of the embodiments of FIGS. 2 and 6 described above, memory modules are arranged horizontally, one close to the other and far away from the memory controller, but the memory modules are positioned at the same position from the memory control. It may be arranged arranged vertically. In this case, write data, command and address signal lines for transferring write data, command and address signals from the memory control section to the branch point are arranged, and write data, command and address signal lines extend from the branch point to the first memory module. The write data, command and address signal lines may be extended from the branch point to the second memory module.

In the above-described embodiments, the first memory module and the second memory module have been described as being inserted into slots not shown on the system board. However, as shown in the drawing, the first memory module and the second memory module are inserted onto the system board without slots. It may be configured by soldering directly to. In addition, although the connection boards of FIGS. 7 and 8 are provided with connectors not shown, the connection tabs of the first memory module and the second memory module are connected to each other. However, as shown in FIG. 2 may be directly soldered to the memory module.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand that you can.

The memory system of the present invention and the method of transmitting and receiving signals of the system enable high-speed signal transmission by minimizing delay that may occur in signal transmission by reducing line loading of signal transmission lines.

In addition, the memory system of the present invention and the method for transmitting and receiving signals of the system do not constitute write data, command and address signals as many signal lines as the number of bits of these signals, and are much smaller than the number of bits of these signals. In this case, the serial transmission through these signal lines reduces the number of signal lines arranged on the system board, thereby simplifying signal placement on the board.

Claims (26)

A memory controller; And First and second memory modules for transmitting and receiving data with the memory control unit, Each of the first and second memory modules And a first memory and a second memory, the first memory outputs a control signal applied from the memory controller to the second memory, and the second memory inputs read data output from the first memory. Output to the memory controller, The control signal output from the memory controller is commonly transmitted to the first memory of the first and second memory modules through a control signal line, and the read data output from the second memory of the first memory module is transferred. Transfer the read data output from the second memory of the second memory module to the memory controller through a first lead data line, The control signal line, the first lead data line and the second lead data line are disposed on a board of a system, One side of the first memory module is connected to the control signal line and the first lead data line, and the control signal transmitted through the control signal line includes the first memory and the first memory of the first memory module. Sent to the other side of the module, One side of the second memory module is connected to the second lead data line, characterized in that the control signal transmitted through the other side of the first memory module is transmitted through the other side of the second memory module. Memory system. The method of claim 1, wherein the first memory and the second memory The memory system of claim 1, wherein the memory modules are disposed on the same surface of each board. The memory module of claim 1, wherein each of the memory modules A plurality of first and second memories, And arranging the plurality of first memories and the plurality of second memories on both sides of a board of the memory module and on the same side of the both sides of a board of the memory module. The method of claim 1, wherein the control signal line is A memory system arranged on the board of the system from the memory controller to the first memory module, and extended to the second memory module. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 1, wherein the control signal line is And a branch point on the board of the system and branched from the branch point to the first memory module and the second memory module. The method of claim 1, wherein the control signal is Including command signals, address signals, write data, and identification signals, And the identification signal indicates whether the control signal is a signal related to a first memory or a signal related to a second memory. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 6, wherein the control signal And a predetermined number of bits are serially transmitted through a predetermined number of the control signal lines. delete The system of claim 1, wherein the memory system is Further comprising a connecting means, And connecting the other side of the first memory module with the other side of the second memory module. The memory device of claim 1, wherein the first memory includes a repeater that inputs a control signal applied from the memory controller and outputs the control signal to the second memory. And the second memory includes a repeater for inputting read data output from the first memory and outputting the read data to the memory controller. A memory controller; And First and second memory modules for transmitting and receiving data with the memory control unit, The first memory module includes at least two first memories, and the second memory module includes at least two second memories. The at least two first memories input control signals applied from the memory control unit to be output to the at least two second memories, and the at least two second memories are read data output from the at least two first memories. Input to output to the memory controller, The control signal output from the memory controller is commonly applied to the at least two first memories of the first memory modules through a control signal line, and is output from the at least two first memories of the first memory module. Transfer read data to the at least two second memories of the second memory module through a first read data line, and output second read data output from each of the at least two second memories of the second memory module. And transmitting to the memory controller through a second lead data line. Claim 12 was abandoned upon payment of a registration fee. 12. The memory system of claim 11, wherein the first memory is disposed on the same surface of the board of the first memory module, and the second memory is disposed on the same surface of the second memory module. Claim 13 was abandoned upon payment of a registration fee. The method of claim 11, wherein the first memory module includes a plurality of first memories, and the second memory module includes a plurality of second memories. The plurality of first memories may be divided on both sides of the board of the first memory module and disposed on the same surface of the both sides of the first memory module, and the plurality of second memories may be arranged on the board of the second memory module. The memory system of claim 2, wherein the memory system is disposed on both sides of the second memory module and disposed on the same side of the two sides of the second memory module. Claim 14 was abandoned when the registration fee was paid. The method of claim 11, wherein the control signal line is Placed on the board of the system, And the control signal transmitted through the control signal line is commonly applied to the at least two first memories on the surface of the first memory module. Claim 15 was abandoned upon payment of a registration fee. And a memory system arranged on the board of the system. Claim 16 has been abandoned due to the setting registration fee. The memory device of claim 11, wherein one side of the first memory module is connected to the control signal line, and the control signal transmitted through the control signal line is common to the at least two first memories of the first memory module. The control signal is applied and output from the at least two first memory is transmitted to the other side of the first memory module, One side of the second memory module is connected to the first lead data line and the second lead data line, and the control signal outputted through the other side of the first memory module is controlled through the other side of the second memory module. And the at least two second memories of the second memory module. Claim 17 has been abandoned due to the setting registration fee. The system of claim 16, wherein the memory system is Further comprising a connecting means, And connecting the other side of the first memory module with the other side of the second memory module. Claim 18 was abandoned upon payment of a set-up fee. The method of claim 11, wherein the control signal is Including command signals, address signals, write data, and identification signals, And the identification signal indicates whether the control signal is a signal related to a first memory or a signal related to a second memory. Claim 19 was abandoned upon payment of a registration fee. 19. The method of claim 18, wherein the control signal is And a predetermined number of bits are serially transmitted through a predetermined number of the control signal lines. Claim 20 was abandoned upon payment of a registration fee. 12. The apparatus of claim 11, wherein the at least two first memories each include a repeater for inputting the control signal applied from the memory control unit and outputting the control signal to the at least two second memories. And a repeater for inputting read data output from the at least two first memories and outputting the read data to the memory controller. A memory controller; And In the data transfer method of the memory system comprising a first memory module and a second memory module for transmitting and receiving data to and from the memory control unit, each of the first and second memory modules comprises a first memory and a second memory, When the control signal is transmitted, the memory control unit commonly transmits the control signal to the first memory of each of the modules, the first memory of each of the modules transmits the control signal to the second memory of the corresponding module, When read data is output from the first memory of each of the modules during read data transmission, the first memory of each of the modules transfers read data to the second memory of the corresponding module, and the second memory corresponds to the corresponding memory. The read data output from the first memory of the module is transmitted to the memory controller, and when read data is output from the second memory of each of the modules, the read data output from the second memory of each of the modules is stored in the memory. To the control unit, One side of the first memory module is connected to a control signal line and a first lead data line, and the control signal transmitted through the control signal line is connected to the first memory and the first memory module of the first memory module. Sent to the other side, One side of the second memory module is connected to a second lead data line, characterized in that the control signal transmitted through the other side of the first memory module is transmitted through the other side of the second memory module. Signal transmission and reception method of a memory system. Claim 22 is abandoned in setting registration fee. The method of claim 21, wherein the control signal is Including command signals, address signals, write data, and identification signals, And the identification signal indicates whether the control signal is a signal related to a first memory or a signal related to a second memory. Claim 23 was abandoned upon payment of a set-up fee. The method of claim 22, wherein the control signal is The signal transmission and reception method of the memory system, characterized in that the serial transmission by a predetermined number of bits through the control signal line. A memory controller; And First and second memory modules configured to transmit and receive data to and from the memory controller, wherein the first memory module includes at least two first memories, and the second memory module includes at least two second memories. In the data transfer method of the memory system, When the control signal is transmitted, the memory control unit commonly transmits a control signal to the at least two first memories of the first memory module, and the at least two first memories of the first memory module are the second memory module. Respectively transmitting the control signals to the at least two second memories of When read data is output from the first memory during read data transmission, the at least two first memories of the first memory module transmit read data to the at least two second memories of the second memory module, respectively. The at least two second memories of the second memory module respectively transmit read data output from the at least two second memories to the memory controller, and read from the at least two second memories of the second memory module. And transmitting the read data output from the at least two second memories to the memory controller, when data is output. Claim 25 is abandoned in setting registration fee. The method of claim 24, wherein the control signal is Including command signals, address signals, write data, and identification signals, And the identification signal indicates whether the control signal is a signal related to a first memory or a signal related to a second memory. Claim 26 is abandoned in setting registration fee. The method of claim 25, wherein the control signal The signal transmission and reception method of the memory system, characterized in that the serial transmission by a predetermined number of bits through the control signal line.

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