KR101091844B1 - Flash memory system scanning bad block fast and bad bolck managing method thereof - Google Patents

Abstract

A memory system according to the present invention includes a flash memory device having a first address section and a second address section, and configured to exchange a block address of a bad block belonging to the first address section with a block address of the second address section; And a memory controller configured to control the flash memory device to retrieve bad block information of memory blocks belonging to the second address period and to output the selected bad block information. Through the above configurations, the flash memory system of the present invention can retrieve the bad block address at high speed.

Description

Flash memory system that searches for bad blocks at high speed, and how to manage bad blocks thereof {FLASH MEMORY SYSTEM SCANNING BAD BLOCK FAST AND BAD BOLCK MANAGING METHOD THEREOF}

1 shows a scanning sequence of a typical bad block;

2 is a block diagram schematically showing a flash memory system of the present invention;

3 is a view showing an example of distribution of bad blocks included in a flash memory device according to the present invention;

4 is a flow chart showing one embodiment of a method for retrieving the bad blocks of FIG.

5 is a flow chart showing another embodiment of a method for retrieving the bad blocks of FIG.

6 illustrates another example of distribution of bad blocks of a flash memory device according to the present invention;

7 is a flow chart showing a method for retrieving the bad blocks of FIG.

8A is a flow chart showing one embodiment of FIG. 7;

8B is a flowchart showing another embodiment of FIG. 7;

9 is a block diagram illustrating a mobile system including a memory system according to the present invention.

* Description of the symbols for the main parts of the drawings *

110: flash memory device 120: memory controller

210: flash memory system 220: power supply

230: processing unit 240: ram

250: user interface

The present invention relates to a semiconductor memory device, and more particularly to a flash memory device and a setting method thereof.

Semiconductor memory devices are largely classified into volatile semiconductor memory devices and non-volatile semiconductor memory devices. The volatile semiconductor memory device has a high reading and writing speed, but the stored content disappears when the external power supply is cut off. On the other hand, nonvolatile semiconductor memory devices retain their contents even when the external power supply is interrupted. Therefore, the nonvolatile semiconductor memory device is used to store contents to be preserved regardless of whether or not power is supplied. Non-volatile semiconductor memory devices include mask read-only memory (MROM), programmable read-only memory (PROM), erasable and programmable ROM (EROM), and electrically Electrically erasable programmable read-only memory (EEPROM).

In general, MROMs, PROMs, and EPROMs are not free to erase and write on the system itself, making it difficult for ordinary users to update their contents. In contrast, since EEPROMs can be electrically erased and written, applications to system programming or auxiliary storage devices that require continuous updating are expanding. In particular, the flash EEPROM has a higher density than the conventional EEPROM, which is very advantageous for application to a large capacity auxiliary storage device. Among the flash EEPROMs, the NAND-type flash EEPROM (hereinafter, referred to as 'NAND flash memory') has an advantage of having a higher density than other flash EEPROMs.

Generally, flash memory devices are integrated circuits that can store information and read information when desired. The flash memory device includes a plurality of rewritable memory cells. Each of the memory cells stores one-bit data or multi-bit data. Flash memory devices are becoming increasingly functional through high integration, high capacity, and increasing chip size. However, according to the above-described trends, the circuit line width of the flash memory device is reduced, the process is increased, and the complexity is increased. These conditions are causing the chip yield to decrease. In order to solve this problem, a flash memory device includes a redundant memory cell (hereinafter, referred to as a redundant memory cell) for replacing a defective memory cell. The flash memory device also includes means for converting an address of a defective cell into an address of a redundant memory cell. If a bad block in which a defect is present in the test is detected, the bad block is replaced with a redundant block without a defect. According to the processing of this bad block, the flash memory device in which the bad block exists can be released in good quality.

However, the number of redundant blocks included in one flash memory device is limited and cannot be excluded even when the number of detected bad blocks exceeds the number of redundant blocks. In such a case, the producer may inform the user of the allowable range of the number of bad blocks not repaired from the beginning, and supply a flash memory device including the unrepaired bad blocks. In this case, in order to block the selection of the bad block, the controller or the user must search for the location of the bad block. Hereinafter, the "bad block" refers to a block in which the aforementioned non-repaired defects exist.

1 is a diagram schematically illustrating an address map of a memory block of a flash memory device. Referring to FIG. 1, memory blocks of a flash memory device at power-up are searched from a memory block MB0 to a final memory block MB2047. Check data indicating whether a bad block or a normal block is present in any one area of each memory block. The check data is read through the search and the bad block of the found memory block is determined by referring to the read check data. Through such a search, information on bad blocks of the flash memory device may be provided to the outside of the memory device.

Techniques for processing the above bad blocks are described in US Patent No. 6,956,769 " SEMICONDUCTOR MEMORY DEVICE WITH A FLEXIBLE REDUNDANCY SCHEME , which is described in Korean Patent Laid-Open Publication No. 1998-0026248, entitled " Semiconductor Memory Device with Automatic Defect Block Mapping Function, " and is incorporated by reference in this application.

According to the techniques described above, information about bad blocks that are not repaired in the manner described in FIG. 1 must be provided to the user or the controller during the power-up operation. The user or the controller configures an address mapping table with reference to the bad block address provided from the flash memory device. In order to construct an address mapping table for blocking access to unrepaired bad blocks in advance, all memory blocks of the flash memory device must be searched. In order to search all the memory blocks of the flash memory device and construct an address mapping table, the time required for booting the flash memory device or the memory system becomes long. An extended boot time is a factor that degrades the performance of the memory system.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems, and to provide a flash memory system and a bad block management method thereof capable of performing a fast search of a bad block.

In accordance with another aspect of the present invention, a memory system includes a first address section and a second address section, and exchanges a block address of a bad block belonging to the first address section with a block address of the second address section. A flash memory device configured to be; And a memory controller configured to control the flash memory device to retrieve bad block information of memory blocks belonging to the second address period and to output the selected bad block information.

In this embodiment, the block address of the bad block is preferentially exchanged with the last block address of the normal blocks of the second address period.

In this embodiment, the memory controller searches for all memory blocks corresponding to the second address section in the initialization operation of the flash memory device.

In this embodiment, the memory controller sequentially searches the second address section, but searches only up to the block address where the bad block information corresponding to the bad block is searched first.

In this embodiment, the memory controller recognizes the address of the memory block in which the bad block information is searched and the upper addresses of the searched address as the address of the bad block.

In this embodiment, the second address section includes a plurality of preliminary address sections each having a contiguous block address section.

In this embodiment, each of the plurality of preliminary address periods includes a block address of bad blocks.

In this embodiment, the memory controller searches for all memory blocks corresponding to the plurality of spare address intervals.

In this embodiment, the memory controller searches each of the plurality of preliminary address periods, but searches only up to the block address where the bad block information corresponding to the bad block is searched for the first time.

The bad block management method of the flash memory system according to the present invention for achieving the above object has a first address section and a second address section, and the block address of the bad block belonging to the first address section is the second address section. Providing a flash memory device configured to exchange with a block address of a; And controlling the flash memory device to retrieve bad block information of memory blocks belonging to the second address period and to output the retrieved bad block information.

In this embodiment, in the providing of the flash memory device, the block address of the bad block is preferentially exchanged with the last block address among the normal blocks of the second address period.

In the present embodiment, the controlling of the flash memory device may include: (a) setting a block address for selecting memory blocks included in the second address period, wherein a start address is the lowest address of the second address period; Initializing with; (b) reading bad block information indicating whether the block is bad from the memory block corresponding to the set block address, and determining whether the memory block corresponding to the set block address is a bad block by referring to the read bad block information; Making; And (c) if the bad block information indicates a normal block, adding the block address to a valid block table.

In this embodiment, in step (c), when the bad block information indicates that the bad block, the block address is added to the bad block table.

In this exemplary embodiment, the method may further include, after step (c), determining whether the address of the memory block to be searched is the last block of the second address section.

In this embodiment, in the step (d), if the address of the memory block is not the last block of the second address interval, the block address is counted up to select a memory block subsequent to the block address and the (e) moving to step (b).

In this embodiment, when the bad block information indicates that the bad block information is a bad block in step (c), the block address of the memory block in which the bad block information is searched and the upper block addresses of the searched address are added to the bad block table. .

In this embodiment, the second address section includes a plurality of preliminary address sections each having a contiguous block address section.

In this embodiment, each of the plurality of preliminary address periods includes a block address of bad blocks.

In this embodiment, the operations according to steps (a) to (c) are performed for each of the plurality of spare block address periods.

An information device for achieving the above object includes a memory card; And a computing system for exchanging data with the memory card, wherein the memory card has a first address section and a second address section, wherein the block address of the bad block belonging to the first address section is assigned to the second address. A flash memory device configured to be exchanged with a block address of a section; And a memory controller configured to control the flash memory device to retrieve bad block information of memory blocks belonging to the second address period and to output the selected bad block information.

According to the memory system and the bad block management method according to the present invention, the bad block of the flash memory device can be searched quickly from the outside. Accordingly, the present invention can provide a memory system capable of fast booting.

It is to be understood that both the foregoing general description and the following detailed description are exemplary, and that additional explanations of the claimed invention are provided. Reference numerals are shown in detail in preferred embodiments of the invention, examples of which are shown in the reference figures. In any case, like reference numerals are used in the description and the drawings to refer to the same or like parts.

In the following, a NAND type flash memory device is used as an example for explaining the features and functions of the present invention. However, one of ordinary skill in the art will readily appreciate the other advantages and performances of the present invention in accordance with the teachings herein. The present invention may be implemented or applied through other embodiments. In addition, the detailed description may be modified or changed according to aspects and applications without departing from the scope, technical spirit and other objects of the present invention. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram illustrating a memory system 100 according to the present invention. Referring to FIG. 2, the flash memory system 100 includes a flash memory device 110 and a memory controller 120 for storing a large amount of data. The flash memory device 110 of the present invention remaps a block address so that unrepaired bad blocks are continuously located in a specific address range. In addition, the memory controller 120 searches only some memory blocks included in the flash memory device 110 to search all bad blocks of the flash memory device 110.

The block address of the flash memory device 110 is remapped so that the block addresses of the bad blocks are contiguous to a specific address range. In order to remap the block address, a spare address section for exchanging the block addresses of the bad blocks should be designated. The reserved address section will hereinafter be referred to as a reserved block range. The spare block range is a block address section in which normal blocks are distributed. For example, when 32 memory blocks are allocated to the spare block range among all the blocks of the flash memory device, they may be address ranges corresponding to 16 consecutive memory blocks corresponding to the last block address. Alternatively, two spaced apart address intervals including sixteen memory blocks each having a contiguous block address may be selected as a spare block range. That is, when remapping block addresses, the bad blocks included in the flash memory device 110 exchange a block address with a normal memory block included in a spare block range. In this case, the block addresses of the memory blocks corresponding to the spare block range are remapped so that the block addresses of the bad blocks are continuous. Therefore, after remapping, the bad blocks included in the flash memory device 110 are continuously distributed within the spare block range.

The memory controller 120 controls the flash memory device 110 to read or write data stored in the flash memory device 110 in response to a read / write request of the host. The memory controller 120 must construct an address mapping table for mapping an address provided from a host (mobile device or computer system) to a physical address of the flash memory device 110. In this case, the memory controller 120 should have physical address information on the bad block in order to block a write or read operation to the bad block. Therefore, the memory controller 120 searches for the location of the bad block included in the flash memory device 110 during a power-on or initialization operation. The memory controller 120 of the present invention is configured not to search for all memory blocks included in the flash memory device 110, but to search only a block address range corresponding to the above-described spare block range. Accordingly, even searching for a part of the memory blocks may determine all addresses of the bad blocks included in the flash memory device 110.

The memory system 100 according to the present invention includes a flash memory device 110 for remapping bad blocks in a specific block address range and a memory controller 120 for searching for a bad block for a preliminary address period. do. Therefore, the memory controller 120 can quickly grasp the address of the bad block and provide the address to the host side or use it in the construction of the address mapping table.

FIG. 3 is a diagram schematically illustrating an embodiment of a block address map of a flash memory device 110 (refer to FIG. 2) configured according to remapping of a bad block. According to the remapping of bad blocks made in the flash memory device 110, the bad blocks are continuously distributed in a specific address range (for example, MB2043 to MB2047). According to the remapping of the bad blocks, the blocks of the flash memory device 110 are spare blocks in which bad blocks are continuously distributed in one region and the effective block range 130 accessed by the memory controller 120 (see FIG. 2). Range 140. The spare block range 140 includes normal memory blocks before the remapping of the bad block, but is converted from the memory block of the last address to the bad blocks according to the remapping of the bad block. Therefore, the spare block range 140 includes an address range including normal memory blocks (for example, MB2014 to MB2042) and a bad block range 150 in which bad blocks are consecutively located.

In conclusion, all bad blocks included in the flash memory device 110 are within the spare block range 140. Therefore, the memory controller 120 may be configured to search only the spare block range without searching all the memory blocks. In this case, the memory controller 120 may quickly recognize the addresses of the bad blocks and recognize the memory blocks as unavailable to the address mapping table.
4 is a flowchart schematically illustrating an embodiment of a method for searching for a bad block of a flash memory device 110 in which a bad block is remapped in the manner of FIG. 3. Referring to FIG. 4, the memory controller 120 searches only blocks corresponding to the spare block range 140 among all block addresses. Hereinafter, a method of searching for a bad block by the memory controller 120 will be described in detail with reference to the drawings.
When the search for the bad block is started, the memory controller 120 initializes the block address at which the first search is started to the start address (eg, Block address = 2014) of the spare block range 140 (S110). The memory controller 120 searches whether the block is a bad block from a start address (eg, Block address = 2014) of the spare block range 140. In general, each memory block of the flash memory device 110 stores check data indicating whether the block is a bad block or a normal block in a specific page and a specific column within the block. Therefore, the memory controller 120 reads check data stored at a specified address in the memory block (S120). The memory controller 120 determines whether the memory block being searched for is a bad block or a normal block with reference to the read check data (S130). If the check data indicates the bad block, the memory controller 120 designates the block address of the memory block being searched as the bad block. The memory block designated as the bad block is added to the bad block table configured in the memory controller 120. Subsequently, upon request for access from the host, the memory controller 120 may select valid blocks other than the memory blocks included in the bad block table described above (S140). On the other hand, if the check data does not indicate a bad block, the procedure moves to determining whether it corresponds to the block of the last address. In addition, the memory controller 120 determines whether the final block address is in the spare block range 140 (S150). If the retrieved memory block is the last block address in the spare block range 140, the bad block search ends. However, if it is not the last block, the memory controller 120 counts up the block address (S160). The memory controller 120 moves the procedure to step S120 for reading check data for the memory block corresponding to the counted up block address.
The bad block search operation described above is performed on memory blocks corresponding to the designated spare block range 140. However, as the bad blocks are continuously located in a part of the spare block range 140, it is possible to check the addresses of all bad blocks. Therefore, it is possible to secure the address of the bad bad blocks.
FIG. 5 is a flowchart schematically illustrating another embodiment of a method for searching for a bad block of a flash memory device 110 in which a bad block is remapped in the manner of FIG. 3. Referring to FIG. 5, the memory controller 120 searches only blocks corresponding to the spare block range 140 among all block addresses. However, in the exemplary embodiment illustrated in FIG. 5, all bad blocks may be detected by searching only some of the memory blocks included in the spare block range 140.
When the search for the bad block is started, the memory controller 120 initializes the block address at which the first search is started to the start address (eg, Block address = 2014) of the spare block range 140 (S210). The memory controller 120 searches whether it is a bad block or a normal block starting from the memory block corresponding to the start address (eg, Block address = 2014) of the spare block range 140. That is, check data of each memory block is read from a specific page and a specific column in the block (S220). The memory controller 120 determines whether the memory block being searched for is a bad block or a normal block with reference to the read check data (S230). If the check data indicates a normal block instead of a bad block, the memory controller 120 moves to determining whether the memory block currently being searched corresponds to the last block address. When the determination referring to the check data is completed, the memory controller 120 determines whether the memory block under search is the last block address in the spare block range. That is, the memory controller 120 determines whether the block address is a final address (for example, block adderss = 2047) (S240). If the retrieved memory block is the last block address in the spare block range 140, the bad block search ends. However, if it is not the last block, the memory controller 120 counts up the block address (S250). The memory controller 120 moves the operation procedure to step S220 for reading check data with respect to the memory block corresponding to the counted-up block address.
On the other hand, when it is determined with reference to the above-described check data, when it is determined as a bad block, all subsequent memory blocks are determined as bad blocks from the memory block determined as the first bad block. That is, as the addresses of the continuously distributed bad blocks are remapped in the reverse order from the last address, all the blocks after the first retrieved bad blocks may be determined as bad blocks (S260). The memory controller 120 adds the determined bad blocks to the bad block table configured on the memory controller 120 (S270). According to one bad block search, the addresses of the mode bad blocks were detected. Thus, no search operations are needed to find any more bad blocks. The search of the bad block is terminated by including all blocks after the retrieved block address in the bad block table.

5 illustrates a search method in which the first bad block is searched and all subsequent memory blocks can be regarded as a bad block, and thus include the first searched bad block to the last address in the bad block table. Thus, the configuration of the address table for the bad blocks can be made quickly. Here, in the above-described flowchart, the bad block table is configured using addresses of the bad blocks, but the present invention is not limited thereto. That is, it is obvious to those who have acquired a general knowledge in this field that a block table for valid blocks other than the bad block can be constructed.

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FIG. 6 is a diagram schematically illustrating another embodiment of a block address map of a flash memory device 110 (refer to FIG. 2) configured according to remapping of a bad block. According to the remapping of the bad blocks made in the flash memory device 110, the bad blocks are sequentially distributed adjacent to specific address ranges (eg, MB1020 to MB1023 and MB2045 to MB2047). In order for the bad blocks to be remapped, the flash memory device 110 allocates a spare block range in which the bad blocks can be allocated to the two address periods 160 and 170. Bad blocks are then allocated in reverse order from the last address of each spare block range 160, 170. Therefore, each of the spare block ranges 160 and 170 includes an address range including normal memory blocks (for example, MB1008 to MB1019 and MB2032 to MB2044) and an address range in which bad blocks are continuously located (for example, MB1020). MB1023 and MB2045 to MB2047). The memory controller 120 may obtain addresses of all bad blocks included in the flash memory device 110 by searching the above-described spare block ranges 160 and 170.

FIG. 7 is a flowchart schematically illustrating an operation for searching for a bad block of a flash memory device having a plurality of spare block ranges described in FIG. 6. Referring to FIG. 7, searching for a bad block includes two steps. That is, in order to search for the bad block, the memory controller 120 performs a search for the spare block range 160 (S300) and a search for the spare block range 170 (S400). More detailed embodiments will be described below in FIGS. 8A and 8B.
8A and 8B are flowcharts illustrating embodiments for the bad block search of FIG. 7. 8A shows an embodiment of searching all spare block ranges. 8B shows another embodiment of searching only a portion of the spare block range.
Referring to FIG. 8A, the memory controller 120 searches for the memory blocks corresponding to the spare block range 160 among all block addresses of the flash memory device 110 (S300) and corresponds to the spare block range 170. Searching for memory blocks to perform (S400), respectively. Detailed operations of step S300 are as follows.
When the search for the bad block is started, the memory controller 120 initializes the block address (for example, Block address = 1008) at which the first search is started in the spare block range 160 (that is, MB1008 to MB1023) to the start address. (S310). The memory controller 120 searches for a bad block starting from the start address of the spare block range 160 (eg, Block address = 1008). In general, each memory block of the flash memory device 110 stores check data indicating whether the block is a bad block or a normal block in a specific page and a specific column within the block. Therefore, the memory controller 120 reads check data stored at a specified address in the memory block (S320). The memory controller 120 determines whether the memory block being searched for is a bad block or a normal block with reference to the read check data (S330). If the check data indicates that the bad block, the memory controller 120 designates the block address of the found memory block as the bad block and adds the block address to the bad block table (S340). On the other hand, if the check data indicates that the bad block is not, the memory controller 120 will determine whether it is the last block of the spare block range 160 (ie, MB1008 to MB1023). When the determination referring to the check data is completed, the memory controller 120 determines whether the final block address (eg, Block address = 1023) is in the spare block range 160 (S350). If the retrieved memory block is the last block address in the spare block range 160, the bad block search ends. However, if it is not the last block, the memory controller 120 counts up the block address (S360). The memory controller 120 moves the operation procedure to step S320 for reading check data with respect to the memory block corresponding to the counted-up block address. When the search is completed up to the last block of the spare block range, step S300 ends.
Operation of step S400 following step S300 is as follows. The memory controller 120 initializes the block address (for example, Block address = 2032) at which the first search is started from the preliminary block range 170 (that is, MB2032 to MB2047) to the start address (S410). The memory controller 120 searches whether each of the memory blocks is a bad block, starting from the start address (eg, Block address = 2032) of the spare block range 170. The memory controller 120 reads check data stored at a specified address in the memory block and determines whether the block is a bad block or a normal block (S420). The memory controller 120 determines whether the memory block being searched for is a bad block or a normal block with reference to the read check data (S430). If the check data indicates that the bad block, the memory controller 120 designates the block address of the retrieved memory block as the bad block. That is, an address corresponding to the found valid block is added to the bad block table (S440). On the other hand, when the check data indicates that the bad block is not, the memory controller 120 does not include the corresponding block in the bad block table. When the determination referring to the check data is completed, the memory controller 120 determines whether the final block address (eg, Block address = 2047) is in the spare block range 170 (S450). If the retrieved memory block is the last block address in the spare block range 170, the bad block search ends. However, if it is not the last block, the memory controller 120 counts up the block address (S460). The memory controller 120 moves the operation procedure to step S420 for reading check data with respect to the memory block corresponding to the counted-up block address. When the search from the spare block range 170 to the last block address (eg, Block address = 2047) is completed, the memory controller 120 terminates all search operations for configuring the bad block table or the valid block table. .
In the above, operations for searching for a bad block for respective spare block ranges according to steps S300 and S400 have been described. In the embodiment described with reference to FIG. 8A, all spare block ranges must be searched. However, as long as the bad blocks are continuously distributed in a specific address range, the address information of the whole bad blocks may be obtained only by detecting the start address where the bad blocks are located. This embodiment will be described with the flowchart of FIG. 8B.
Referring to FIG. 8B, the memory controller 120 may detect all the bad blocks by searching only some of the memory blocks included in the spare block ranges 160 and 170. Step S300 for searching for bad blocks included in the spare block range 160 is as follows.
When the search for the bad block is started, the memory controller 120 initializes the block address at which the first search is started to the start address (eg, Block address = 1008) of the spare block range 160 (S310). The memory controller 120 searches whether it is a bad block or a normal block starting from the memory block corresponding to the start address (eg, Block address = 1008) of the spare block range 160. That is, check data of each memory block is read from a specific page and a specific column in the block (S320). The memory controller 120 determines whether the memory block being searched for is a bad block or a normal block with reference to the read check data (S330). If it is determined that the check data of the memory block under search is not the bad block, the memory controller 120 determines whether the memory block under search is the last block address in the spare block range 160. That is, the memory controller 120 determines whether the block address is a final address (for example, block adderss = 1023) (S340). If the retrieved memory block is the last block address in the spare block range 160, the procedure moves to the step for searching for the worship block range 170. However, if it is not the last block, the memory controller 120 counts up the block address (S350). The memory controller 120 moves the operation procedure to step S320 for reading check data with respect to the memory block corresponding to the counted-up block address.
On the other hand, when the check data read out in the step S330 of determining with reference to the above-described check data indicates the bad block, all subsequent memory blocks from the memory block currently being searched are designated as the bad block (S360). As the addresses of consecutively distributed bad blocks are remapped from the last address in reverse order, all of them are allocated as bad blocks after the block address of the first retrieved bad block. Thus, no search is needed to find more bad blocks. The search for the bad block for the spare block range 160 is terminated by including all the memory blocks corresponding to the last address of the spare block range 160 from the found block address in the bad block table (S370). Then, upon request for access from the host, the memory controller 120 may select the memory blocks with reference to the bad block table described above.
Subsequently, step S400 for searching for a bad block corresponding to the spare block range 170 is started. The memory controller 120 initializes the block address at which the initial search is started to the start address (for example, Block address = 2032) of the spare block range 170 (S410). The memory controller 120 searches whether it is a bad block or a normal block starting from the memory block corresponding to the start address (eg, Block address = 2032) of the spare block range 170. That is, check data of each memory block is read from a specific page and a specific column in the block (S420). The memory controller 120 determines whether the memory block being searched for is a bad block or a normal block with reference to the read check data (S430). If it is determined that the check data of the memory block under search is not the bad block, the memory controller 120 determines whether the memory block under search is the last block address in the spare block range 170. That is, the memory controller 120 determines whether the block address is a final address (for example, block adderss = 2047) (S440). If the retrieved memory block is the last block address in the spare block range 170, the overall procedure for searching for the bad block is terminated. However, if it is not the last block, the memory controller 120 counts up the block address (S450). The memory controller 120 moves the operation procedure to step S420 for reading check data with respect to the memory block corresponding to the counted-up block address.
On the other hand, when the check data read in the step S430 is determined by referring to the above-described check data indicates a bad block, all subsequent memory blocks from the currently searching memory block are designated as bad blocks (S460). As the addresses of consecutively distributed bad blocks are remapped from the last address in reverse order, all of them are allocated as bad blocks after the block address of the first retrieved bad block. Thus, no search is needed to find more bad blocks. The search for the bad block for the spare block range 170 is terminated by including all the memory blocks corresponding to the last address of the spare block range 170 after the retrieved block address in the bad block table (S470).

According to the bad block search method described in FIG. 8B, all the bad blocks of the flash memory device 110 may be searched by searching only a part of a designated spare block range. Therefore, the configuration of the address table for the bad blocks can be made at high speed, thereby enabling a quick booting or initialization of the memory system.

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9 is a simplified block diagram of a computing system 200 incorporating a flash memory system in accordance with the present invention. Referring to FIG. 9, a flash memory system 210 of the present invention is mounted in a computing system 200 such as a mobile device or a desktop computer. The computing system 200 according to the present invention includes a flash memory system 210 including a memory controller 212 and a flash memory device 211, a central processing unit 230 electrically connected to a system bus, and a RAM 240, respectively. , A user interface 250, and a power supply 220. The flash memory system 210 may be configured substantially the same as the flash memory system 100 of FIG. 2 mentioned above. The flash memory device 211 stores data provided through the user interface 250 or processed by the CPU 230 through the memory controller 212. Here, the CPU 230 and other components corresponding to the host on which the flash memory system 210 is mounted may be quickly accessed to the flash memory device 211 according to the remapping of the bad block. Alternatively, the bad block search operation of FIGS. 5 and 7 described above may be performed under the control of the host. If the flash memory system 210 is mounted as a semiconductor disk device (SSD), the booting speed of the system 200 will be significantly faster. Although not shown in the drawings, it is apparent to those skilled in the art that an application chipset, a camera image processor, or the like may be further provided in a system according to the present invention.

According to the flash memory device and the memory card system of the present invention, an address for the bad block can be obtained or provided by selectively searching only a partial block address range. Therefore, the performance of the flash memory device and the system can be improved.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not used to limit the scope of the present invention as defined in the meaning or claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

According to the present invention described above, it is possible to provide a flash memory system and a computing system capable of quickly searching for information on a bad block of a flash memory device.

Claims (20)

A flash memory device including a plurality of memory blocks corresponding to a first address section and a second address section, and configured to exchange a block address of a bad block belonging to the first address section with a block address of the second address section; And And a memory controller configured to control the flash memory device to search memory blocks corresponding to the second address period and output search results as bad block information during a bad block search operation. The method of claim 1, The block address of the bad block belonging to the first address period is preferentially exchanged with the last block address among the normal blocks of the second address period. The method of claim 2, The memory controller searches for all memory blocks corresponding to the second address section in an initialization operation of the flash memory device. The method of claim 2, The memory controller sequentially searches memory blocks corresponding to the second address interval, and performs the bad block search operation until the first bad block is searched. The method of claim 4, wherein The memory controller recognizes the memory blocks corresponding to the block address of the memory block found as the first bad block or the last block address as a bad block. Claim 6 was abandoned when the registration fee was paid. The method of claim 1, The second address period includes a plurality of preliminary address periods each having a consecutive block address period. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 6, Each of the plurality of spare address periods includes a block address of bad blocks. Claim 8 was abandoned when the registration fee was paid. The method of claim 7, wherein The memory controller searches for memory blocks corresponding to the plurality of preliminary address periods during the bad block search operation. Claim 9 was abandoned upon payment of a set-up fee. The method of claim 8, The memory controller searches for memory blocks corresponding to each of the plurality of preliminary address periods, and performs the bad block search operation until an initial bad block is found in each of the plurality of preliminary address periods. In the bad block management method of a flash memory system: The flash memory device may include a plurality of memory blocks corresponding to a first address section and a second address section, and configured to exchange a block address of a bad block belonging to the first address section with a block address of the second address section. Providing; And And performing a bad block search for memory blocks belonging to the second address period. 11. The method of claim 10, In the providing of the flash memory device, the block address of the bad block is preferentially exchanged with the last block address of the normal blocks of the second address interval. The method of claim 11, Performing the bad block search, (a) setting a block address for selecting memory blocks corresponding to the second address period, wherein initializing a start address to an initial address of the second address period; (b) reading bad block information indicating whether the block is bad from the memory block corresponding to the set block address, and determining whether the memory block corresponding to the set block address is a bad block by referring to the read bad block information; Making; And (c) if the read bad block information indicates a normal block, adding the set block address to a valid block table. 13. The method of claim 12, In step (c), when the read bad block information indicates that the bad block, the set block address is added to the bad block table, characterized in that the bad block table. Claim 14 was abandoned when the registration fee was paid. 13. The method of claim 12, And (d) after the step (c), determining whether the set block address corresponds to a last block of the second address period. Claim 15 was abandoned upon payment of a registration fee. The method of claim 14, In step (d), If the set block address is not the last block of the second address interval, counting up the set block address to select a subsequent memory block subsequent to the set block address and moving to step (b) (e) The bad block management method further comprising a step. 13. The method of claim 12, And in step (c), if the bad block information indicates that the bad block is a bad block, adding the block address or the last block address of the memory block in which the bad block information is found to the bad block table. Claim 17 has been abandoned due to the setting registration fee. 13. The method of claim 12, And the second address section includes a plurality of preliminary address sections each having a contiguous block address section. Claim 18 was abandoned upon payment of a set-up fee. The method of claim 17, Each of the plurality of spare address periods includes a block address of bad blocks. Claim 19 was abandoned upon payment of a registration fee. The method of claim 18, And performing operations according to steps (a) to (c) for each of the plurality of preliminary address periods. Claim 20 was abandoned upon payment of a registration fee. Memory card; And And a computing system for exchanging data with said memory card, said memory card being the memory system of claim 1.

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