KR101088457B1 - Method For Fabricating Polysilicon Hard Mask Using Metal Catalyst and Method For Fabricating Semiconductor Device Using The Same - Google Patents

Method For Fabricating Polysilicon Hard Mask Using Metal Catalyst and Method For Fabricating Semiconductor Device Using The Same Download PDF

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KR101088457B1
KR101088457B1 KR1020090029866A KR20090029866A KR101088457B1 KR 101088457 B1 KR101088457 B1 KR 101088457B1 KR 1020090029866 A KR1020090029866 A KR 1020090029866A KR 20090029866 A KR20090029866 A KR 20090029866A KR 101088457 B1 KR101088457 B1 KR 101088457B1
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layer
method
polysilicon
metal catalyst
amorphous silicon
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KR20100111433A (en
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박경완
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주식회사 테라세미콘
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31144Etching the insulating layers by chemical or physical means using masks
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02664Aftertreatments
    • H01L21/02667Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02672Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using crystallisation enhancing elements
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10844Multistep manufacturing methods
    • H01L27/10847Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells
    • H01L27/1085Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto
    • H01L27/10852Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto the capacitor extending over the access transistor
    • H01L27/10855Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto the capacitor extending over the access transistor with at least one step of making a connection between transistor and capacitor, e.g. plug
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10844Multistep manufacturing methods
    • H01L27/10847Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells
    • H01L27/10882Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making a data line
    • H01L27/10888Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making a data line with at least one step of making a bit line contact
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate

Abstract

In the present invention, a method of manufacturing a polysilicon mask using a metal catalyst and a method of manufacturing a semiconductor device using the same are disclosed. Method for producing a polysilicon mask using a metal catalyst according to the present invention, providing a substrate (10); Forming one or a plurality of thin film layers 20 on the substrate 10; Forming an amorphous silicon layer 30 on the thin film layer 20; Forming a metal catalyst layer 40 on the amorphous silicon layer 30; And heat treating the amorphous silicon layer 30 to form the polysilicon mask 31.
Polysilicon, hard mask, metal catalyst, capacitor

Description

Method for fabricating polysilicon mask using metal catalyst and manufacturing method of semiconductor device using same {Method For Fabricating Polysilicon Hard Mask Using Metal Catalyst and Method For Fabricating Semiconductor Device Using The Same}

The present invention relates to a method of manufacturing a polysilicon mask using a metal catalyst and a method of manufacturing a semiconductor device using the same. More particularly, the polysilicon mask used in an etching process of a semiconductor device is crystallized at a low temperature using a metal catalyst. A method of manufacturing a polysilicon mask using a metal catalyst, and a method of manufacturing a semiconductor device capable of improving the degree of integration by improving the pattern precision of the semiconductor device using the same.

As the demand for memory and non-memory embedded in most electronic devices increases, the demand for semiconductor technology and displays such as mobile phones, notebooks, personal digital assistants (PDAs), and large TVs increases. Flat Panel Display) technology is developing rapidly.

In particular, in the semiconductor field, technology development for realizing highly integrated semiconductors with improved processing speed and storage capacity is being progressed. In addition, the number of pixels is increasing in flat panel displays to improve the clarity of image quality, and the development of a system on panel (SOP) technology that integrates a scan driver and a data driver on a glass to improve the size and driving speed is in progress. have.

In order to achieve such a technique, a technique for minimizing the width of the wiring pattern and improving the precision of the pattern is required. For this purpose, the function of a mask for determining the pattern is most important.

However, in the related art, the fine pattern may be formed by lowering the height of the photoresist due to the limitation of the exposure technique. However, as the degree of integration of semiconductor devices increases, it is necessary to form contacts having high aspect ratios or self-aligned contacts while maintaining very small line widths, but the etching selectivity of the oxide film to the photoresist film is limited. Therefore, such a photoresist film has a limitation in performing a role of a mask in manufacturing a semiconductor device having a high degree of integration.

In order to solve this problem, a method using a hard mask having a high selectivity has been proposed. The hard mask is usually formed of polysilicon (p-Si). However, in the case of using polysilicon (p-Si), the a-Si is crystallized to p-Si only by performing heat treatment for a long time at a high temperature of more than 650 ℃ in the process of depositing amorphous silicon (a-Si) and then crystallizing. Can be. Since the heat treatment is performed for a long time at a high temperature, it is possible to increase the thermal budget of the semiconductor device, and there is a limit to uniform crystallization as a whole, resulting in a mask of non-uniform density, so it is difficult to implement precise etching.

The present invention is to solve the above problems of the prior art, it is an object to reduce the crystallization temperature and time of the hard mask formed of polysilicon.

In addition, the present invention has another object to improve the deterioration of the characteristics and the decrease in productivity generated during the pattern formation (etching process) of the semiconductor device using a hard mask formed of polysilicon.

The object of the present invention is to provide a substrate; Forming one or a plurality of thin film layers on the substrate; Forming an amorphous silicon layer on the thin film layer; Forming a metal catalyst layer on the amorphous silicon layer; And heat treating the amorphous silicon layer to form a polysilicon mask.

In addition, the object of the present invention is to form an etch stop layer on the substrate including a source / drain region and a gate line; Forming a mold layer on the etch stop layer; Forming an amorphous silicon layer on the mold film; Forming a metal catalyst layer on the amorphous silicon layer; Heat treating the amorphous silicon layer to form a polysilicon layer; Forming a storage contact hole by etching the etch stop layer and the mold layer using the polysilicon layer as a hard mask; And forming a capacitor including a storage electrode electrically connected to the source / drain region through the storage contact hole.

In this case, the metal catalyst layer may include at least one of Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Mo, Tr, Ru, Rh, Cd and Pt.

The heat treatment temperature may be 500 to 650 ℃.

The material of the substrate may be any one of a semiconductor, glass, plastic, and metal material.

The thin film layer may be any one of an insulating layer, a metal layer, and a semiconductor layer.

 to be.

According to the present invention, the heat treatment temperature and time of the hard mask formed of polysilicon can be reduced.

Moreover, according to this invention, the integration degree of a semiconductor element can be improved using the hard mask formed from polysilicon.

In addition, according to the present invention, the etching accuracy of the semiconductor device can be improved by using a hard mask made of polysilicon.

Moreover, according to this invention, the characteristic and productivity of a semiconductor element can be improved using the hard mask formed from polysilicon.

DETAILED DESCRIPTION The following detailed description of the invention refers to the accompanying drawings that show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that the various embodiments of the present invention are different but need not be mutually exclusive. For example, certain features, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the invention in connection with an embodiment. It is also to be understood that the position or arrangement of the individual components within each disclosed embodiment may be varied without departing from the spirit and scope of the invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention, if properly described, is defined only by the appended claims, along with the full range of equivalents to which such claims are entitled. In the drawings, like reference numerals refer to the same or similar functions throughout the several aspects, and length, area, thickness, and the like may be exaggerated for convenience.

DETAILED DESCRIPTION Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention.

[Preferred Embodiments of the Invention]

Poly  Semiconductor device using silicon mask

1A to 1E are cross-sectional views illustrating a process of manufacturing a semiconductor device using a hard mask formed of polysilicon according to an embodiment of the present invention.

Referring first to FIG. 1A, a substrate 100 is provided according to an embodiment of the present invention. The substrate 100 may be a semiconductor wafer or a transparent material (eg, a glass substrate) capable of transmitting light, but is not limited thereto. The substrate 100 may be a plastic, a metal in a thin film form, or the like.

Subsequently, one or a plurality of thin film layers 20 may be formed on the substrate 10. The thin film layer 20 may be any one of an insulating layer, a metal wiring, and a semiconductor layer constituting a semiconductor device.

Next, referring to FIG. 1B, an amorphous silicon layer 30 having a pattern may be formed on the thin film layer 20. The amorphous silicon layer 30 may be formed of a low pressure chemical vapor deposition (LPCVD) or It may be formed using a Plasma Enhanced Chemical Vapor Deposition (PECVD). In this case, since the amorphous silicon layer 30 is provided with a pattern exposing only an area requiring etching in the thin film layer 20, the amorphous silicon layer 30 may function as a mask in a subsequent process.

Subsequently, the metal catalyst layer 40 may be formed on the amorphous silicon layer 30. The metal catalyst layer 40 may be formed of Ni, Pd, Ti, Ag, Au, Al, Sn, One or more of Sb, Cu, Co, Mo, Tr, Ru, Rh, Cd, or Pt may be included. Preferably, nickel (Ni) having easy reaction control may be used.

Meanwhile, the metal catalyst layer 40 may be formed by physical vapor deposition such as thermal deposition or sputtering or chemical vapor deposition such as LPCVD or PECVD.

Next, referring to FIG. 1C, the amorphous silicon layer 30 is formed of a polysilicon layer 31 (hereinafter, referred to as a polysilicon mask) by performing a heat treatment process that heats the entire surface of the metal catalyst layer 40 of the substrate 10. Can be crystallized.

In more detail, some of the metal catalysts (not shown) included in the metal catalyst layer 40 may be moved to the surface of the amorphous silicon layer 30 by this heat treatment. That is, the metal catalyst of the metal catalyst layer 40 is combined with the silicon of the amorphous silicon layer 30 to form a metal silicide, and the metal silicide acts as a seed, which is the nucleus of crystallization, so that the amorphous silicon layer 30 Induce crystallization. At this time, the temperature of the heat treatment may proceed in the temperature range of 500 ℃ to 650 ℃, preferably at a temperature of 550 ℃ can be easily crystallized by diffusing the metal catalyst to the amorphous silicon layer (30).

As the heat treatment method, any one or more of a furnace process, a rapid thermal annealing (RTA) process, a UV process, or a laser process may be used.

Therefore, the polysilicon mask 31 can crystallize using a metal catalyst diffused at a low temperature of 550 ° C. as a seed without performing a high temperature heat treatment of 650 ° C. or higher as in the prior art, thereby functioning as a hard mask. Can be performed. In this case, in one embodiment of the present invention, the crystallization of the polysilicon mask 31 may be controlled by adjusting the thickness or density of the metal catalyst layer 40.

Next, referring to FIG. 1D, the thin film layer 20 may be etched in a predetermined pattern using the crystallized polysilicon mask 31 to form a contact hole 20a. For example, C 4 F 8 + CO plasma gas Plasma dry etching using Ar as a carrier gas, but the present invention is not limited thereto, and various known etching methods capable of forming the contact hole 20a may be applied. .

Next, referring to FIG. 1E, the polysilicon layer 31 and the metal catalyst layer 40 formed on the thin film layer 20 may be removed, for example, chemical mechanical polishing (CMP), wet etch back, dry etch back, or the like. Stripping may be performed in the same manner, but the present invention is not limited thereto.

As described above, the semiconductor device using the polysilicon mask according to the embodiment of the present invention can significantly reduce the heat treatment temperature and the heat treatment time, and crystallize using a plurality of seeds, thereby providing a thermal budget for the semiconductor device. It is possible to reduce the budget) and to improve the uniformity of crystallization, thereby realizing a more precise and non-degrading semiconductor device.

Meanwhile, in the present embodiment, first, the amorphous silicon layer 30 is patterned in advance according to the shape of the mask to be manufactured in the future, and then the metal catalyst layer 40 is formed on the amorphous silicon layer 30 and then heat treated to form the polysilicon mask. 31 is formed, but is not necessarily limited thereto. That is, in some cases, the metal catalyst layer 40 may be formed on the amorphous silicon layer 30, and then heat-treated to form a polysilicon layer, and then patterned according to the shape of a mask to be manufactured.

In the following detailed description, a specific example is applied to aid in understanding the polysilicon mask according to an embodiment of the present invention. Such a polysilicon mask may be used in an etching process for patterning a thin film formed on a substrate. The polysilicon mask mainly uses a DRAM process using a polysilicon mask, a bit line and a contact ( Contact) process is described as an example, but the present invention is not limited thereto, and the present invention may be used without limitation in general semiconductor technology for etching a thin film using a hard mask.

Poly  DRAM using silicon mask DRAM )

2A to 2H are cross-sectional views illustrating a process of fabricating a cell region of a DRAM using a polysilicon mask according to an embodiment of the present invention.

Referring first to FIG. 2A, a substrate 100 is provided according to an embodiment of the present invention. The substrate 100 may be, for example, an n or p-type semiconductor substrate 100, and an isolation layer 200 of an insulating material may be formed in an internal region to separate an area between devices.

Subsequently, a gate insulating layer 310 formed of an insulating material, a gate electrode 320 formed of a conductive material, and a capping layer 330 formed of an insulating material may be sequentially stacked on the substrate 100. For example, the gate insulating layer 310 may be SiO 2 , and the gate electrode 320 may include at least one selected from polysilicon, a metal (eg, tungsten or molybdenum), and a metal silicide. In addition, the capping insulating layer 330 may be a silicon nitride layer (Si 3 N 4 ).

Subsequently, the stacked gate insulating layer 310, the gate electrode 320, and the capping layer 330 may be etched in a predetermined pattern to form the gate line 300, which will be described in an embodiment of the present invention. The polysilicon mask 31 can be applied.

In more detail, the amorphous silicon layer 30 having a predetermined pattern is formed on the capping insulating layer 330, the metal catalyst layer 40 is formed on the amorphous silicon layer 30, and then subjected to a 550 ° C. heat treatment process. The heat treatment temperature and heat treatment time can be crystallized with the reduced polysilicon mask 31. Therefore, the contact hole can be easily etched using the polysilicon mask 31 as a hard mask.

Subsequently, dopant ions are implanted into a predetermined region of the substrate 100 using the gate line 300 etched with the polysilicon mask 31 as a mask to form the first source / drain region 110a and The second source / drain region 110b may be formed.

Next, referring to FIG. 2B, the capping spacer 340 may be formed on the semiconductor substrate 100 on which the gate line 300 is formed by a low pressure chemical vapor deposition method. The capping spacer 340 may form the same silicon nitride layer Si 3 N 4 as the capping insulating layer 330. In this case, the capping spacer 340 may be formed by anisotropic etching, and the capping part including the capping insulating layer 330 and the capping spacer 340 may damage the gate electrode 320 from a subsequent etching process of the upper oxide layer. To prevent it.

Next, referring to FIG. 2C, contact pads 330a and 330b are formed for each contact hole by forming a conductive material on the entire upper surface of the substrate including the contact holes and then removing a conductive material other than the contact holes. Can be.

Subsequently, the first interlayer insulating layer 410 may be formed on the entire upper surface of the substrate, and the first interlayer insulating layer 410 may be formed of SiO 2 by, for example, chemical vapor deposition.

Subsequently, the first interlayer insulating layer 410 is etched in a predetermined pattern to form a bit line contact hole exposing the contact pad 330b connected to the second source / drain region 110b. In the etching process, the polysilicon mask 31 described in the above-described embodiment of the present invention may be equally applied. At this time, the amorphous silicon mask 30 and the metal catalyst layer 40 are formed on the first interlayer insulating film 410 and then heat-treated to form the polysilicon mask 31, and the etching process is performed using the polysilicon mask 31 as a hard mask. Steps are the same as described above, detailed description thereof will be omitted.

In addition, an embodiment of the present invention also when etching the first interlayer insulating layer 410 for forming the storage contact hole exposing the contact pad 330a connected to the first source / drain region 110a which is performed in a subsequent process. The polysilicon mask described in may be applied.

Next, referring to FIG. 2D, a conductive material such as tungsten is formed on the entire upper surface of the first interlayer insulating layer 410 having the bit line contact hole, and then removed using a chemical mechanical polishing or etch back process. To form a contact plug 430b.

Subsequently, after the bit line 440 is formed of a conductive material, a second interlayer insulating layer 420 may be formed. The second interlayer insulating layer 420 may be formed of SiO 2 by, for example, chemical vapor deposition. have.

Subsequently, as described above, the second interlayer insulating layer 420 may be etched to form a storage contact hole exposing the contact pad 330a connected to the first source / drain region 110a. The contact plug 430a may be formed by forming a conductive material such as tungsten on the entire upper surface of the hole and then removing the same by using a chemical mechanical polishing or etch back process.

Subsequently, an etch stopping layer 500 may be formed on the entire upper surface of the semiconductor substrate 100, and a mold layer 510 may be formed on the etch stop layer 500. For example, the etch stop layer 500 may be formed. May be a silicon nitride film, and the mold film 510 may be silicon oxide.

Next, referring to FIGS. 2E and 2F, the etch stop layer 500 and the mold layer 510 may be etched to form a capacitor contact hole for connecting to the first source / drain region 110a. An etching of the capacitor contact hole exposing the contact plug 430a may be performed. In the etching process of the capacitor contact hole, the polysilicon mask 31 described in the embodiment of the present invention described above may be applied in the same manner. In this case, the amorphous silicon mask 30 and the metal catalyst layer 40 are formed on the mold layer 510 and then heat-treated to form the polysilicon mask 31, and the etching process using the polysilicon mask 31 is performed as a hard mask. The detailed description is omitted because the same as described above.

2G and 2H, the conductive material is formed on the entire upper surface of the substrate including the capacitor contact hole and then the storage electrode 600 is formed by using a chemical mechanical polishing or etch back process. Subsequently, a process of removing the mold layer 510 may be performed.

Subsequently, the storage electrode 600, the dielectric layer 700, and the plate electrode 800 may be formed by sequentially stacking a capacitor. Since the forming step is a known technique, a detailed description thereof will be omitted.

Therefore, by implementing a high density hard mask using a polysilicon mask through a short heat treatment at a low temperature, it is possible to perform good patterning in the capacitor process of the DRAM, the bit line and the contact process. Can be. That is, etching can be performed precisely and without deterioration of the characteristics of the semiconductor device, and in particular, the etching precision and efficiency of the stack capacitor can be improved.

In the foregoing detailed description, the present invention has been described by specific embodiments such as specific components and the like, but the embodiments and drawings are provided only to help a more general understanding of the present invention, and the present invention is limited to the above embodiments. However, one of ordinary skill in the art can make various modifications and variations from this description.

Accordingly, the spirit of the present invention should not be limited to the above-described embodiments, and all of the equivalents or equivalents of the claims, as well as the appended claims, fall within the scope of the spirit of the present invention. I will say.

1A to 1E are cross-sectional views illustrating a process of manufacturing a semiconductor device using a hard mask formed of polysilicon according to an embodiment of the present invention.

2A to 2H are cross-sectional views illustrating a process of fabricating a cell region of a DRAM using a polysilicon mask according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

10, 100: substrate

20: thin film layer

30: amorphous silicon layer

31: polysilicon mask

40: metal catalyst layer

200: separator

300: gate line

500: etch stop film

510: mold film

600: storage electrode

700: dielectric film

800: plate electrode

Claims (8)

  1. Providing a substrate;
    Forming an amorphous silicon layer on the substrate;
    Forming a metal catalyst layer on the amorphous silicon layer;
    Patterning the amorphous silicon layer and the metal catalyst layer; And
    Heat treating the patterned amorphous silicon layer to form a polysilicon mask
    Method of producing a polysilicon mask comprising a.
  2. delete
  3. The method of claim 1,
    The metal catalyst layer is a polysilicon mask comprising any one or more of Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Mo, Tr, Ru, Rh, Cd and Pt Manufacturing method.
  4. The method of claim 1,
    The heat treatment temperature is a method for producing a polysilicon mask, characterized in that 500 to 650 ℃.
  5. The method of claim 1,
    The material of the substrate is a method of manufacturing a polysilicon mask, characterized in that any one of a semiconductor, glass, plastic, metal.
  6. Forming an etch stop layer on the substrate including a source / drain region and a gate line formed thereon;
    Forming a mold layer on the etch stop layer;
    Forming an amorphous silicon layer on the mold film;
    Forming a metal catalyst layer on the amorphous silicon layer;
    Heat treating the amorphous silicon layer to form a polysilicon layer;
    Forming a storage contact hole by etching the etch stop layer and the mold layer using the polysilicon layer as a hard mask; And
    Forming a capacitor including a storage electrode electrically connected to the source / drain region through the storage contact hole
    Method of manufacturing a semiconductor device using a polysilicon mask comprising a.
  7. The method of claim 6,
    The metal catalyst layer is a polysilicon mask comprising any one or more of Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Mo, Tr, Ru, Rh, Cd and Pt Method of manufacturing a semiconductor device using.
  8. The method of claim 6,
    The heat treatment temperature is a manufacturing method of a semiconductor device using a polysilicon mask, characterized in that 500 to 650 ℃.
KR1020090029866A 2009-04-07 2009-04-07 Method For Fabricating Polysilicon Hard Mask Using Metal Catalyst and Method For Fabricating Semiconductor Device Using The Same KR101088457B1 (en)

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KR1020090029866A KR101088457B1 (en) 2009-04-07 2009-04-07 Method For Fabricating Polysilicon Hard Mask Using Metal Catalyst and Method For Fabricating Semiconductor Device Using The Same
TW099109582A TW201044106A (en) 2009-04-07 2010-03-30 Method for fabricating polysilicon hard mask using metal catalyst and semiconductor device using the same
PCT/KR2010/002116 WO2010117201A2 (en) 2009-04-07 2010-04-07 Production method for a polysilicon mask using a metal catalyst, and a production method for semiconductor elements using the same
CN201080015376XA CN102365710A (en) 2009-04-07 2010-04-07 Production method for a polysilicon mask using a metal catalyst, and a production method for semiconductor elements using the same
JP2012504609A JP2012523129A (en) 2009-04-07 2010-04-07 Method for manufacturing polysilicon mask using metal catalyst and method for manufacturing semiconductor device using the mask

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US9385002B2 (en) * 2013-10-01 2016-07-05 Samsung Electronics Co., Ltd. Semiconductor devices and fabricating methods thereof

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