KR101064900B1 - Method of forming pattern - Google Patents

Abstract

A pattern forming method is disclosed. A UV-based nanoimprint lithography method is used on the substrate on which the polymer layer is formed to transfer a predetermined pattern to the polymer layer. A hole pattern is formed on the substrate by applying a two-stage lift-off process using a selective etching method to the polymer layer to which a certain pattern is transferred. In the pattern forming method according to the present invention, a hole-shaped pattern may be formed on a substrate from a pillar dot stamp without distortion of the pattern resolution.

Nanoimprint Lithography, Two-Stage Lift-off, Hole Pattern

Description

Pattern Forming Method {METHOD OF FORMING PATTERN}

The present invention relates to a method of forming a pattern of a semiconductor device, and more particularly, to a method of forming a nanoscale hole pattern capable of forming a photonic crystal structure in a semiconductor device such as a light emitting diode, a chemical and a biological sensor.

Nanoimprint lithography is a technology that can produce nanoscale structures at low cost and is drawing attention as an alternative to low-productivity electron beam lithography and expensive optical lithography.

The core of nanoimprint technology is to produce a stamp with nanoscale structure by using advanced lithography technology such as electron beam lithography, imprint the stamp on the polymer thin film, transfer the nanoscale structure, and use the manufactured stamp repeatedly The low productivity problem of electron beam lithography can be overcome.

On the other hand, in order to increase the light absorption surface area of the transparent electrode of the solar cell and improve the light extraction efficiency of the light emitting diode has been attempted to introduce a photonic crystal structure using nanoimprint lithography.

In the related art, in order to obtain a nanoscale hole pattern using nanoimprint technology, a method of making a hole mask on a desired substrate using a pillar dot pattern stamp and using the same is used. It became.

However, since the pattern etched using the polymer mask is not only uniform but not etched vertically, the effect of forming the photonic crystal structure is insignificant. For this reason, the photonic crystal structure until now has been mostly pillar-shaped because a metal mask having a dot shape is formed by removing a polymer after depositing a metal on the polymer hole pattern and etching using the metal mask. .

In addition, although a hole pattern may be made on a desired substrate by using a hole stamp from the beginning in the nanoimprint process, uniformity is inferior due to air in the stamp pattern.

It is an object of the present invention to provide a method of forming a pattern using a nanoimprint technique and a two-stage lift-off technique to introduce a photonic crystal structure into a semiconductor device.

Method of forming a pattern according to a preferred embodiment of the present invention for achieving the above object is to provide a substrate on which a polymer layer is formed, forming a predetermined pattern on the polymer layer, the substrate and the constant pattern is formed Forming a first metal layer on the polymer layer, removing the polymer layer, forming a second metal layer on the substrate and the first metal layer, removing the first metal layer and masking the second metal layer Etching the substrate, and removing the second metal layer.

According to the pattern forming method of the present invention as described above has the following effects.

First, a hole pattern may be formed on a substrate using a stamp in the form of a pillar dot using nanoimprint lithography and a two-stage lift-off process.

Second, nanoscale hole patterns can be formed without limitation on materials of substrates (Si, SiOx, GaN, ITO, etc.) used in solar cells, light emitting diodes, and the like.

The effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be embodied in various different forms, and the present embodiments merely make the disclosure of the present invention complete, and are common in the art to which the present invention pertains. It is provided to fully inform those skilled in the art of the scope of the invention, which is to be defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

Hereinafter, a method of forming a nanoscale hole pattern according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings. In the following description, well-known functions or constructions are not described in detail to avoid unnecessarily obscuring the subject matter of the present invention.

1A to 1I are process diagrams sequentially illustrating a method of forming a hole pattern according to a preferred embodiment of the present invention.

Method of forming a pattern according to a preferred embodiment of the present invention comprises the steps of providing a substrate 10 having a polymer layer formed thereon, forming a predetermined pattern on the polymer layer, the substrate 10 and the predetermined pattern is formed Forming a first metal layer 50 on the polymer layer, removing the polymer layer, forming a second metal layer 60 on the substrate 10 and the first metal layer 50, the Removing the first metal layer 50, etching the substrate 10 using the second metal layer 60 as a mask, and removing the second metal layer 60.

The substrate 10 is a substrate on which a desired final pattern is formed, and is used for semiconductors such as silicon, silicon oxide, silicon nitride, indium tin oxide (ITO), (transparent) electrodes used for solar cells, and clad layers of light emitting devices. Gallium nitride (GaN), zinc oxide (ZnO), and the like.

FIG. 1A is a diagram illustrating a substrate 10 on which a polymer layer having a two-layer structure of a resist layer 30 and an under layer 20 is formed.

The polymer layer may be formed as a single layer on the substrate 10 by using a method such as spin coating a resist having a property of curing in ultraviolet light.

In particular, the polymer layer may include a UV-cured resist, the UV-cured resist may be composed of poly (dimethylsiloxane), ethylene glycol dimethacrylate and 1-hydroxy-cyclohexyl-phenyl-ketone, and the AS9 (silicone Acrylate derivative containing 9 wt%), AS19 (acrylate derivative containing 19 wt% silicon), and 1-hydroxy-cyclohexyl-phenyl-ketone.

However, the resist is not limited to the above materials and may be any polymer material having ultraviolet curing properties, including PDMS (polydimethylsiloxane).

2a to 2c show the chemical structures of AS9, AS19 and 1-hydroxy-cyclohexyl-phenyl-ketone, respectively.

In addition, the polymer layer may be formed in a two-layer structure of a resist layer 30 and an under layer 20.

The resist layer 30 is used as the polymer resist and the under layer 20 maintains adhesion to the substrate 10, maintains bonding with the resist when the stamp 40 is separated, and during the metal lift-off process. It is composed of a polymer having a property of being well dissolved in a solvent, and LOL 1000 (Shipley Ltd.) may be used.

In the case of the polymer layer of the two-layer structure, patterns imprinted on the resist layer by the master stamp 40 described below are transferred to the under layer 20 by selective reactive ion etching (RIE) or the like.

By introducing the two-layer structure into the polymer layer as described above, the aspect ratio of the entire resist structure can be improved by etching up to the underlayer 20 and the substrate 10 from the sidewalls of the trench in the underlayer 20. The metal lift-off process can be improved by creating a resist undercut on the side that separates the metal deposition layer on the phase.

Forming a predetermined pattern on the polymer layer comprises first imprinting the master stamp 40 in the form of pillar dots (pillar dots) formed at regular intervals on the polymer layer formed on the substrate 10.

1B illustrates a process of nanoimprinting the resist layer 30 using the master stamp 40 having a predetermined pattern formed thereon.

The master stamp 40 is a nano structure corresponding to the nano structure to be formed on the substrate 10 or the like is engraved on the surface of quartz, glass, sapphire or silicon nitride (Si ₃ N ₄ ) And the like.

During imprinting, ultraviolet light (UV) is irradiated onto the polymer layer to cure the polymer layer.

After the curing of the polymer layer is completed, removing the master stamp 40, a predetermined pattern is formed on the polymer layer.

In the forming of the predetermined pattern on the polymer layer, after removing the master stamp 40, the residual resist layer 30 under the trench is removed by etching, and the under layer 20 is etched using the resist layer 30 as a mask. It involves doing.

FIG. 1C illustrates that after the master stamp 40 is removed, the residual resist layer 30 and the under layer 20 under the trench are etched by etching.

After a predetermined pattern is formed on the polymer layer, a first metal layer 50 is formed on the substrate 10 and the polymer layer.

FIG. 1D illustrates a deposition of the first metal layer 50 on the substrate 10 and on the resist.

The first metal layer 50 may be aluminum, gold, silver, or the like, and preferably aluminum.

Subsequently, the polymer layer on the substrate, shown in FIG. 1D, is removed. Removing the polymer layer may include a first lift-off process of dissolving the polymer by injecting a specimen into a polymer remover after the first metal layer 50 is formed.

When the polymer layer on the substrate is removed, the first metal layer formed on the polymer layer is also removed, and only the first metal layer formed directly on the substrate remains. Therefore, after the polymer layer is removed, the first metal layer 50 is formed in a dot shape on the substrate 10.

FIG. 1E illustrates that only the first metal layer 50 is formed on the substrate 10 by ripping-off the underlayer 20.

Subsequently, a second metal layer is formed on the substrate on which the first metal layer remains. The second metal layer 60 may be formed by forming a metal layer such as chromium having a different solubility in the first metal layer 50 and the etchant on the substrate 10 in which the first metal layer 50 is formed in a dot shape. By forming. That is, the selection of the second metal layer may be any metal having an etching selectivity with the first metal layer.

The second metal layer 60 is formed on the substrate 10 by the formation of the second metal layer 60, and the second metal layer 60 is locally formed on the dot-shaped first metal layer 50.

FIG. 1F illustrates that the second metal layer 60 is formed on the substrate 10 and the first metal layer 50 by depositing the second metal layer 60 on the substrate 10.

Subsequently, the first metal layer is removed from the structure shown in FIG. 1F and a portion of the second metal layer is selectively left. The removing of the first metal layer 50 may include a second lift-off process of dipping the specimen on which the second metal layer 60 is formed to remove the first metal by dissolving the first metal. As a result, the first metal layer 50 and the second metal layer 60 on the first metal layer 50 are removed, and only the second metal layer 60 formed on the substrate 10 remains.

Accordingly, hole patterns may remain in the second metal layer 60 by selectively dissolving the first metal by the second lift-off process.

In FIG. 1G, the second metal layer 60 is formed on the substrate 10 by removing the first metal layer 50.

Subsequently, the substrate 10 is etched using the second metal layer 60 shown in FIG. 1G as an etching mask. The etching of the substrate 10 by using the second metal layer 60 as a mask may be performed by using a pattern formed on the second metal layer 60 after the first metal layer 50 is removed. Etching the substrate 10.

FIG. 1H illustrates a process of etching the substrate 10 using the second metal layer 60 as a mask.

After the final pattern is formed on the substrate 10, the second metal layer 60 is removed, thereby enabling application of the substrate 10 to a desired semiconductor device.

FIG. 1I illustrates a pattern formed on the substrate 10 after removing the second metal layer 60.

Hereinafter, an example of preparing a master stamp and an example of manufacturing a nanoscale hole pattern using a two-stage lift-off process will be provided to assist in understanding the present invention. However, the following preparation examples are merely to aid the understanding of the present invention, and the present invention is not limited by the following preparation examples.

Production Example 1: Stamp Production Example

A 200 nm thick silicon nitride (Si ₃ N ₄ ) thick film was uniformly deposited on a borosilicate glass substrate (1.5 × 1.5 cm ² ) using plasma accelerated chemical vapor deposition (PECVD).

Interference lithography using a He-Cd laser (325 nm) with an intensity of 0.75 mW / cm ² was used to fabricate the master stamp.

3 is a simplified illustration of a laser interference lithographic apparatus used in the manufacture of a master stamp.

The substrate was treated with a 1: 1 hydrochloric acid and hydrogen peroxide mixture and ultrasonically cleaned for 10 minutes in acetone, isopropyl alcohol and deionized water to remove contaminants.

Finally, it was dried with dry nitrogen gas before laser interference lithography.

The glass substrate was coated with an adhesion promoter HDMS (hexamethyldisilazane, Fluka) to a thickness of 20nm and then annealed for 5 minutes.

A positive resist (AZ6612, Clariant) mixed with thinner (AZ1512, Clariant) at a volume ratio of 2: 1 was spin coated onto the HDMS layer at a thickness of 230 nm.

An interference lithography method was used with the incident angle of 32.79 ° to form repeated photoresist pillar patterns having a diameter of 150 nm and a pitch size of 300 nm.

Irradiation of a UV laser beam from a He-Cd ion laser generator through a spatial filter consisting of several lenses and one pin hole at 10 μm in diameter where diffraction limited beam enhancement occurs at the end. It was.

The enhanced beam was then projected onto an angle bracket with the specimen holder and Lloyd mirror placed perpendicular to each other.

The first beam directly incident from the laser generator and the second beam reflected from the Lloyd's mirror met each other and were subjected to constructive and extinction interference for 10 seconds on the resist.

After the first exposure, the specimen was rotated 90 ° and subjected to another exposure to form a pillar image with a resist layer.

After the development process with MIF 500 solution (Clariant) for 35 seconds at room temperature, the fabricated resist pillar patterns are baked for 5 minutes at 140 ℃ on a hot plate to serve as an etching mask in the subsequent etching process.

In order to transfer the resist pillar patterns onto the silicon nitride (Si ₃ N ₄ ) layer, a dry etching process was performed with a CHF ₃ / O ₂ gas mixture at 100 W, 100 mTorr for 65 seconds.

The etching rate was 2.3 nm / s and pillars with an aspect ratio of about 1 were created after removing the resist with a piranha solution.

FIG. 4 shows a field emission scanning electron microscope image of a transparent silicon nitride (Si ₃ N ₄ ) master stamp having repeated pillars having a diameter of 150 nm and a pitch size of 300 nm prepared by Preparation Example 1.

Production Example 2: Nano-scale Hole Pattern Formation Method

First, before performing imprinting using the prepared master stamp, a self-adhesive monolayer (SAM) is formed on the fabricated stamp surface so that the stamp is easily separated from the imprinted resist layer by reducing the surface energy of the stamp surface. Coated.

The silicon substrate was cleaned by the same cleaning method as mentioned for the silicon nitride (Si ₃ N ₄ ) film.

For imprinting, a two-layer process of resist and underlayer was adopted and LOL 1000 (Shipley Ltd.) was used as underlayer.

The thickness of the underlayer formed at a rotational speed of 3000 rpm for 30 seconds was 80 nm and baked at 120 ° C. for 180 seconds on a hot plate.

After the baking process, in order to increase the surface energy, the underlayer surface was treated with oxygen plasma with an RF power source of 20 W for 10 seconds.

The higher the surface energy, the greater the adhesion between the imprinted resist layer and the LOL layer, thereby making it easier to separate the stamp from the imprinted resist as well as the anti-stick SAM on the stamp surface.

In addition, a low viscosity UV-cured resist solution consisting of UV-cured silicone based acrylate-derivative (AS9, 70wt.%, AS19, 27wt.%) And radical initiator (Irgacure 184, Ciba, 3wt.%) Was used.

The prepared imprint resist solution was coated on the underlayer for 200 seconds at a rotation speed of 6000 rpm.

UV was irradiated for 5 minutes to cure the imprint resist sandwiched between the stamp and the substrate while an imprinting pressure of 5 bars was applied by a nanoimprint machine (NANOSIS 620, Nano & Device).

Fluorocarbon (CF ₄ ) gas was used to remove the residual resist layer under the trench for 30 seconds at 20 mTorr, 20 W and the imprinted patterns were subjected to oxygen gas (O ₂₎ at 20 mTorr, 20 W for 70 seconds using selective etching. Transfer to the under layer by reactive ion etching (RIE) method.

The cured resist layer has higher oxygen plasma etching resistance than the under layer. The etching rate of the underlayer under oxygen plasma was 1.23 nm / s, which was four times faster than the 0.33 nm / s etching rate of the imprinted resist layer.

A two stage lift-off process was used for the formation of reverse patterns.

First, a 20 nm thick Au layer was deposited on the patterned substrate by an electron beam evaporator and the sample was immersed in a polymer remover (1165, Shipley Ltd.) at 120 ° C. for 180 seconds to dissolve the LOL layer. The first lift-off process was performed.

As a result, the same repeated pillar-shaped aluminum patterns as the protruding shapes on the master stamp remained.

Subsequently, after depositing a 5 nm thick layer of chromium (Cr) on a gold (Au) patterned substrate, the specimen was subjected to an aqua regia solution (37% concentrated hydrochloric acid and 70% nitric acid in volume ratio 3 :). A second lift-off process was performed to remove the gold patterns by soaking in 1) for 30 minutes.

After the second lift-off process, gold was dissolved by selective etching and chromium hole patterns remained.

The etch rate of aqua regia to gold was 10 μm / min at room temperature and chromium did not dissolve by forming a passivated layer of chromic chloride.

Finally, repeated hole-shaped chromium patterns were obtained and used as a hard etch mask during etching the silicon substrate by capacitively coupled plasma (CCP) with a mixed gas of CHF ₃ and O ₂ for 100 seconds at a 100 W RF power source. .

The etching rate of the silicon layer under the above conditions was 0.5 nm / s. Finally, the chromium mask was removed by chromium etchant (Cr-7, Cyantek, etch rate: 800 μs / min) and the corresponding hole patterns were left on the silicon substrate.

5A is a scanning electron micrograph of hole patterns formed in a polymer layer (resist) after imprinting with a pillar dot stamp. Hole patterns with a minimum residual layer thickness (10 nm or less) under the trench were formed over the entire resist surface under an imprinting pressure of 5 bars.

FIG. 5B shows that 20 nm thick gold dots were formed on the holes of the imprinted polymer template after the first lift-off process.

5C shows the chromium hole patterns after the second lift-off process (gold removal) and was used as a hard etch mask to create concave holes in subsequent silicon substrate etching.

FIG. 5D shows the final hole patterns formed on the silicon substrate after the silicon etching process and chrome mask removal. Holes having a diameter of 146 nm and a pitch size of 296 nm were formed in the silicon substrate, and had the same size as the pillars on the original master stamp. Almost identical.

In the pattern forming method of the present invention, since there is no problem of uniformity due to air generated from the hole pattern stamp, and a metal mask of the hole pattern can be made, vertical etching that is not possible in the polymer mask is possible.

The method of forming a pattern according to the present invention is a method of forming a hole pattern on a substrate using a stamp of a pillar dot pattern, and a technology capable of introducing a photonic crystal structure in the form of a negative hole into a clad layer of an electrode for a solar cell and a light emitting diode. to be.

As described above, the method of forming a pattern according to the present invention can be widely applied to the technology of forming a transparent electrode of a solar cell for increasing light absorption surface area and forming a light emitting diode cladding layer for improving light extraction efficiency.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that.

It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of the present invention is shown by the following claims rather than the above description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. .

1A to 1I are flowcharts sequentially illustrating a method of forming a hole pattern according to an exemplary embodiment of the present invention.

2A is a view showing the chemical structure of AS9 constituting the resist layer of the present invention.

2B is a view showing the chemical structure of AS19 constituting the resist layer of the present invention.

Figure 2c is a view showing the chemical structure of 1-hydroxy-cyclohexyl-phenyl-ketone constituting the resist layer of the present invention.

3 is a schematic diagram of a laser interference lithography apparatus for fabricating a master stamp used in a method of forming a pattern according to an embodiment of the present invention.

4 is a field emission scanning electron micrograph of a master stamp prepared by laser interference lithography, which is used in the method for forming a pattern according to an embodiment of the present invention.

5A is a scanning electron micrograph showing holes imprinted in a polymer layer using a master stamp having pillars.

5B is a scanning electron micrograph showing a gold (Au) dot pattern after the first lift-off process.

5C is a scanning electron micrograph showing a chrome hole pattern after the second lift-off process (gold removal).

5D is a scanning electron micrograph of hole patterns formed on a silicon substrate after an etching process and chrome mask removal.

<Description of Symbols for Main Parts of Drawings>

10 substrate 20 underlayer

30: resist layer 40: stamp

50: first metal layer 60: second metal layer

Claims (6)

Providing a substrate having a polymer layer formed thereon; Forming a predetermined pattern on the polymer layer; Forming a first metal layer on the substrate and the polymer layer on which the predetermined pattern is formed; Removing the polymer layer in which the predetermined pattern is formed; Forming a second metal layer on the substrate and the first metal layer formed on the substrate; Removing the first metal layer formed on the substrate and etching the substrate using the second metal layer formed on the substrate as a mask; And Removing the second metal layer formed on the substrate. The method of claim 1, The method of forming a pattern on the polymer layer may include imprinting a stamp in the form of a pillar dot on the polymer layer. The method of claim 1, In the step of forming the first metal layer, the first metal layer is a pattern forming method of the substrate, characterized in that the aluminum (Al) or gold (Au). The method of claim 1, In the forming of the second metal layer, the second metal layer is a pattern forming method of the substrate, characterized in that the chromium (Cr). The method of claim 1, The polymer layer comprises a poly (dimethylsiloxane), ethylene glycol dimethacrylate and 1-hydroxy-cyclohexyl-phenyl-ketone or AS9, AS19 and 1-hydroxy-cyclohexyl-phenyl-ketone. The method of claim 1, In the providing of the substrate, wherein the polymer layer has a two-layer structure of a resist layer and an under layer.

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