KR101053662B1 - Phase change memory device - Google Patents

Abstract

The present invention provides a phase change memory device capable of reducing the number of fuse sets required during a repair operation by preventing a word line of a neighboring memory block caused by a defect such as a short circuit of a global row decoder line. To this end, the present invention provides a memory block comprising a plurality of memory cells connected between a plurality of bit lines and a plurality of word lines, respectively; A plurality of local row lines for supplying a first driving voltage to the plurality of word lines; A plurality of first switching elements for connecting the plurality of word lines and the plurality of local row lines; And a global row decoder line configured to control the plurality of first switching elements and to be disposed between the plurality of word lines.

Phase Change Memory Devices, Global Low Decoder Lines

Description

Phase change memory device {PHASE CHANGE RANDOM ACCESS MEMORY}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor layout design, and more particularly, to a layout structure of a global row decoder line (GXDECL) and a local row / column switching element of a phase-change random access memory (PRAM) device. It is about.

In general, a semiconductor memory device may include a flash memory and a volatile memory device such as a dynamic random access memory (DRAM) device or a static random access memory (SRAM) device according to whether data stored in a memory cell is maintained when power is cut off from the outside. It may be classified into a nonvolatile memory device such as a FLASH memory device or an electrically erasable programmable read-only memory (EEPROM) device.

In nonvolatile memory devices, flash memory devices are widely used in digital cameras, mobile phones, or electronic devices such as MP-3 (MPEG Audio Layer-3). However, since a flash memory device requires a relatively long time in writing or reading data, a magnetic random access memory (MRAM) device, a ferroelectrics random access memory (FRAM) device, or a phase-RAM (PRAM) device is used to replace the flash memory device. New semiconductor devices such as change random access memory devices have been developed.

PRAM devices (hereinafter, referred to as phase change memory devices) are classified into an amorphous state and a polycrystalline state according to phase transitions of a chalcogenide compound constituting a phase change layer, and store data using the resistance difference of these states. Device. That is, the phase change memory device uses a reversible phase change of a phase change layer made of germanium-antimony-tellurium (Ge-Sb-Te, GST), which is a chalcogen compound, according to an applied pulse (current) to convert the data into a logical value ' Save as 0 'and' 1 '. For example, when a reset pulse (reset current) is applied, the phase change layer melts into an amorphous high resistance state, that is, a reset state ('1'). In addition, when a set pulse (set current) is applied to the phase change layer, the phase change layer becomes a polycrystalline low resistance state, that is, a set state ('0').

FIG. 1 is a diagram illustrating a phase change memory device according to the related art, and FIG. 2 is a diagram illustrating 'BLK0' and 'BLK1' among the memory blocks BLK0 to BLKn illustrated in FIG. 1.

1 and 2, a phase change memory device according to the related art includes a memory cell array 100 including a plurality of memory blocks BLK0 to BLKn. Each memory block includes a plurality of memory cells 101 connected between a plurality of bit lines LBL0 to LBL7 and word lines GWL0 to GWL7, respectively. Here, the memory block refers to a random partition of the memory cell array 100, and its size may vary according to design. For example, the memory block includes memory cells selected by eight word lines. The memory cell 101 is composed of one diode and one variable resistor.

In addition, the phase change memory device according to the related art may include a plurality of local low switching devices LXST0 to which transfer driving voltages respectively transmitted through the local low lines LXL0 to LXL7 to the word lines GWL0 to GWL7 during a memory cell operation. LXST7) (hereinafter referred to as first switching element). Also, a plurality of global row decoder lines connected in common with gates of the first switching elements LXST0 to LXST7 transfer the row addresses provided from the row decoders (not shown) to the first switching elements LXST0 to LXST7. Includes (GXDEL0 to GXDELn).

Each of the global row decoder lines GXDEL0 to GXDELn receives a row address supplied from the row decoder and simultaneously transmits the row addresses to the gates of the first switching elements LXST0 to LXST7. The total number of such global row decoder lines corresponds to the number of memory blocks, and one global row decoder line is disposed between each memory block. The first switching elements LXST0 to LXST7 correspond one-to-one with the word lines GWL0 to GWL7 of each memory block.

In addition, the phase change memory device according to the related art includes a plurality of local column switching elements LYST0 to LYST7 (hereinafter referred to as a second switching element) connecting the bit lines LBL0 to LBL7 and each memory cell 101. It includes one common bit line GBL connected in common with the bit lines LBLO to LBL7. The second switching elements LYST0 to LYST7 operate by column addresses respectively transmitted through the global column decoder lines GYDECL0 to GYDECL7. That is, the second switching elements LYST0 to LYST7 are selected by column addresses transferred through the global column decoder lines GYDECL0 to GYDECL7 to connect the bit lines LBL0 to LBL7 and the memory cell 101. .

A phase change memory device according to the related art having such a structure uses a variable resistor as a data storage, and reversible characteristics of the variable resistor according to the amount of current applied to the memory cell 101 through the bit lines LBL0 to LBL7. A write operation is performed by using. In other words, when a write operation is performed on an arbitrary memory cell, if a current is supplied through the selected bit line, and the potential of the selected word line transitions to a logic low or ground voltage level, a forward bias is applied to the diode so that A current path in the direction of the word line is formed. At this time, a phase change occurs in the variable resistor connected to the anode terminal of the diode to become 'set' in a low resistance state or 'reset' in a high resistance state.

As described above, the phase change memory device according to the related art has a structure in which global row decoder lines GXDECL0 to GXDECL7 are arranged one by one between each memory block. For example, as shown in FIG. 2, the global row decoder line GXDECL0 is disposed between the memory blocks BLK0 and BLK1. Accordingly, when a defect such as a short circuit occurs in the global row decoder line GXDECL0 due to a lack of process margin in the manufacturing process, the word of the memory block BLK0 as well as the words of the neighboring memory block BLK1. It also affects the lines, causing badness. As a result, an additional fuse set is required for a repair operation on the memory cells in the neighboring memory block BLK1, which adversely affects manufacturing cost and area.

Accordingly, the present invention has been proposed to solve the problems according to the prior art, and it is necessary to prevent the failure of word lines of a neighboring memory block caused by a defect such as a short circuit of a global row decoder line. It is an object of the present invention to provide a phase change memory device capable of reducing the number of fuse sets.

According to an aspect of the present invention, there is provided a memory block including a plurality of memory cells connected between a plurality of bit lines and a plurality of word lines, respectively; A plurality of local row lines for supplying a first driving voltage to the plurality of word lines; A plurality of first switching elements for connecting the plurality of word lines and the plurality of local row lines; And a global row decoder line configured to control the plurality of first switching elements and to be disposed between the plurality of word lines.

As described above, according to the present invention, by placing a global row decoder line between word lines of each memory block, the word lines of neighboring memory blocks generated due to a defect such as a short circuit of the global row decoder line are generated. It is possible to reduce the number of fuse sets required during the repair operation by preventing the failure at the source.

In addition, according to the present invention, by changing the gate structure of the first and second switching elements from the finger shape to the bar shape, even if one of the via contacts is not formed stably stably the first and second switching elements It can be turned on to prevent the memory cell from failing.

Hereinafter, with reference to the accompanying drawings, the most preferred embodiment of the present invention will be described.

In the drawings, pitches of gates and lines are exaggerated for clarity and convenience of explanation. Further, eight word lines, bit lines, first and second switching elements are shown, respectively, but he is not limited in number as an example. In addition, in the drawings, the same reference numerals denote the same components.

In the description of the specification, 'word line' and 'bit line' are metal wires having a hierarchical structure, wherein 'word line' is a global word line and a local word line, and 'bit line' is a global bit line and a local bit line. It may have a structure disposed on different wiring layers. For example, 'GWL0 to GWL7' correspond to global word lines, and 'LBL0 to LBL7' correspond to local bit lines. In addition, the "global" and "local" described in the specification is named according to the arbitrarily divided according to the presence or absence of the connection with the pad (pin) or the length thereof.

Example

3 is a diagram illustrating a phase change memory device according to an exemplary embodiment of the present invention, and FIG. 4 is a diagram illustrating 'BLK0' and 'BLK1' among the memory blocks BLK0 to BLKn illustrated in FIG. 3. .

3 and 4, a phase change memory device according to an embodiment of the present invention includes a plurality of memory blocks BLK0 to BLKn. Each memory block includes a plurality of memory cells 101 connected between a plurality of bit lines LBL0 to LBL7 and word lines GWL0 to GWL7, respectively. Also, a plurality of global row decoder lines GXDECL0 to GXDECLn (where n is a natural number) interposed between the word lines GWL0 to GWL7 to cross each memory block.

The word lines GWL0 to GWL7 of each memory block are divided into two parts based on the respective global row decoder lines GXDECL0 to GXDECLn. That is, the global row decoder line is disposed at a point that is half of the word lines. For example, in the case of the memory block BLK0, the global row decoder line GXDECL0 is disposed between the word line GWL3 and the word line GWL4.

The global row decoder lines GXDECL0 to GXDECLn are arranged in parallel with the word lines GWL0 to GWL7 to cross the memory block. That is, the global row decoder lines GXDECL0 to GXDECLn are arranged in parallel with the longitudinal direction (extension direction) of the word lines GWL0 to GWL7. In addition, the global row decoder lines GXDECL0 to GXDECLn are arranged to intersect the bit lines LBL0 to LBL7. That is, the global row decoder lines GXDECL0 to GXDECLn are arranged to cross the bit lines LBL0 to LBL7 in the memory blocks BLK0 to BLKn.

The bit lines LBL0 to LBL7 are disposed to intersect the word lines GWL0 to GWL7 in the vertical direction. Each memory cell 101 is connected to a point where bit lines LBL0 to LBL7 and word lines GWL0 to GWL7 cross each other. The memory cell 101 includes a diode and a variable resistor connected between a word line and a bit line. The cathode of the diode is connected to the word line and the anode is connected to one end of the variable resistor. The variable resistor is connected at one end to the anode of the diode and at the other end to the bit line. The variable resistor is made of a phase change material.

As a phase change material, germanium-antimony-tellurium (Ge-Sb-Te, GST), a chalcogenide compound, is used. However, the present invention is not limited to the chalcogen compound alone, and any material showing relatively high resistance or low resistance according to the changed state of the crystal and the changed state of the crystal may be used. For example, GaSb, InSb, InSe, Sb ₂ Te ₃ , GeTe, which combines two elements, GeSbTe, GaSeTe, InSbTe, SnSb ₂ Te ₄ , InSb ₂ Te ₄ , InSbGe, which combines three elements, four elements One material selected from the group consisting of AgInSbTe, (GeSn) SbTe, GeSb (SeTe), Te ₈₁ Ge ₁₅ Sb ₂ S ₂ , and the like may be used.

In addition, the phase change memory device according to an exemplary embodiment of the present invention may be configured by a plurality of local row lines LXL0 to LXL7 transferring first driving voltages and row addresses transmitted from global row decoder lines GXDECL0 to GXDECLn. A plurality of first switching elements LXST0 to LXST7 which are selected to transfer the first driving voltage to corresponding word lines, are further provided.

FIG. 5 is a diagram illustrating an arrangement structure of the first switching elements LXST0 to LXST7, the word lines GWL0 to GWL7, and the global row decoder line GXDECL0 shown in FIG. 3. A cross-sectional view showing only 'LXST0' along the II 'cut line shown. In FIG. 6, the word lines GWL0 to GWL7 and the global row decoder line GXDECL0 are not illustrated.

5 and 6, the first switching elements LXST0 to LXST7 may include a plurality of active regions 206 arranged in the longitudinal direction of the word lines GWL0 to GWL7, and word lines GWL0 to GWL7. And a gate 205 formed to cross the active regions 206 in the longitudinal direction of the cross section.

The active regions 206 exist as many as the first switching elements LXST0 to LXST7. That is, one active region 206 exists for each of the first switching elements LXST0 to LXST7. As shown in FIG. 6, the active regions 206 are formed by implanting n-type or p-type impurity ions into the semiconductor substrate 200. In this case, a well (not shown) having a different conductivity type from the active regions 206 is formed in the semiconductor substrate 200. The active regions 206 are formed in a different conductivity type from the wells, and have a high doping concentration. The gate 205 is disposed in parallel with the word lines GWL0 to GWL7 to overlap the active regions 206, and is connected to each other between the active regions 206 to have a ladder structure.

In addition, a phase change memory device according to an exemplary embodiment of the present invention may include a plurality of first via contacts 208 that connect word lines GWL0 to GWL7 and active regions 206 with each other, and a global row decoder. The semiconductor device may further include a plurality of second via contacts 210 connecting the line GXDECL0 and the gate 205 to each other. In this case, the number of the first and second via contacts 208 and 210 is not limited and may be appropriately selected according to the design of the device. The second via contacts 210 are connected to a point where the gates 205 extending in two lines are connected to each other. That is, the second via contacts 210 are disposed to overlap with the active regions 206.

In addition, the phase change memory device according to an exemplary embodiment of the present invention may be disposed at a lower end of the memory block BLKn disposed last in the memory blocks BLK0 to BLKn disposed in the length direction of the bit lines LBL0 to LBL7. Selected by a plurality of global column decoder lines GYDECL0 to GYDECL7 arranged in parallel with the global row decoder lines GXDECL0 to GXDECL0n, and column addresses transferred from the global column decoder lines GYDECL0 to GYDECL7, respectively. The apparatus further includes a plurality of second switching elements LYST0 to LYST7 respectively transferring the driving voltages to the bit lines LBL0 to LBL7. In this case, the second driving voltage is a voltage input to the cathode of the diode of the memory cell 101 and becomes a ground voltage or a power supply voltage.

In addition, the phase change memory device according to the embodiment of the present invention is disposed in parallel with the bit lines LBL0 to LBL7 to cross the memory blocks BLK0 to BLKn, and the second switching elements LYST0 to LYST7. A common bit line (GBL) for transmitting the second driving voltage to the) is further provided. The common bit line GBL is disposed to intersect the global row decoder lines GXDECL0 to GXDECLn and the global column decoder lines GYDECL0 to GYDECL7.

FIG. 7 is a diagram illustrating an arrangement structure of the second switching elements LYST0 to LYST7, the bit lines LBL0 to LBL7 and the global column decoder lines GYDECL0 to GYDECL7 shown in FIG. 3. FIG. 7 is a cross-sectional view illustrating only 'LYST0' along the cut line II-II 'of FIG. 7. In FIG. 8, the bit lines LBL0 to LBL7 and the global column decoder lines GYDECL0 to GYDECL7 are not shown.

7 and 8, the second switching elements LYST0 to LYST7 may include a plurality of active regions 306 arranged in the longitudinal direction of the bit lines LBL0 to LBL7, and bit lines LBL0 to LBL7. A plurality of gates 305 are formed on the active regions 306 in the longitudinal direction of the < RTI ID = 0.0 >

The gates 305 are disposed in two active patterns 306 symmetrically separated from each other, the overall shape of the pattern has a 'II' shape. In addition, the gates 305 may be disposed to be symmetrically separated from each other in the form of a comb tooth in each of the active regions 306. That is, each pattern includes a first line extending in the longitudinal direction of the global column decoder line and a second line extending in the longitudinal direction of the bit line from the first line, wherein the number of the second lines is one. Or more than that can form a comb overall. The active regions 306 exist as many as the second switching elements LYST0 to LYST7.

In addition, the phase change memory device may include a plurality of first via contacts 308 connecting the bit lines LBL0 to LBL7 and the active regions 306, and a global column decoder line ( A plurality of second via contacts 310 may be further provided to connect GYDECL0 to GYDECL7 and the gates 305, respectively. In this case, the number of the first and second via contacts 208 and 210 is not limited and may be appropriately selected according to the design of the device.

5 to 8, the first and second switching elements LXST0 to LXST7 and LYST0 to LYST7 are formed on the same semiconductor substrate. However, in the present specification, for convenience of description, the semiconductor substrates 200 and 300 having different reference numerals are illustrated as being formed.

In addition, the first and second via contacts 208, 308, 210, and 310 may be formed on the same layer as each other or may be formed on different layers. If some of the first via contacts 208 and 308 are shown overlapping the gate in the figure, they are bypassed so as not to be directly connected to the gate and connected to the active regions 206 and 306 respectively. The first and second via contacts 208, 308, 210, and 310 are made of a conductive material and are connected to the corresponding active regions or gates through an interlayer insulating film made of an insulating material.

9 and 10 illustrate an arrangement structure of the first and second switching elements LXST0 to LXST7 and LYST0 to LYST7 shown in FIGS. 5 to 8, and first and second structures according to the prior art shown in FIGS. 1 and 2. FIG. 4 is a diagram illustrating a comparative arrangement of the second switching elements.

FIG. 9 is a view illustrating an arrangement of first switching elements LXST0 to LXST7, word lines GWL0 to GWL7, and global row decoder line GXDECL0 according to the prior art, and FIG. 10 according to the prior art. FIG. 2 is a diagram illustrating an arrangement structure of second switching elements LYST0 to LYST7, bit lines LBL0 to LBL7, and global column decoder lines GYDECL0 to GYDECL7.

9 and 10, in the first and second switching devices LXST0 to LXST7 and LYST0 to LYST7 according to the related art, gates 405 and 505 are formed in a finger type, respectively. In FIG. 10, two patterns of the gates 505 of the second switching elements LYST0 to LYST7 are illustrated in the form of bars, but in fact, both ends of the two patterns are connected to each other to have a finger shape. Since the process margin is difficult to secure in the gate of the finger structure, the first and second via contacts 408 and 410 and the via contacts 508 may not be stably formed. As such, when none of the first and second via contacts 408 and 410 and the via contacts 508 are stably formed, one finger transistor constituting the transistor is not turned on so that the transistor This results in an effect of reducing the width of the phase change. As a result, current supply through the first and second switching elements LXST0 and LYST0 is not smooth, which makes it difficult to supply current for the reset operation of the variable resistor. The problem is that a memory cell of a process is failed.

In contrast, as illustrated in FIGS. 5 and 7, in the phase change memory device according to the exemplary embodiment of the present invention, the gates 205 of the first switching elements LXST0 to LXST7 are connected to the word lines GWL0 to GWL7. While forming the bar extending in the longitudinal direction of the, while forming the gate 505 of the second switching elements (LYST0 ~ LYST7) each separated from each other 'II' shape due to the lack of process margin And even if any one of the second via contacts 208, 210, 308, and 310 is not stably formed, there is no problem in operation because the transistor is turned on by surrounding via contacts. Accordingly, the present invention can improve the process margin than the arrangement of the first and second switching elements according to the prior art shown in FIGS. 9 and 10.

As described above, although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not for the purpose of limitation. As such, those skilled in the art may understand that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a view for explaining a phase change memory device according to the prior art.

FIG. 2 is a diagram illustrating 'BLK0' and 'BLK1' among the memory blocks BLK0 to BLKn illustrated in FIG. 1.

3 illustrates a phase change memory device according to an embodiment of the present invention.

FIG. 4 is a diagram illustrating 'BLK0' and 'BLK1' among the memory blocks BLK0 to BLKn illustrated in FIG. 3.

FIG. 5 is a diagram illustrating the layout of the first switching elements LXST0 to LXST7, the word lines GWL0 to GWL7, and the global row decoder line GXDECL0 shown in FIG. 3.

FIG. 6 is a cross-sectional view showing only 'LXST0' along the line II ′ of FIG. 5;

FIG. 7 is a diagram illustrating a layout of second switching elements LYST0 to LYST7, bit lines LBL0 to LBL7, and global column decoder lines GYDECL0 to GYDECL7 shown in FIG. 3.

FIG. 8 is a cross-sectional view of only 'LYST0' along a cutting line II-II 'shown in FIG. 7;

9 is a diagram illustrating a layout of first switching elements LXST0 to LXST7, word lines GWL0 to GWL7, and global row decoder line GXDECL0 according to the prior art.

FIG. 10 illustrates a layout of second switching elements LYST0 to LYST7, bit lines LBL0 to LBL7, and global column decoder lines GYDECL0 to GYDECL7 according to the related art.

<Explanation of symbols for the main parts of the drawings>

GWL0 ~ GWL7: Word line

LBL0 ~ LBL7: Bit line

GXDECL0 ~ GXDECLn: Global Low Decoder Line

GYDECL0 ~ GYDECL7: Global column decoder line

LXST0 to LXST7: first switching element

LYST0 to LYST7: second switching element

GYDECL0 ~ GYDECL7: Global column decoder line

BLK0 ~ BLKn: Block

100: memory cell array

101: memory cell

205, 305, 405, 505: Gate

206, 306, 406, 506: active area

Via Contact: 208, 210, 308, 310, 408, 410, 508

202 and 302: device isolation membrane

200, 300: semiconductor substrate

Claims (24)

A memory block including a plurality of memory cells connected between the plurality of bit lines and the plurality of word lines, respectively; A plurality of local row lines for supplying a first driving voltage to the plurality of word lines; A plurality of first switching elements for connecting the plurality of word lines and the plurality of local row lines; And A global row decoder line controlling the plurality of first switching elements and disposed between the plurality of word lines Phase change memory device having a. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, And the word lines are divided into two parts based on the global row decoder line. Claim 3 was abandoned when the setup registration fee was paid. The method of claim 1, And the global row decoder line is disposed in parallel with the word lines. Claim 4 was abandoned when the registration fee was paid. The method of claim 1, Claim 5 was abandoned upon payment of a set-up fee. The method of claim 1, And the bit lines are arranged to intersect the word lines. delete Claim 7 was abandoned upon payment of a set-up fee. The method of claim 1, The first switching elements, A plurality of active regions arranged in the longitudinal direction of the word lines; And A gate formed to cross the active regions in a length direction of the word lines Phase change memory device having a. Claim 8 was abandoned when the registration fee was paid. The method of claim 7, wherein And the active regions are present as many as the number of the first switching elements. Claim 9 was abandoned upon payment of a set-up fee. The method of claim 7, wherein And the gates are arranged in parallel with the word lines to overlap the active regions, and connected to each other between the active regions to form a ladder structure. Claim 10 was abandoned upon payment of a setup registration fee. The method of claim 7, wherein And the active region is formed by implanting impurity ions into a semiconductor substrate. Claim 11 was abandoned upon payment of a setup registration fee. The method of claim 7, wherein A plurality of first via contacts connecting the word lines and the active regions one to one; And A plurality of second via contacts connecting the global row decoder line and the gate electrode Phase change memory device further comprising. Claim 12 was abandoned upon payment of a registration fee. The method of claim 11, And the second via contacts are disposed to overlap between the active regions. Claim 13 was abandoned upon payment of a registration fee. The method of claim 1, And a plurality of memory blocks arranged in the longitudinal direction of the bit lines. Claim 14 was abandoned when the registration fee was paid. The method of claim 13, Claim 15 was abandoned upon payment of a registration fee. The method of claim 13, A plurality of global column decoder lines arranged in a direction parallel to the global row decoder line at a lower end of the memory block disposed last of the memory blocks; And A plurality of second switching elements each selected by a column address transferred from the global column decoder lines to transfer a second driving voltage to the bit lines, respectively; Phase change memory device further comprising. Claim 16 was abandoned upon payment of a setup registration fee. The method of claim 15, And a common bit line disposed in a direction parallel to the bit lines to cross the memory blocks, and configured to transfer the second driving voltage to the second switching elements. Claim 17 has been abandoned due to the setting registration fee. The second switching elements, A plurality of active regions arranged in the longitudinal direction of the bit lines; And A plurality of gates respectively formed on the active regions in a length direction of the bit lines; Phase change memory device having a. Claim 18 was abandoned upon payment of a set-up fee. The method of claim 17, And the gates are symmetrically separated from each other by two patterns for each of the active regions. Claim 19 was abandoned upon payment of a registration fee. The method of claim 18, The overall shape of the pattern has a 'II' shape of the phase change memory device. Claim 20 was abandoned upon payment of a registration fee. The method of claim 17, And the gates are symmetrically separated from each other in a comb form in each of the active regions. Claim 21 has been abandoned due to the setting registration fee. The method of claim 17, And the active regions are present as many as the number of second switching elements. Claim 22 is abandoned in setting registration fee. The method of claim 17, A plurality of first via contacts connecting the bit lines and the active regions, respectively; And A plurality of second via contacts connecting the global column decoder lines and the gates, respectively; Phase change memory device further comprising. Claim 23 was abandoned upon payment of a set-up fee. The method of claim 1, The memory cell, A diode connected to the word line; And A variable resistor connected between the diode and the bit line Phase change memory device having a. Claim 24 is abandoned in setting registration fee. The method of claim 23, wherein And the variable resistor is made of a phase change material.

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