KR101035915B1 - Liquid Crystal Display Device - Google Patents

Liquid Crystal Display Device Download PDF

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Publication number
KR101035915B1
KR101035915B1 KR1020030098059A KR20030098059A KR101035915B1 KR 101035915 B1 KR101035915 B1 KR 101035915B1 KR 1020030098059 A KR1020030098059 A KR 1020030098059A KR 20030098059 A KR20030098059 A KR 20030098059A KR 101035915 B1 KR101035915 B1 KR 101035915B1
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South Korea
Prior art keywords
gate
formed
data
wiring
link
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KR1020030098059A
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Korean (ko)
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KR20050066712A (en
Inventor
박희영
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엘지디스플레이 주식회사
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Abstract

The present invention relates to a liquid crystal display device in which a structure of a link wiring portion in which a seal pattern is formed is changed to eliminate the step of the seal pattern, thereby preventing lifting, and includes first and second substrates in which a display part and a non-display part of the outer part are defined; A plurality of gate lines and data lines vertically intersecting with each other on the first substrate in the display unit, and a gate pad applying a driving signal to the gate lines and data lines on a non-display unit on the first substrate, respectively; A portion and a data pad portion, a gate link wiring connecting the gate wiring and the gate pad portion, a data link wiring connecting the data wiring and the data pad portion, and a gate link wiring under the seal pattern. And a passivation layer formed with a hole between the adjacent gate link wires, and between the first and second substrates. And a seal pattern passing through the gate link wires and the data link wires at a boundary between the display unit and the non-display unit, and a semiconductor layer formed under the passivation hole.
Line on glass (LOG), pads, links, seal patterns, benzocyclobutene (BCB)

Description

Liquid crystal display device

1 is a cross-sectional view of a general liquid crystal display device

2 is a plan view of a conventional COG type liquid crystal display device.

3 is a plan view of a conventional LOG-A type liquid crystal display device.

4 is a plan view showing a problem of the conventional LOG-B type liquid crystal display device.

5 is an enlarged plan view of a portion E of FIG. 4;

6 is a cross-sectional view taken along line II ′ of FIG. 5.

7 is a structural cross-sectional view taken along line II-II 'of FIG. 5.

8 is a plan view showing a liquid crystal display of the present invention.

9 is an enlarged plan view of a portion F of FIG. 8;

10 is a cross-sectional view taken along line III-III ′ of FIG. 9;

FIG. 11 is a cross-sectional view taken along line IV-IV 'of FIG.

12 is a cross-sectional view illustrating a line III-III ′ of FIG. 9 according to another embodiment.

FIG. 13 is a structural cross-sectional view taken along line IV-IV 'of FIG. 10 according to another embodiment.

Description of the Related Art [0002]

150: lower substrate 151: pixel portion

152: gate wiring 153: data wiring                 

154: gate link wiring 155: data link wiring

156: gate insulating film 157: protective film

158: gate pad wiring 160: upper substrate

170: seal pattern 180: semiconductor layer

181: gate driver IC 182: source driver IC

190: LOG wiring pattern 200: source / drain electrode pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device in which the structure of the link wiring portion on which the seal pattern is formed is changed to eliminate the step of the seal pattern to prevent the lifting phenomenon.

Hereinafter, a liquid crystal display according to the related art will be described with reference to the accompanying drawings.

1 is a cross-sectional view of a general liquid crystal display.

As shown in FIG. 1, the liquid crystal display includes a first area A in which an image is represented and a pad (not shown) connected to a driving circuit for applying a signal to the first area A is located. It is divided into two areas (B).

In the lower region of the first region A, a gate electrode 11 made of a conductive material such as a metal is formed on the transparent first substrate 10, and a silicon nitride film (SiNx) or a silicon oxide film (SiO 2) is formed thereon. The gate insulating film 12 made of) covers the gate electrode 11. An active layer 13 made of amorphous silicon is formed on the gate insulating layer 12 on the gate electrode 11, and an ohmic contact layer 14 made of amorphous silicon doped with impurities is formed thereon.

Source and drain electrodes 15a and 15b formed of a conductive material such as a metal are formed on the ohmic contact layer 14, and the source and drain electrodes 15a and 15b are formed together with the gate electrode 11. ).

Although not shown, the gate electrode 11 is connected to the gate wiring, the source electrode 15a is connected to the data wiring, and the gate wiring and the data wiring are orthogonal to each other to define the pixel region.

Subsequently, a passivation layer 16 made of a silicon nitride layer, a silicon oxide layer, or an organic insulating layer is formed on the source and drain electrodes 15a and 15b, and the passivation layer 16 has a contact hole 16c exposing the drain electrode 15b. .

A pixel electrode 17 made of a transparent conductive material is formed in the pixel area above the passivation layer 16, and the pixel electrode 17 is connected to the drain electrode 15b through the contact hole 16c.

Meanwhile, a transparent second substrate 20 spaced apart from the first substrate 10 at a predetermined interval is disposed on the first substrate 10, and a black matrix 21 is disposed on an inner surface of the second substrate 20. ) Is formed at a position corresponding to the thin film transistor T, although not shown, the black matrix 21 covers portions other than the pixel electrode 17. The color filter 22 is formed under the black matrix 21. The color filter 22 sequentially repeats red, green, and blue colors, and one color corresponds to one pixel area. The common electrode 23 made of a transparent conductive material is formed under the color filter 22.

The liquid crystal layer 30 is injected between the two substrates 10 and 20.

Here, the common insulating film 23 of the gate insulating film 12, the protective film 16, and the second substrate 20 on the first substrate 10 extends to the second region B, and the second region B A seal pattern 40 is formed between the first substrate 10 and the second substrate 20 to form a gap for injecting the liquid crystal and prevent leakage of the injected liquid crystal.

Such a liquid crystal display includes a process of manufacturing a lower substrate on which a thin film transistor and a pixel electrode are arranged, a process of manufacturing an upper substrate on a top including a color filter and a common electrode, an arrangement of the two substrates manufactured, and a It is formed by a liquid crystal cell process consisting of injection, encapsulation, and polarizer attachment.

Meanwhile, the liquid crystal display further includes a driver for driving the thin film transistor.

The driver unit includes a driver circuit (hereinafter referred to as a driver integrated circuit) for applying a signal to the wiring of the liquid crystal display device, and according to a method of packaging the driver IC in the liquid crystal display device, the chip on glass (COG: chip on glass), tape carrier package (TCP), chip on film (COF).                         

The COG method is a method in which a driver IC is attached to a lower substrate of a liquid crystal display device to directly connect an output electrode of the driver IC to a wiring pad on the lower substrate. The COG method is simple in structure and simple in manufacturing. There is an advantage.

2 is a plan view of a conventional COG type liquid crystal display device.

As shown in FIG. 2, the conventional COG type liquid crystal display includes a lower substrate 50 and an upper substrate 60, and the lower substrate 50 has a larger area than the upper substrate 60. A seal pattern 70 is formed at an outer side between the two substrates 50 and 60, and liquid crystal is injected into the seal pattern 70 between the two substrates 50 and 60, although not shown. The inner region divided by the seal pattern 70 is a pixel portion 51 in which an image is displayed, and a plurality of gate lines 52 and data lines 53 intersect to define pixel regions, and the gate lines 52 A thin film transistor (not shown) is positioned at a portion where the data line 53 crosses each other.

Next, gate and data link wires 54 and 55 connected to the gate wire 52 and the data wire 53 are formed on the left and upper outer edges of the lower substrate 50, respectively. 55 is connected to the gate driver IC 81 and the data driver IC 82 mounted on the lower substrate 50, respectively. The gate driver IC 81 and the data driver IC 82 are connected to an external printed circuit board (PCB) (not shown), respectively, via a flexible printed circuit (FPC) (not shown). It is.

In the printed circuit board (PCB), a plurality of elements such as integrated circuits are formed on a substrate to generate various control signals and data signals for driving the liquid crystal display. At this time, the printed circuit board may be formed of a gate portion and a data portion, respectively, which are connected to each other by an FPC so that the gate signal and the data signal are organically connected, thereby supplying a signal.

As mentioned above, the seal pattern 70 forms a gap for injecting the liquid crystal and prevents leakage of the injected liquid crystal. The seal pattern 70 is formed by forming a thermosetting resin in a predetermined pattern on the lower substrate 50, and then placing and lowering the lower substrate 50 and the upper substrate 60 and pressing and curing the two substrates 50 and 60. It is made by bonding.

However, as shown in FIG. 1, the passivation layer 16 of FIG. 1 is formed on the entire surface of the lower substrate 10 of FIG. 1 to be positioned below the seal pattern 40 of FIG. 1. Recently, in order to improve the aperture ratio of a liquid crystal display device, a protective film is formed of an organic insulating film having a low dielectric constant such as benzocyclobutene (BCB), and when the protective film is formed of an organic insulating film such as BCB, Since the insulating film has poor adhesiveness with the seal pattern, a phenomenon such as bursting of the seal pattern may be caused on the upper portion of the protective film.

Therefore, when the protective film is formed of the organic insulating film, in order to prevent such a problem, the protective film of the portion where the seal pattern is formed must be removed.

On the other hand, in the recent COG method of forming the driver IC on the lower substrate, in order to simplify the structure and manufacturing process of the FPC, wiring on glass (lines on glass) connecting the gate driver IC and the data driver IC on the lower substrate (LOG) Method has been proposed and used.

3 is a plan view of a conventional LOG A type liquid crystal display device.

Since the liquid crystal display of the conventional LOG A method of FIG. 3 is the same as that shown in FIG. 2 except for the LOG wiring pattern part, the same reference numeral is assigned to the same part, and a description thereof will be omitted.

As shown in FIG. 3, a plurality of LOG wiring patterns 90 connecting the gate driver IC 81 and the data driver IC 82 are formed on the lower substrate 50 of the conventional LOG A type liquid crystal display. . The LOG wiring patterns 90 may replace the gate driver and the data driver by FPC, thereby simplifying a manufacturing process and reducing costs.

In general, FPC is made of copper, which is a metal having a very low specific resistance. Therefore, the LOG wiring pattern 90 instead of the FPC should also be made of a material having a small resistance, and the width of the pattern should be short and the length should be short.

Relatively small resistance materials include aluminum or aluminum alloy materials. Recently, as the screen is enlarged, gate wiring is formed using aluminum or aluminum alloy to prevent signal delay. Therefore, in order to reduce the number of steps while reducing the resistance of the LOG wiring pattern 90, the LOG wiring pattern 90 can be formed in the same process as the gate wiring. However, since the aluminum-based material may be easily corroded by chemicals and the like, it is preferable to form a metal layer such as molybdenum (Mo) mainly on the aluminum or aluminum alloy.

On the other hand, when forming the LOG wiring pattern 90 to the minimum length in order to reduce the resistance of the LOG wiring pattern 90 as shown, the portion of the LOG wiring pattern 90 also overlaps the seal pattern 70 Since the protective film (not shown) is formed of an organic insulating film, the protective film of the portion where the seal pattern 70 is located must be removed.

4 is a plan view illustrating a conventional LOG-B type liquid crystal display, and FIG. 5 is an enlarged plan view of a portion E of FIG. 4.

As shown in FIG. 4, the liquid crystal display of the conventional LOG-B method is substantially similar to the LOG-A method described with reference to FIG. 3. However, as shown in FIG. 5, the first and second gates adjacent to each other are enlarged. The gate driver IC may be electrically connected to each other by the source / drain metal material of the final link wire and the first link wire of each pad part P to transmit signals between adjacent first and second gate pad parts P. It is possible to embed the gate PCB into the liquid crystal panel without mounting the gate PCB to which the driving signal is applied to the outside.

However, in this case, a step of the seal pattern occurs in the gate driver ICs 81 spaced apart from each other and the link wiring portion E corresponding thereto, so that the seal pattern is not bonded horizontally, and some dropping phenomenon occurs. Happens.

This will be described in detail through the cross section of the link wiring portion between the gate pad portion and adjacent gate pad portions.

FIG. 6 is a cross-sectional view taken along line II ′ of FIG. 5, and FIG. 7 is a cross-sectional view taken along line II—II ′ of FIG. 5. Here, the gate pad wiring is formed before the gate driver IC is formed.

Referring to FIG. 6, the link wiring part corresponding to the gate pad part P is as follows.

A seal with a lower substrate (not shown, see 50 of FIG. 4, below the gate link wiring 54 in FIG. 6) between two adjacent gate link wirings 54 passing through the seal pattern 70 forming portion. In order to improve the adhesion of the pattern 70, the protective film hole 95a is formed in a predetermined width to expose the lower substrate.

Therefore, a method of forming a link wiring part corresponding to the gate pad part P will be described in detail as follows.

First, gate link wirings 54 spaced a predetermined distance from the lower substrate (not shown) are formed.

Subsequently, a gate insulating film 56 and a protective film 57 are sequentially deposited on the entire surface of the substrate on the gate link wiring 54.

Subsequently, the passivation layer 57 is selectively removed to form a passivation layer hole in such a manner that the gate link wiring 54 is not exposed. The reason why the protective film 57 is etched up to the gate insulating film 56 when forming the protective film hole 95a is that the protective film 57 is formed thicker than other layers in order to maintain a low dielectric constant. In order to etch to a predetermined width, overetching occurs, and at this time, the gate insulating film 56 is etched. The gate insulating film 56 component at this time is an inorganic insulating film such as silicon nitride film (SiNx), silicon oxide film (SiOx), or the like.                         

All of the above-described processes are performed when the thin film transistor array is formed on the lower substrate.

As such, after completing the process of forming the thin film transistor array on the lower substrate 50 and completing the process of forming the color filter array on the upper substrate 60 which is symmetrical with this, the bonding process is performed. 60 or the spacer is formed on one side of the lower substrate 50, and the seal pattern 70 is formed on the other side, and the two substrates 50 and 60 are pressed and joined so that the seal pattern 70 is a protective film hole ( 95a) Let it soak inside.

As shown in FIG. 7, the link wiring part corresponding to the portion H between the adjacent gate pad parts P is as follows.

The link wiring portion corresponding to the region H between the adjacent gate pad portions P is not located at the gate link wiring 54, and the source / drain electrode material is formed beyond the seal pattern 70. 100 is formed, and similarly, in order to improve adhesion of the seal pattern 70 to the lower substrate 50, the upper protective film 57 is etched to a predetermined width to form the protective film hole 95b.

Therefore, a method of forming a link wiring portion corresponding to the portion H between the adjacent gate pad portions P is as follows.

First, the gate insulating film 56 is sequentially deposited on the entire lower substrate (not shown).

Next, the semiconductor layer 80 and the source / drain electrode material 100 are sequentially deposited.

Next, the protective film 57 is deposited.

Next, the protective film 57 is selectively removed to form a protective film hole. As such, the reason why the protective layer 57 is etched to the source / drain electrode material 100 when forming the protective layer hole 95b is to increase the thickness of the protective layer 57 in order to maintain a low dielectric constant. ) Is etched to a predetermined width with a predetermined thickness, and overetching occurs, and the source / drain electrode material 100 is etched. In this case, the semiconductor layer 80 functions as an etch stopper when the passivation layer hole 95b is formed to prevent etching of the semiconductor layer 80.

Likewise, all of the above-described processes are performed simultaneously when forming the thin film transistor array on the lower substrate.

As such, after completing the process of forming the thin film transistor array on the lower substrate 50 and completing the process of forming the color filter array on the upper substrate 60 which is symmetrical with this, the bonding process is performed. 60 or the spacer is formed on one side of the lower substrate 50, and the seal pattern 70 is formed on the other side, and the two substrates 50 and 60 are pressed and joined so that the seal pattern 70 is a protective film hole ( 95b) Let it soak inside.

6 and 7, when the protective film holes 95a and 95b are formed, the seal pattern 70 penetrates into the protective film holes 95a and 95b to correspond to the gate pad part P. Referring to FIGS. The link wiring portion is formed to have a deeper thickness since the protective film hole 95a is further removed from the protective film hole 95b between the gate pad portions P, so that the protective film hole 95a is formed. Since the amount of the seal pattern 70 permeated therein is large, the seal pattern 70 remaining on the passivation layer 57 is left in a smaller amount than the link wiring portion corresponding to the region H between the gate pad portions.                         

As described above, a step of the seal pattern 70 passing through the link wiring part corresponding to the region H between the gate pad part P and the gate pad parts occurs, causing the lifting phenomenon.

The conventional liquid crystal display as described above has the following problems.

Steps are generated in the seal pattern passing through the link wiring portion corresponding to the area between the pad portion and the adjacent pad portion, and the floating phenomenon occurs.

An object of the present invention is to provide a liquid crystal display device which prevents the phenomenon of lifting by eliminating the step of the seal pattern by changing the structure of the link wiring portion in which the seal pattern is formed to solve the above problems.

In order to achieve the above object, a liquid crystal display of the present invention includes a plurality of first and second substrates on which a display unit and a non-display unit outside the display unit are defined, and a plurality of vertically crossing each other on the first substrate inside the display unit. A gate wiring portion and a data pad portion, a gate pad portion and a data pad portion applying a driving signal to the gate lines and data lines, respectively, on a non-display portion on the first substrate, and a gate connecting the gate line and the gate pad portion. A link layer, a data link line connecting the data line and the data pad unit, a protective layer formed to cover the gate link line under the seal pattern, and having a hole between the adjacent gate link lines; Located between the first and second substrates, the gate link wiring on the boundary between the display unit and the non-display unit And a semiconductor layer formed under the passivation layer hole.

The passivation hole is smaller than a gap between the gate link lines.

The semiconductor layer is formed to have a width wider than that of the protective film hole.

Source / drain electrode materials are formed on the semiconductor layer on both sides of the passivation hole.

The semiconductor layer is formed between the gate link wirings.

The semiconductor layer is formed on the entire lower surface of the passivation layer including the passivation layer hole.

The gate link wires respectively connected to the gate pad portions spaced apart from each other are electrically connected to each other by source / drain electrode materials.

The protective film is an organic insulating film.

Hereinafter, the liquid crystal display of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 8 is a plan view illustrating a liquid crystal display of the present invention, and FIG. 9 is an enlarged plan view of a portion F of FIG. 8.

As shown in FIG. 8, the liquid crystal display of the present invention includes a lower substrate 150 and an upper substrate 160. The lower substrate 150 has a larger area in consideration of the formation of a pad portion than the upper substrate 160. . A seal pattern 170 is formed at an outer side between the two substrates 150 and 160, and the liquid crystal is injected into the seal pattern 170 between the two substrates 150 and 160. The inner region divided by the seal pattern 170 is a pixel portion 151 in which an image is displayed, and a plurality of gate lines 152 and data lines 153 intersect to define pixel regions, and the gate lines 152. ) And the data line 153 intersect a thin film transistor (not shown).

Next, gate and data link wires 154 and 155 connected to the gate wire 152 and the data wire 153 are formed on the left and upper outer edges of the lower substrate 150, respectively. 155 is connected to the gate driver IC 181 and the data driver IC 182 mounted on the lower substrate 150, respectively.

Only the data driver IC 182 is connected to an external source printed circuit board (FPC) (not shown) through an FPC (FPC) (not shown).

In the source PCB, a plurality of elements such as integrated circuits are formed on a substrate to generate various control signals and data signals for driving the liquid crystal display.

The seal pattern 170 forms a gap for injecting the liquid crystal and prevents leakage of the injected liquid crystal. The seal pattern 170 is formed by forming a thermosetting resin in a predetermined pattern on the lower substrate 150, and then placing and lowering the lower substrate 150 and the upper substrate (160 in FIG. 8) and pressing and curing the two substrates ( 150, 160).

On the other hand, the passivation layer is formed on the entire lower substrate 150 is also located under the seal pattern 170. Recently, in order to improve the aperture ratio of a liquid crystal display device, a protective film is formed of an organic insulating film having a low dielectric constant such as benzocyclobutene (BCB), and when the protective film is formed of an organic insulating film such as BCB, Since the insulating film has poor adhesiveness with the seal pattern, a phenomenon such as bursting of the seal pattern may be caused on the upper portion of the protective film. Therefore, when the protective film is formed of an organic insulating film, in order to prevent such a problem, the protective film hole must be formed to remove the protective film at the portion where the seal pattern is formed.

In the LOG-B method, as in the LOG-A method, a plurality of LOG wiring patterns 190 are formed on the lower substrate 150 to connect the gate driver IC 181 and the data driver IC 182. The LOG wiring patterns 190 replace the conventional gate PCB and the source PCB by FPC, thereby simplifying the manufacturing process and reducing costs.

In general, FPC is made of copper, which is a metal having a very low specific resistance. Therefore, the LOG wiring pattern 190 instead of the FPC should also be made of a material having a small resistance, and the width of the pattern should be short and the length should be short.

Relatively small resistance materials include aluminum or aluminum alloy materials. Recently, as the screen is enlarged, gate wiring is formed using aluminum or aluminum alloy to prevent signal delay. Therefore, in order to reduce the number of processes while reducing the resistance of the LOG wiring pattern 190, the LOG wiring pattern 190 may be formed in the same process as the gate wiring. However, since the aluminum-based material may be easily corroded by chemicals and the like, it is preferable to further form a metal layer such as molybdenum (Mo) mainly on the aluminum or aluminum alloy.                     

On the other hand, when forming the LOG wiring pattern 190 to a minimum length in order to reduce the resistance of the LOG wiring pattern 190 as shown, the portion of the LOG wiring pattern 190 also overlaps the seal pattern 170 Since the protective film (not shown) is formed of an organic insulating film, the protective film of the portion where the seal pattern 170 is located must be removed.

In addition, as shown in FIG. 9, in the liquid crystal display of the present invention, the final link wiring and the first link wiring of each of the first and second gate pad portions P adjacent to each other are formed of a source / drain metal material in a LOG-B manner. Electrically connected, the signal between the adjacent first and second gate pad portion (P) is transmitted, the liquid crystal of the gate PCB without mounting the gate PCB for applying a drive signal to the gate driver IC 181 to the outside It can be built into the panel.

In the liquid crystal display of the present invention, the seal pattern passing through the link wiring part by changing the pattern of the link wiring part corresponding to the region H between the link wiring part corresponding to the gate pad part P and the adjacent gate pad parts ( The step of 170 is eliminated, which will be described in detail through the cross section of the link wiring portion corresponding to the region H between the gate pad portion P and the adjacent gate pad portions.

FIG. 10 is a cross-sectional view taken along line III-III 'of FIG. 9, and FIG. 11 is a cross-sectional view taken along line IV-IV ′ of FIG. 9. Here, the gate pad wiring is formed before the gate driver IC is formed.

A link wiring part corresponding to the gate pad part P will be described with reference to FIG. 10.                     

That is, between two adjacent gate link wires 154 passing through the seal pattern 170 forming portion, a seal pattern with a lower substrate (refer to 150 of FIG. 8 and located under the gate link wire 154 in FIG. 10) An etching stopper is formed on the gate insulating layer on which the protective film hole 195a is formed to have a predetermined width in order to improve the adhesion of the 170, and the protective film hole 195a is formed to prevent over-etching when the protective film hole 195a is formed. The semiconductor layer 180 having the function of () is further formed. At this time, the semiconductor layer 180 and the source / drain electrode material 200 are deposited at the same time, and a source / drain electrode material 200 is further formed on the semiconductor layer 180. However, the reason why the source / drain electrode material 200 is removed to the same width as the passivation hole 195a in the passivation hole 195a may be due to overetching the passivation layer 157 during the formation of the passivation hole 195a. Because it is going on. The source / drain electrode material 200 electrically connects the gate link wires H between the gate pad portions spaced apart from each other (see trapezoidal shape 200 in FIG. 9).

As shown in FIG. 11, the link wiring part corresponding to the portion H between adjacent gate pad parts P is as follows.

In the link wiring portion corresponding to the region H between the adjacent gate pad portions P, the gate link wiring 154 is not positioned, and the source / drain electrode material is formed beyond the seal pattern 170. Similarly, the protective layer 157 is formed by etching the upper protective layer 157 with a predetermined width to improve the adhesion of the seal pattern 170 to the lower substrate 150.

8 to 11, a link wiring part forming method of the liquid crystal display of the present invention will be described.

First, a metal material is deposited on the entire surface of the lower substrate 150, and then selectively removed to form a gate line 152 in the pixel portion 151, and in the link wiring portion, the gate link wiring 154 connected thereto is formed. In the pad portion, the gate pad wiring 158 is formed.

Subsequently, a gate insulating layer 156 and a semiconductor layer forming layer 180 are sequentially deposited on the lower substrate (not shown) on the gate link wiring 154.

Subsequently, after depositing the source / drain electrode material layer (the same layer as the layer 200), patterning the semiconductor layer forming layer (the same layer as the layer 180) and the source / drain electrode material layer (the same layer as the layer 200) using a diffraction exposure mask. do. In this case, a semiconductor layer (not shown), a source / drain electrode, and a data line 153 are formed in the pixel portion 151, and the data link wiring 155 connected thereto is formed in the data link wiring portion, and the data is formed in the data pad portion. Pad wiring (not shown, covered by the source driver IC 182) is formed. In this case, the link wiring part corresponding to the gate pad part P is patterned so as to leave the source / drain electrode material 200 and the semiconductor layer 180 at the same width in the portion where the passivation layer hole 195a is to be formed.

Subsequently, the passivation layer 157 is entirely deposited on the gate insulating layer 156 including the source / drain electrode material 200.

Subsequently, the passivation layer 157 is selectively removed to the extent that the gate link wiring 154 is not exposed to form passivation holes 195a and 195b. When the passivation layer holes 195a and 195b are formed, the semiconductor layer 180 functions as an etch stopper to prevent the etching from occurring even when overetching occurs. Here, the source / drain electrode material 200 formed on the semiconductor layer 180 is etched and removed together with the passivation layer 157 when the protective layer holes 195a and 195b are formed.

As such, when the semiconductor layer 180 and the source / drain electrode material 200 are formed in the link wiring portion corresponding to the gate pad part P, the passivation layer hole 195a for etching the subsequently deposited passivation layer 157 is formed. 195b, the thickness of the passivation layer hole 195a formed during the formation process is substantially the same as the thickness of the passivation layer hole 195b formed in the link wiring portion corresponding to the region H between the gate pad portions. Steps do not occur on the formed link wiring portion. Here, the reason why the semiconductor layer 180 and the source / drain electrode material 200 are formed on top of the source / drain electrode material 200 without forming only the semiconductor layer 180 functioning as an etch stopper is provided. This is because the deposition process takes place at the same time. As such, the source / drain electrode material 200 formed together with the semiconductor layer 180 by the same deposition process may be removed together with the passivation layer 157 during the formation of the passivation layer holes 195a and 195b.

All of the above processes are performed simultaneously when forming the thin film transistor array on the lower substrate.

As such, after completing the process of forming the thin film transistor array on the lower substrate 150, and completing the process of forming the color filter array on the upper substrate 160 which is symmetrical thereto, the bonding process is performed. The spacer pattern (not shown) is formed on one side of the 160 or the lower substrate 150, and the seal pattern 170 is formed on the other side. Then, when the two substrates 150 and 160 are pressed and joined, the seal pattern 170 is formed. The protective film holes 195a and 195b penetrate into the same thickness.

Therefore, in the liquid crystal display of the present invention, a passivation layer hole is formed to have a thickness almost similar to that of the link wiring portion corresponding to the gate pad portion P and the link wiring portion corresponding to the region H between the gate pad portions. The step 170 of the pattern 170 hardly occurs for each part, and the upper and lower substrates 160 and 150 are stably bonded.

Here, the protective film 157 is an organic insulating film such as BCB and photo acryl.

12 is a cross-sectional view illustrating a line III-III ′ of FIG. 9 according to another exemplary embodiment of the liquid crystal display of the present invention, and FIG. 13 is a cross-sectional view illustrating a line IV-IV ′ of FIG. 10 according to another embodiment. .

As shown in FIG. 12, another embodiment of the liquid crystal display of the present invention includes a semiconductor device such as a link wiring part corresponding to an area H between the gate pad parts in a link wiring part corresponding to the gate pad part P. In the patterning process of the layer 180 and the source / drain electrode material 200, the pattern 180 is left without any separate patterning. Other than the same as the embodiment described in Figures 10 and 11 described above, the same reference numerals are assigned to the same parts and description thereof will be omitted.

In other embodiments, similarly to the above-described embodiment, the same step improvement effect may be obtained as the thickness of the passivation hole 195a is removed to the extent that the passivation layer 157 and the source / drain electrode material 200 are removed.

The liquid crystal display of the present invention as described above has the following effects.                     

The semiconductor layer and the source / drain electrode material are further deposited on the portion where the protective layer hole of the link wiring portion corresponding to the gate pad portion is to be formed, and the semiconductor layer functions as an etch stopper during etching to form the protective layer hole. The seal pattern step with the link wiring section corresponding to the area between the sections can be prevented.

Such a seal pattern step prevention prevents lifting by eliminating the gap around the seal pattern, thereby improving yield and improving the quality level of the liquid crystal display.

Claims (8)

  1. First and second substrates on which a display unit and a non-display unit at an outer portion thereof are defined;
    A plurality of gate lines and data lines perpendicular to each other on the first substrate in the display unit;
    A gate pad portion and a data pad portion for applying a driving signal to the gate lines and the data lines on a non-display portion of the first substrate, respectively;
    A gate link wiring connecting the gate wiring and the gate pad portion;
    A data link wiring connecting the data wiring and the data pad portion;
    A seal pattern disposed between the first and second substrates and passing through the gate link wires and the data link wires at boundary portions of the display unit and the non-display unit;
    A passivation layer covering the gate link wiring under the seal pattern and having a hole between the adjacent gate link wirings; And
    In the liquid crystal display device having a semiconductor layer formed below the protective film hole,
    And gate link wires respectively connected to the gate pad portions spaced apart from each other, by the source / drain electrode material.
  2. The method of claim 1,
    And the passivation hole is smaller than a gap between the gate link wires.
  3. The method of claim 1,
    And the semiconductor layer is wider than the passivation hole.
  4. The method of claim 3, wherein
    And a source / drain electrode material formed on the semiconductor layer on both sides of the passivation hole.
  5. The method of claim 3, wherein
    And the semiconductor layer is formed between the gate link wirings.
  6. The method of claim 3, wherein
    And the semiconductor layer is formed on the entire lower surface of the passivation layer including the passivation hole.
  7. delete
  8. The method of claim 1,
    And the protective film is an organic insulating film.
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US10268090B2 (en) 2010-10-20 2019-04-23 Samsung Display Co., Ltd. Display substrate having more uniform cell gap and method of fabricating the same

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KR101593103B1 (en) * 2009-10-29 2016-02-18 엘지디스플레이 주식회사 Liquid crystal display device

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KR20010057023A (en) * 1999-12-17 2001-07-04 구본준, 론 위라하디락사 Liquid Crystal Display Device and Method of Fabricating the Same

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KR20010057023A (en) * 1999-12-17 2001-07-04 구본준, 론 위라하디락사 Liquid Crystal Display Device and Method of Fabricating the Same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10268090B2 (en) 2010-10-20 2019-04-23 Samsung Display Co., Ltd. Display substrate having more uniform cell gap and method of fabricating the same

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