KR101032941B1 - Thin film transistor array panel - Google Patents

Thin film transistor array panel Download PDF

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Publication number
KR101032941B1
KR101032941B1 KR1020030093252A KR20030093252A KR101032941B1 KR 101032941 B1 KR101032941 B1 KR 101032941B1 KR 1020030093252 A KR1020030093252 A KR 1020030093252A KR 20030093252 A KR20030093252 A KR 20030093252A KR 101032941 B1 KR101032941 B1 KR 101032941B1
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KR
South Korea
Prior art keywords
line
gate
gate driver
formed
driver
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KR1020030093252A
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Korean (ko)
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KR20050061132A (en
Inventor
김일곤
김철민
김철호
박태형
Original Assignee
삼성전자주식회사
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Priority to KR1020030093252A priority Critical patent/KR101032941B1/en
Publication of KR20050061132A publication Critical patent/KR20050061132A/en
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    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1345Conductors connecting electrodes to cell terminals
    • G02F1/13452Conductors connecting driver circuitry and terminals of panels
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1345Conductors connecting electrodes to cell terminals
    • G02F1/13454Drivers integrated on the active matrix substrate
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136259Repairing; Defects
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136286Wiring, e.g. gate line, drain line

Abstract

A gate line formed on an insulating substrate, a data line insulated from and crossing the gate line to define a display area, a gate driver for applying a scan signal to the gate line, a data driver for applying an image signal to the data line, and a display area As a result, a thin film transistor array panel including a dummy gate driver formed on the opposite side of the gate driver is provided.
Thin film transistor display panel, dummy gate driver

Description

Thin film transistor array panel

1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention.

FIG. 2A is an enlarged view of a portion A of FIG. 1;

FIG. 2B is a cross sectional view taken along the line IIb-IIb ′ of FIG. 2A;

3A is an enlarged view of a portion B of FIG. 1,

FIG. 3B is a cross-sectional view taken along line IIIb-IIIb 'of FIG. 3A.

121 gate line,

171 data lines,

400 gate driver,

410 dummy gate driver,

401, 402, 403 dummy gate leads

500 data driver,

600 data drive ic,

610 FPC (flexible printed circuit)

700 printed circuit board

The present invention relates to a thin film transistor array panel.

The thin film transistor array panel is a substrate in which a thin film transistor, which is a switching element for driving each pixel independently in a flat panel display such as a liquid crystal display or an organic EL display, is formed in a predetermined arrangement.

In the thin film transistor array panel, a plurality of gate lines and a data line cross each other, and a thin film transistor is formed in each pixel region where the two lines cross each other. The gate line transfers a scan signal and the data line transfers an image signal.

In the scan signal and the image signal, a gate driving circuit and a data driving circuit are applied to each gate line and data line, respectively. These driving circuits may be configured by mounting separate integrated chip (IC) chips, or may be formed together in the process of forming a thin film transistor on a display panel. The latter case is mainly applied to a polysilicon thin film transistor array panel having excellent performance of a thin film transistor.

However, the gate line and the data line formed on the thin film transistor array panel are very fine metal patterns, and there is a possibility that the gate lines and the data lines may be disconnected during the formation process. In preparation for the disconnection of such wiring, a structure that can be repaired later is formed or a structure that prevents disconnection is formed. In the case of the gate line, it is common to take a method of preventing the disconnection by forming the gate line in double, but in this case, the gate line has a large area and thus has a low opening ratio. If a repair line is formed around the display area and the gate line is disconnected, the repair line and the disconnected gate line are connected to each other so that the scan signal can be transmitted via the repair line. However, in this case, the load of the gate line increases, causing a problem that the scan signal is distorted.

The technical problem to be achieved by the present invention is to provide a structure compared to the gate line disconnection without the problem of lowering the aperture ratio or increasing the gate line load.

In order to solve this problem, the present invention forms a dummy gate driver.

Specifically, an insulating substrate, a gate line formed on the insulating substrate, a data line insulated from and intersecting the gate line to define a display area, a gate driver for applying a scan signal to the gate line, and an image on the data line. A thin film transistor array panel including a data driver configured to apply a signal and a dummy gate driver disposed opposite the gate driver based on the display area is provided.

The dummy gate connection line may further include a dummy gate connection line for connecting between the gate driver and the dummy gate driver. The dummy gate connection line is connected to an input terminal of the dummy gate driver. You can nest them with. The dummy gate driver may further include a connection line overlapping the lead line and the gate line and the insulating layer therebetween.                     

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Hereinafter, the present invention will be described using a thin film transistor for a liquid crystal display as an example.

Next, a structure of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described with reference to the drawings.

1 is a layout view of a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention, FIG. 2A is an enlarged view of a portion A of FIG. 1, and FIG. 2B is a line IIb-IIb ′ of FIG. 2A. 3A is an enlarged view of a portion B of FIG. 1, and FIG. 3B is a cross-sectional view taken along line IIIb-IIIb ′ of FIG. 3A.

The liquid crystal display device includes a liquid crystal layer including a lower panel, an upper panel facing the lower panel, and liquid crystal molecules injected between the lower panel and the upper panel.

A thin film transistor array including a gate line 121 and a data line 171, a gate driver 400, and a data driver 500 are formed on the lower panel, and the data driver 500 is a flexible printed circuit (FPC). And a data driver IC 600 mounted at 610. The data driver IC 600 is connected to a gray voltage generator circuit or a signal control circuit mounted on a printed circuit board 700. The gate driver 400 is also connected to a driving voltage generation circuit of the PCB 700 via a pin of the FPC 610 or the data driver IC 600.

In addition, the dummy gate driver 410 is formed to face the gate driver 400 with the display area indicated by a dotted line therebetween. The dummy gate driver 410 has the same structure as the gate driver 400 and includes dummy gate connection lines 401, 402, and 403 so that the dummy gate driver 410 may be connected to the gate driver 400 if necessary. Although three dummy gate connection lines 401, 402, and 403 are illustrated in the drawing, this is only an example and may be formed in more or less. In addition, the dummy gate driver 410 has a connection structure so that the dummy gate driver 410 can also be connected to each gate line 121 if necessary.

Then, the connection structure between the dummy gate connection lines 401, 402, and 403 and the gate driver 400, and the connection structure between the dummy gate driver 410 and the gate line 121 will be described with reference to FIGS. 2A, 2B, 3A, and 3B. Will be explained.

First, as shown in FIGS. 2A and 2B, a blocking film 111 is formed on the insulating substrate 110, a gate insulating film 130 is formed on the blocking film 111, and a gate driver is formed on the gate insulating film 130. A leader line 122 is formed. Here, the blocking film 111 is formed to prevent foreign matter from penetrating into the polycrystalline silicon layer of the thin film transistor formed in the display region from the insulating substrate 110 made of glass or the like. The gate driver lead line 122 is formed of the same material as the gate line 121 and outputs the same signal as that input to the gate driver 400 as a signal line drawn from the gate driver 400.

A first interlayer insulating layer 801 is formed on the gate driver lead line 122, a dummy gate connection line 172 is formed on the first interlayer insulating layer 801, and a second interlayer insulating layer is formed on the dummy gate connection line 172. 801 is formed. The dummy gate connection line 172 overlaps with the gate driver lead-out line 122 and is formed of the same material as the data line 171.

As described above, the gate driver lead line 122 and the dummy gate connection line 172 overlap with the first interlayer insulating film 801 therebetween. Therefore, these two wires 122 and 172 can be shorted by irradiating a laser if necessary.

In the present exemplary embodiment, the gate driver lead line 122 is formed on the same layer as the gate line 121, and the dummy gate connection line 172 is formed on the same layer as the data line 171. ) May be formed on the same layer as the data line 171, and the dummy gate connection line 172 may be formed on the same layer as the gate line 121.

3A and 3B, the blocking film 111 is formed on the insulating substrate 110, the gate insulating film 130 is formed on the blocking film 111, and the gate line is formed on the gate insulating film 130. The 121 and the dummy gate driver lead line 123 are formed. A first interlayer insulating film 801 is formed on the gate line 121 and the dummy gate driver lead line 123, a connecting piece 174 is formed on the first interlayer insulating film 801, and a first interlayer insulating film 801 is formed on the connecting piece 174. A two interlayer insulating film 802 is formed. The connection piece 174 overlaps the gate line 121 and the dummy gate driver lead line 123 with the first interlayer insulating layer 801 therebetween. Therefore, if necessary, the laser can be irradiated to short-circuit between the connecting piece 174 and the gate line 121 and between the connecting piece 174 and the dummy gate driver lead line 123.

In the present exemplary embodiment, the dummy gate driver lead line 123 is formed on the same layer as the gate line 121, and the connecting piece 174 is separately formed and connected. However, the dummy gate driver lead line 123 is connected to the gate line 121. May be formed in another layer, and the dummy gate driver lead line 123 may be directly overlapped with the gate line 121.

In the above structure, when a gate line 121 is disconnected, the gate driver lead line 122 and the dummy gate connection lines 401, 402, and 403 are connected, and the gate line disconnected from the dummy gate driver lead line 123. Connect (121). In this case, the scan signal may be applied to the disconnected gate line 121 by the dummy gate driver 410 outputting the scan signal in the same manner as the gate driver 400.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights. In particular, the arrangement of the cutouts formed in the pixel electrode and the common electrode may be variously modified.

If the gate line repair structure is formed in the above configuration, since there is no additional wiring to repair the gate line in the display area, the opening ratio is not reduced and the scan signal output from the dummy gate driver is directly transmitted to the gate line, thereby increasing the load. No signal distortion occurs.

Claims (4)

  1. delete
  2. delete
  3. Insulation board,
    A gate line formed on the insulating substrate,
    A data line insulated from and intersecting the gate line to define a display area;
    A gate driver applying a scan signal to the gate line;
    A data driver for applying an image signal to the data line;
    A dummy gate driver formed opposite the gate driver with respect to the display area;
    A dummy gate connection line for connecting the gate driver and the dummy gate driver;
    The dummy gate connection line is connected to an input terminal of the dummy gate driver and overlaps the lead line of the gate driver and an insulating layer therebetween.
  4. Insulation board,
    A gate line formed on the insulating substrate,
    A data line insulated from and intersecting the gate line to define a display area;
    A gate driver applying a scan signal to the gate line;
    A data driver for applying an image signal to the data line;
    A dummy gate driver formed opposite the gate driver with respect to the display area;
    And a connecting piece overlapping the lead line of the dummy gate driver and the gate line and the insulating layer therebetween.
KR1020030093252A 2003-12-18 2003-12-18 Thin film transistor array panel KR101032941B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020030093252A KR101032941B1 (en) 2003-12-18 2003-12-18 Thin film transistor array panel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020030093252A KR101032941B1 (en) 2003-12-18 2003-12-18 Thin film transistor array panel

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KR20050061132A KR20050061132A (en) 2005-06-22
KR101032941B1 true KR101032941B1 (en) 2011-05-06

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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108646486A (en) * 2018-05-04 2018-10-12 昆山国显光电有限公司 Display panel and display device
CN108646485A (en) * 2018-05-04 2018-10-12 昆山国显光电有限公司 Display panel and display device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5365284A (en) 1989-02-10 1994-11-15 Sharp Kabushiki Kaisha Liquid crystal display device and driving method thereof
KR19990052420A (en) * 1997-12-22 1999-07-05 김영환 Lcd
KR20030043672A (en) * 2001-11-28 2003-06-02 샤프 가부시키가이샤 Liquid crystal display device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5365284A (en) 1989-02-10 1994-11-15 Sharp Kabushiki Kaisha Liquid crystal display device and driving method thereof
KR19990052420A (en) * 1997-12-22 1999-07-05 김영환 Lcd
KR20030043672A (en) * 2001-11-28 2003-06-02 샤프 가부시키가이샤 Liquid crystal display device

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