KR101020940B1 - Flip-Flop Circuit of having Multi-threshold Voltage CMOS and Method of driving the same - Google Patents

Flip-Flop Circuit of having Multi-threshold Voltage CMOS and Method of driving the same Download PDF

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KR101020940B1
KR101020940B1 KR1020080111055A KR20080111055A KR101020940B1 KR 101020940 B1 KR101020940 B1 KR 101020940B1 KR 1020080111055 A KR1020080111055 A KR 1020080111055A KR 20080111055 A KR20080111055 A KR 20080111055A KR 101020940 B1 KR101020940 B1 KR 101020940B1
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node
transistor
unit
mode
signal
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KR20100052158A (en
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김영환
신현철
이봉현
황은주
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한양대학교 산학협력단
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    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356Bistable circuits
    • H03K3/356008Bistable circuits ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318541Scan latches or cell details
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01Details
    • H03K3/012Modifications of generator to improve response time or to decrease power consumption

Abstract

A flip-flop circuit having multiple threshold voltages and a driving method thereof are disclosed. MTCMOS-based flip-flop circuits operating in active and inactive modes should minimize power consumption during sleep mode during inactive mode. To this end, the power control unit for controlling the supply of power includes transistors having a higher threshold voltage than the sense amplifier. The transistors having a high threshold voltage effectively cut off the leakage current at the time of cut-off. Also, since the sense amplifier has a relatively low threshold voltage, it is possible to maintain a high operating speed when operating in the active region.
Figure R1020080111055
MTCMOS, Flip-Flop, Multiple Threshold Voltages

Description

Flip-flop circuit of having multi-threshold voltage CMOS and method of driving the same

The present invention relates to a flip-flop having a multi-threshold voltage, and more particularly, to a flip-flop having a multi-threshold voltage to minimize power consumption and enable high-speed operation based on a sense amplifier.

Semiconductor integrated circuits are mounted in a variety of applications. The types of semiconductor integrated circuits applied to the actual electronic devices can be classified into various types according to the performance or characteristics of the product, and the product ranges are different depending on the characteristics. Recently, with the development of portable devices, discussions have been made to minimize the power consumed by a single semiconductor integrated circuit, and active research and development is in progress.

In particular, a circuit having a multi-threshold voltage has been recently discussed with the development of semiconductor manufacturing processes. That is, a plurality of transistors constituting one semiconductor integrated circuit are classified into a group having a relatively high threshold voltage and a group having a relatively low threshold voltage, and are appropriately disposed in the circuit.

A method of arranging transistors having different threshold voltages in a semiconductor circuit is as follows.

For example, transistors having a high threshold voltage are arranged at a portion that is connected to a power line or supplies power to a circuit that performs a predetermined function. This is because, when the transistor has a high threshold voltage, it has a high on / off blocking capability. That is, when the transistor enters the cut-off region, it is excellent in the ability to prevent leakage current from the power line.

On the other hand, transistors having a relatively low threshold voltage are disposed in a portion that implements the operation of the circuit. This is because the transistors having a low threshold voltage slightly lower the current blocking capability in the cut-off region, but consume less power in normal operation. In addition, the high threshold operation is possible due to the low threshold voltage.

Due to the advantages described above, research on a semiconductor circuit having multiple threshold voltages has been conducted. However, even if certain placement techniques for transistors with high threshold voltages are used, some circuits produce unwanted leakage currents. In addition, the plurality of threshold voltages may cause a problem in that the control signals have a reduced ability to control the operation mode of the transistors. As a result, a circuit having only one threshold voltage is used to construct a circuit that performs a predetermined operation.

1 is a circuit diagram in which a flip-flop is implemented as a semiconductor circuit having one threshold voltage.

1 is disclosed in Korean Patent Registration No. 305710.

Referring to FIG. 1, the flip-flop circuit includes a current sense amplifier 10, a non-inverted output 20, and an inverted output 30.

The current sensing amplifier 10 receives the clock signal CK, the data signal D, and the inverted data signal / D, and outputs a predetermined level to the precharge nodes / S and / R according to the level of the clock signal CK. do.

The non-inverting output unit 20 receives the signal of the precharge node / S and inverts it to form the output signal Q. However, the operation of the non-inverting output unit 20 is controlled by the clock signal CK.

The inversion output unit 30 receives the signal of the precharge node / R, and inverts the signal of the precharge node / R under the control of the clock signal CK to form the inverted output signal / Q.

The operation of the above-described circuit assumes that the threshold voltages of the transistors constituting the flip-flop are the same. That is, the plurality of transistors may have process differences, but have substantially the same threshold voltages. If the flip-flop is composed of transistors having a relatively high threshold voltage, the power consumption may be slightly reduced, but the operation speed may be reduced. In addition, when the flip-flop is composed of transistors having a relatively low threshold voltage, the leakage current also increases with an increase in operating speed, thereby causing a problem in that power consumption increases as a whole. In particular, in the operation of the flip-flop, the output current cannot be maintained due to the leakage current in the sleep mode in which power is not supplied to the current sensing amplifier 10.

A first object of the present invention for solving the above problems is to provide a flip-flop circuit having a low power consumption and a high operating speed, and having a multiple threshold voltage.

A second object of the present invention is to provide a method of driving a flip-flop circuit having a multiple threshold voltage implemented by achieving the first object.

Accordingly, the present invention for achieving the first object, the flip-flop operating in an inactive mode in which the active mode for updating and storing the input data signal and the power supply are cut off, and only the data signal is stored. A circuit comprising: a sense amplification coupled between a positive power supply voltage and a first node for sensing said data signals at a high level of a clock signal in said active mode to produce complementary signals to a second node and a third node; part; A node setting unit connected between the positive power supply voltage and the second node and the third node and configured to set the second node and the third node to a high level in the inactive mode; A first latch part connected to the positive power supply voltage and configured to update an output signal or to maintain the output signal according to the level of the second node; A second latch part connected to the positive power supply voltage and configured to update an inverted output signal according to the level of the third node or to maintain the inverted output signal; A data recovery unit connected between the first node, a second node, and a third node, and configured to recover output signals of the first and second output nodes of the sense amplifier before entering the active mode; And a ground voltage connected to the ground voltage, supplying power to the first latch unit, the second latch unit, the data recovery unit, and the sense amplifier unit, and configured to configure the data recovery unit, the node setting unit, or the sense amplifier unit. Provided is a flip-flop circuit including a power control unit having a higher threshold voltage than transistors.

In addition, the present invention for achieving the second object, in the operating method of the flip-flop circuit consisting of a sense amplifier, a node setting unit, a first latch unit, a second latch unit, a data recovery unit and a power control unit, the clock Detecting a data signal at a high level of the signal and operating in an active mode for updating or storing the data signal; And an inactive mode that turns off the power control unit having a higher threshold voltage than the transistors configuring the node setting unit, the data recovery unit, or the sense amplifier, and blocks the operation of the sense amplifier unit to preserve the data signal stored in the active mode. It provides a method of driving a flip-flop circuit comprising the step of operating in.

According to the present invention described above, the transistors constituting the flip-flop circuit do not have a matching threshold voltage. That is, transistors that power the circuit have higher threshold voltages than other components. If the threshold voltage of the transistor is relatively high, the corresponding transistor has a high current blocking capability. That is, leakage current is minimized in the cut-off region, and power consumption in the sleep mode is minimized. In addition, the sense amplifier and the like have a relatively low threshold voltage, it is possible to maintain a high operating speed in the active mode.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. Like reference numerals are used for like elements in describing each drawing.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

Example

2 is a circuit diagram illustrating a flip-flop having multiple threshold voltages according to an embodiment of the present invention.

2, the flip-flop circuit of this embodiment is based on the sense amplifier. The flip-flop circuit includes a sense amplifier 100, a node setting unit 200, a data recovery unit 300, a power control unit 400, a first latch unit 500, and a second latch unit 600.

The sense amplifier 100 includes a transistor Q0 providing a virtual ground, two transistors Q1 and Q2 to which data signals D and / D are input, a transistor Q3 and a latch structure that controls the flow of current according to the input of the data signal. It consists of four transistors Q4, Q5, Q6 and Q7 having

The sense amplifier 100 senses the data signal D and the inverted data signal / D, amplifies it, and outputs it to the second node N2 and the third node N3. In particular, the sensing and amplifying operation is performed in the active mode, and the operation is stopped in the inactive mode.

Transistor Q0 receives clock signal CK through the gate terminal. In addition, one end of the transistor Q0 is connected to the first node N1.

Transistor Q1 receives the data signal D and is connected to one end of the first node N1 and transistor Q3. In addition, transistor Q2 receives the inverted data signal / D and is connected between the first node N1 and the other end of transistor Q3. Thus, the source terminals of the transistors Q1 and Q2 are commonly connected to the first node N1.

Transistor Q3 is connected between one end of the transistors Q1 and Q2. In addition, the gate terminal of the transistor Q3 is connected to the positive power supply voltage VDD.

Transistors Q4 and Q5 have one inverter structure. That is, transistor Q4 connected to positive power supply voltage VDD is composed of PMOS, transistor Q5 is connected to transistor Q4, and the gate terminals of two transistors Q4 and Q5 are commonly connected to each other and are connected to third node N3. . In addition, the output terminals of the transistors Q4 and Q5 constituting one inverter are connected to the second node N2. Similarly, transistors Q6 and Q7 have a configuration opposite to the inverter configured in transistors Q4 and Q5. That is, transistor Q6 is connected between positive power supply voltage VDD and third node N3, and transistor Q7 is connected between third node N3 and transistor Q3. Transistor Q6 is composed of PMOS, and transistor Q7 is composed of NMOS. In addition, the gate terminals of the transistors Q6 and Q7 are commonly connected to each other, and are connected to the second node N2 which is an output terminal of the transistors Q4 and Q5.

The node setting unit 200 is composed of five transistors M1, M2, M3, M4, and M5. The node setting unit 200 forcibly sets the levels of the second node N2 and the third node N3 in the inactive mode. That is, in the sleep mode among the inactive modes, the levels of the second node N2 and the third node N3 are fixed to a high level.

The first transistor M1 is connected between the positive power supply voltage VDD and the second node N2. The first mode control signal SC1 is input to the gate terminal of the first transistor M1. In addition, the first transistor M1 is configured of a PMOS. Thus, the first transistor M1 is turned on upon application of the low level. As a result, the level of the second node N2 is set according to the first mode control signal SC1 applied to the first transistor M1.

For convenience, when the signal has a low level, it is expressed as '0', and when the signal has a high level, it is expressed as '1'. In the present invention, the signal is divided into upper and lower levels, or mixed and displayed as data 0 or 1. However, for easy understanding, the high level is used in the same meaning as data 1 and the low level is used in the same meaning as data 0. Of course, it will be apparent to those skilled in the art that the display and the upper and lower levels of the data may be interchanged.

The second transistor M2 is connected between the positive power supply voltage VDD and the third node N3. The first mode control signal SC1 is input to the gate terminal of the second transistor M2. Similar to the first transistor M1, the level of the third node N3 is set according to the first mode control signal SC1 applied to the second transistor M2.

The third transistor M3 is connected between the positive power supply voltage VDD and the fourth node N4. The second mode control signal SC2 is input to the gate terminal of the third transistor M3. According to the second mode control signal SC2, a positive power supply voltage VDD is applied to the fourth node N4. In addition, the positive power supply voltage VDD is supplied to the transistors M4 and M5 through the fourth node N4.

The fourth transistor M4 is connected between the second node N2 and the fourth node N4 and performs an on / off operation under the control of the clock signal CK. In addition, the fifth transistor M5 is connected between the third node N3 and the fourth node N4 and performs an on / off operation under the control of the clock signal CK.

The data recovery unit 300 has a first recovery path 310 and a second recovery path 320.

The first recovery path 310 is connected between the first node N1 and the second node N2 and includes a sixth transistor M6 and a seventh transistor M7. In addition, the second recovery path 320 is connected between the first node N1 and the third node N3 and includes an eighth transistor M8 and a ninth transistor M9. The second mode control signal SC2 and two output signals Q and / Q are applied to the data recovery unit 300. The first recovery path returns the voltage of the second node N2 to the level in the active mode by the signals applied to the gate terminals of the transistors constituting the data recovery unit 300, and the second recovery path is the third node. Return the voltage at N3 to the level in active mode.

The sixth transistor M6 and the seventh transistor M7 constituting the first recovery path 310 are connected in series. In addition, the sixth transistor M6 is connected between the second node N2 and the seventh transistor M7, and the second mode control signal SC2 is applied to the gate terminal of the sixth transistor M6. In addition, the seventh transistor M7 is connected between the sixth transistor M6 and the first node N1. The output signal Q is applied to the gate terminal of the seventh transistor M7.

The eighth transistor M8 and the ninth transistor M9 constituting the second recovery path 320 are connected in series. The eighth transistor M8 is connected between the third node N3 and the ninth transistor M9, and the second mode control signal SC2 is input to the gate terminal. In addition, the ninth transistor M9 is connected between the first node N1 and the eighth transistor M8. The inverted output signal / Q is applied to the gate terminal of the ninth transistor M9. As a result, the source terminals of the transistors M7 and M9 are commonly connected to each other.

The power control unit 400 is composed of three transistors M10, M11, and M12. The power control unit 400 is turned on in the active mode to supply predetermined power to the sense amplifier, the first latch unit 500, and the second latch unit 600. The three transistors M10, M11, and M12 constituting the power control unit 400 have higher threshold voltages than transistors constituting the sensing amplifier 100, the data recovery unit 300, or the node setting unit 200. Have

The tenth transistor M10 is connected between the first node N1 and the ground voltage. The first mode control signal SC1 is applied to the gate terminal of the tenth transistor M10. In FIG. 2, the ground voltage is introduced instead of the negative power supply voltage, but the ground voltage may be set to various values according to the embodiment and the power distribution.

The eleventh transistor M11 is connected between the first latch portion 500 and the ground voltage. The first mode control signal SC1 is applied to the gate terminal of the eleventh transistor M11.

The twelfth transistor M12 is connected between the second latch unit 600 and the ground voltage, and the first mode control signal SC1 is applied to the gate terminal.

The first latch unit 500 mass-produces the output signal Q according to the signal applied to the second node N2 and the clock signal CK. That is, the first latch unit 500 is connected between the positive power supply voltage VDD and the power control unit 400, and updates or maintains stored data according to the level of the second node N2. The first latch unit 500 includes three transistors M13, M14 and M15 and a first latch 510.

The thirteenth transistor M13 is connected between the positive power supply voltage VDD and the fifth node N5. The voltage of the second node N2 is applied to the gate terminal of the thirteenth transistor M13.

In addition, the fourteenth transistor M14 is connected between the fifth node N5 and the fifteenth transistor M15. The clock signal CK is applied to the gate terminal of the fourteenth transistor M14.

The fifteenth transistor M15 is connected between the fourteenth transistor M14 and the eleventh transistor M11 of the power control unit 400. The gate terminal of the fifteenth transistor M15 is connected to the second node N2.

The first latch 510 is composed of two inverters and is connected to the fifth node N5. The signal applied to the fifth node N5 generates the output signal Q.

The second latch unit 600 generates an inverted output signal / Q according to the signal applied to the third node N3 and the clock signal CK. The second latch unit 600 includes three transistors M16, M17 and M18, and a second latch 610.

The sixteenth transistor M16 is connected between the positive power supply voltage VDD and the sixth node N6. The signal of the third node N3 is applied to the gate terminal of the sixteenth transistor M16. As a result, the inverted output signal / Q level is set at the sixth node N6 as the output node according to the on / off operation of the sixteenth transistor M16.

The seventeenth transistor M17 is connected between the sixth node N6 and the eighteenth transistor M18. The clock signal CK is input to the gate terminal of the seventeenth transistor M17.

An eighteenth transistor M18 is connected between the seventeenth transistor M17 and the twelfth transistor M12 of the power control unit 400. The gate terminal of the eighteenth transistor M18 is connected to the third node N3.

In addition, the second latch 610 is composed of two inverters, and stores a signal of the inverted output signal / Q, which is a signal of the sixth node N6, which is an output node.

The flip-flop circuit of this embodiment described above operates in two operation modes.

3 is a timing diagram illustrating an operation of the flip-flop circuit shown in FIG. 2 according to a preferred embodiment of the present invention.

Referring to FIG. 3, the flip-flop circuit of this embodiment operates largely in an active mode and an inactive mode.

The active mode and the inactive mode are defined by the levels of the first mode control signal SC1 and the second mode control signal SC2.

In the active mode, data 1 is input to the first mode control signal SC1 and 0 is input to the second mode control signal SC2. In the active mode, the data signals D and / D input in accordance with the level of the clock signal CK are updated and stored in the two latch units 500 and 600.

First, the transistors M10, M11, and M12 of the power control unit 400 are turned on by the first mode control signal SC1 in the active mode.

Data 0 is supplied to the sense amplifier 100 and the data recovery unit 300 by the turned-on tenth transistor M10.

When the clock signal CK is at the low level, the transistor Q0 is turned off, so that power to the sense amplifier 100 is cut off. Further, the sixth and eighth transistors M6 and M8 are turned off by the second mode control signal SC2 having a value of zero. This means that the sense amplifier 100 and the data recovery unit 300 do not operate.

In addition, some of the transistors M3, M4, and M5 of the node setting unit 200 are turned on and supply a positive power supply voltage VDD to the second node N2 and the third node N3. That is, the second node N2 and the third node N3 are set to data one.

Due to the data 1 of the second node N2, the first latch unit 500 maintains the previous value without updating the output signal. That is, since the voltage of the second node N2 corresponds to data 1, the thirteenth transistor M13 is turned off, and since the clock signal CK is low level, the fourteenth transistor M14 is also turned off. As a result, the supply of the voltage from the positive power supply voltage VDD and the ground voltage is cut off, so that the first latch 510 maintains the previously stored value.

This is shown in a similar operation of the second latch unit 600.

Since the clock signal CK is at the low level, the fifth transistor M5 is turned on and data 1 is set to the third node N3. Therefore, the sixteenth transistor M16 of the second latch portion is turned off, and the seventeenth transistor M17 to which the clock signal CK is input is also turned off. Therefore, the sixth node N6 maintains the previous state, and the second latch 610 maintains the previous value.

When the clock signal CK rises from the low level to the high level in the active mode, the sense amplifier 100 receives the input signals D and / D, detects the signals, and detects a predetermined signal at the second node N2 and the third node N3. Outputs In addition, the first latch unit 500 inverts and stores the signal of the second node N2, which is an output signal of the sense amplifier 100. Similarly, the second latch unit 600 inverts and stores the signal of the third node N3, which is another output signal of the sense amplifier 100.

First, when the clock signal CK changes to a high level, the transistor Q0 of the sense amplifier 100 is turned on. Therefore, a low level is set at the first node N1, which is a common source terminal of the transistors Q1 and Q2 constituting the differential stage, to form a virtual ground.

When the clock signal CK is input to the data signal D at a high level and 0 is input to the inverted data signal / D, the transistor Q1 is turned on and the node to which the transistor Q1 and the transistor Q3 are connected is set to zero. Thus, transistor Q3 is turned on and current flows between the source-drain terminals of transistor Q3. The transistor Q5 is turned on by the data value of one end of the transistor Q3 set to 0, and a value of 0 is output to the second node N2. In addition, the transistor Q6 is turned on by the voltage of the second node N2 set to 0, and a value of 1 is output to the third node N3. That is, when the clock signal CK changes from the low level to the high level in the active mode, the sense amplifier 100 senses the data signals D and / D and amplifies them to form two output signals that are complementary to each other. For example, when the data signal D is 1, a value of 0 is output to the second node N2 and a value of 1 is output to the third node N3. If the data signal D is 0, signals of opposite values are output.

When the clock signal CK changes to the high level in the active mode, the first latch unit 500 and the second latch unit 600 invert the signal of the sense amplifier 100 and store the inverted signal in the first latch 510. . This is because the fourth and fifth transistors M4 and M5 of the node setting unit 200 enter the off state as the clock signal CK is set to the high level. This is also due to the turn-on of the fourteenth transistor M14 of the first latch portion 500 and the seventeenth transistor M17 of the second latch portion 600.

First, the first latch unit 500 inverts and stores the signal of the second node N2 that is the output of the sense amplifier 100. Since the clock signal CK is high level and the first mode control signal SC1 has a value of 1, the eleventh transistor M11 and the fourteenth transistor M14 are turned on.

When the second node N2 has a value of 1, the thirteenth transistor M13 is turned off, and the fifteenth transistor M15 is turned on. Therefore, the fifth node N5, which is an output terminal, is set to a value of zero, and the first latch 510 stores the data value of the fifth node N5. If the second node N2 has a value of zero, the fifteenth transistor M15 is turned off and the thirteenth transistor M13 is turned on. Therefore, the second node N2, which is an output terminal, is set to a value of one.

The second latch unit 600 which receives the signal of the third node N3 also has the same operation pattern. That is, the twelfth transistor M12 and the seventeenth transistor M17 are turned on, and the sixteenth transistor M16 is turned on or the eighteenth transistor M18 is turned on according to the signal level of the third node N3. As a result, by the complementary on / off operation of the two transistors M16 and M18, the second latch 610 inverts and stores the signal of the third node N3.

The inactive mode consists of three sub modes.

That is, it is composed of a sleep-in mode, a sleep mode, and a wake-up mode.

First, the inactive mode is a case where the second mode control signal SC2 is one. In the inactive mode, the data recovery unit 300 starts an operation.

First, in the sleep-in mode, the first mode control signal SC1 is set to 1 and the second mode control signal SC2 is also set to 1.

All transistors M10, M11, and M12 of the power control unit 400 are turned on by the first mode control signal SC1 set to 1. In addition, the sixth and eighth transistors M6 and M8 of the data recovery unit 300 are also turned on by the second mode control signal SC2 having a value of 1. FIG. However, the operation of the data recovery unit 300 has a different operation mode by the output signal Q and the inverted output signal / Q.

For example, when the output signal Q has a value of 1, the inverted output signal / Q has a value of zero. Therefore, the second node N2 is set to a value of zero. This turns on the thirteenth transistor M13 of the first latch portion and causes the output signal Q to maintain a value of 1, which is the value of the previous state. In addition, since the inverted output signal / Q has a value of 0, the third node N3 maintains the previous state. The inverted output signal / Q has a value of zero when the signal of the third node N3 has a value of one. As a result, in the sleep-in mode, the value of the output signal is maintained as it is regardless of the variation of the clock signal CK. In addition, as the mode control signals have a value of 1, the node setting unit 200 stops operating, and supply of a signal through the node setting unit 200 is cut off.

Then, the sleep mode is started. In the sleep mode, the first mode control signal SC1 is set to zero and the second mode control signal SC2 is set to one.

The first and second transistors M1 and M2 of the node setting unit 200 are turned on by the first mode control signal SC1 set to zero. Therefore, the second node N2 and the third node N3 are set to data one. In addition, the transistors M10, M11, and M12 of the power control unit 400 are turned off. Therefore, the supply path of the power through the ground voltage is cut off, the detection and amplification of the data signals D and / D through the sense amplifier 100, the update of the output signal Q through the first latch unit 500, and the second Update of the inverted output signal / Q through the latch unit 600 does not occur. Instead, only the maintenance of the output signal according to the operation of the first latch 510 and the second latch 610 is performed.

The wake-up mode then begins. In the wake-up mode, the first mode control signal SC1 is set to 1 and the second mode control signal SC2 is also set to 1. Thus, aspects of operation in the circuit occur identically to the sleep-in mode.

That is, the transistors M10, M11, and M12 of the power control unit 400 are turned on by the first mode control signal SC1 set to 1. In addition, the sixth and eighth transistors M6 and M8 of the data recovery unit 300 are also turned on by the second mode control signal SC2 having a value of 1. FIG. However, the operation of the data recovery unit 300 has a different operation mode by the output signals Q and / Q.

For example, when the output signal Q has a value of 1, the inverted output signal / Q has a value of zero. Therefore, the second node N2 is set to a value of zero. This turns on the thirteenth transistor M13 of the first latch portion and causes the output signal Q to maintain a value of one. In addition, since the inverted output signal / Q has a value of 0, the third node N3 maintains the previous state. The inverted output signal / Q has a value of zero when the signal of the third node N3 has a value of one. As a result, in the wake-up mode, the value of the output signal is maintained as it is regardless of the variation of the clock signal CK. In addition, the levels of the second node N2 and the third node N3 during operation in the active region are restored. In addition, as the mode control signals have a value of 1, the node setting unit 200 stops operating, and supply of power through the node setting unit 200 is cut off.

Subsequently, it enters the active mode again, and the flip-flop circuit performs normal data update and store operations.

In the aspect of operation of the flip-flop described above, the power control unit 400 is composed of transistors having a high threshold voltage. In the present exemplary embodiment, a transistor having a high threshold voltage refers to, for example, an absolute value of a threshold voltage higher than a portion of a transistor constituting the sense amplifier 100 or another component. When the transistors constituting the power controller 400 have a high threshold voltage, leakage power is minimized, and power consumption in the sleep mode of the flip-flop is minimized. In the sleep mode, the transistors constituting the power control unit 400 are turned off. Thus, transistors M10, M11 and M12 must have high current blocking capability. If the transistors constituting the power controller 400 have a low threshold voltage, they have a relatively high leakage current, and a constant leakage current is generated even in the sleep mode, thereby increasing the power consumption of the flip-flop as a whole. In order to solve this problem, the transistors of the power controller 400 are composed of transistors having a high threshold voltage.

In addition, the transistor M13 of the first latch unit 500 and the transistor M16 of the second latch unit 600 may also be configured of a transistor having a high threshold voltage. Since the transistors M13 and M16 are PMOS, they should be interpreted as having an absolute value of a high threshold voltage in a precise sense. This is because the transistors M13 and M16 are turned off in the sleep mode in which the sense amplifier 100 does not operate. When a leakage current occurs in the transistors M13 and M16, unwanted signal distortion occurs in the output signals Q and / Q. to be. Therefore, the two transistors M13 and M16 connected to the positive supply voltage VDD must be sufficiently cut off in the sleep mode. This, in turn, means that the two transistors described above must have a high threshold voltage.

In addition, the first latch 510 of the first latch unit 500 and the second latch 610 of the second latch unit 600 may also include transistors having a high threshold voltage. Although not shown in FIG. 2, the first latch 510 and the second latch 610 are also provided between the positive power supply voltage and the ground voltage, and receive driving power from two power supply voltages. Therefore, the greater the difference between the smoothness of operation and the input high level (typically denoted VIH on the data book) and the input low level (typically denoted VIL on the data book) that the transistor recognizes, the more apparent the latch operation will be. It is possible to maintain a constant level even in the slight fluctuation of the output signal Q or / Q.

In this embodiment, the positive power supply voltage VDD is set to 1V to 1.2V in a 100nm standard process. In addition, the absolute value of the high threshold voltage or the high threshold voltage is set to 0.18V to 0.2V. In this case, the threshold voltages of transistors having low threshold voltages other than those having high threshold voltages are preferably set to 0.09V to 0.1V. Of course, it is obvious to those skilled in the art that the magnitude of the high threshold voltage and the low threshold voltage can be changed according to the difference in the power supply voltage when the process precision and the power supply voltage are provided as rail-to-rail. It can be seen that the examples do not reduce the scope of the invention.

1 is a circuit diagram in which a flip-flop is implemented as a semiconductor circuit having one threshold voltage.

2 is a circuit diagram illustrating a flip-flop having multiple threshold voltages according to an embodiment of the present invention.

3 is a timing diagram illustrating an operation of the flip-flop circuit shown in FIG. 2 according to a preferred embodiment of the present invention.

Claims (16)

  1. In a flip-flop circuit operating in an inactive mode in which an active mode for updating and storing an input data signal and storing power and a supply of power are cut off, and only the data signal is stored,
    A sensing amplifier connected between a positive power supply voltage and a first node, for sensing the data signals at a high level of a clock signal in the active mode to generate signals complementary to a second node and a third node;
    A node setting unit connected between the positive power supply voltage and the second node and the third node and configured to set the second node and the third node to a high level in the inactive mode;
    A first latch part connected to the positive power supply voltage and configured to update an output signal or to maintain the output signal according to the level of the second node;
    A second latch part connected to the positive power supply voltage and configured to update an inverted output signal according to the level of the third node or to maintain the inverted output signal;
    A first recovery path connected to the first node to set the inverted output signal to the second node before entering the active mode, and before entering the active mode connected to the first node; A data recovery unit having a second recovery path for setting the output signal to a third node; And
    A transistor connected to a ground voltage and supplying power to the first latch unit, the second latch unit, the data recovery unit, and the sense amplifier, and configured to configure the data recovery unit, the node setting unit, or the sense amplifier unit; A flip-flop circuit comprising a power control unit having a threshold voltage higher than those.
  2. The flip-flop circuit of claim 1, wherein the node setting unit sets the second node and the third node to a high level when the sense amplifier stops the sense amplification operation in the active mode.
  3. The flip-flop circuit of claim 2, wherein the node setting unit supplies the positive power supply voltage to the second node and the third node in a sleep mode of the inactive mode.
  4. The method of claim 1, wherein the node setting unit operates according to a first mode control signal and a second mode control signal for determining an operation of a mode according to a level.
    A first transistor receiving the first mode control signal and coupled between the positive power supply voltage and the second node;
    A second transistor receiving the first mode control signal and coupled between the positive power supply voltage and the third node;
    A third transistor receiving the second mode control signal and connected between the positive power supply voltage and a fourth node;
    A fourth transistor configured to receive a clock signal and be coupled between the second node and the fourth node; And
    And a fifth transistor configured to receive the clock signal and be coupled between the third node and the fourth node.
  5. The method of claim 1, wherein the data recovery unit,
    A first recovery path connected between the first node and the second node and configured to set the inverted output signal to the second node according to an output signal and a second mode control signal; And
    And a second recovery path coupled between the first node and the third node and configured to set the output signal to the third node according to the second mode control signal and the inverted output signal. Flip-flop circuit.
  6. The flip-flop circuit of claim 5, wherein the first recovery path and the second recovery path of the data recovery unit operate complementarily according to the output signal in a sleep-in mode of the inactive mode.
  7. 6. The flip-flop circuit of claim 5, wherein the first recovery path and the second recovery path operate complementarily according to the output signal in the wake-up mode of the inactive mode.
  8. The method of claim 5, wherein the first recovery path,
    A sixth transistor configured to perform an on / off operation according to the second mode control signal and connected to the second node; And
    And a seventh transistor configured to perform an on / off operation according to the output signal and to be connected between the first node and the sixth transistor.
  9. The method of claim 5, wherein the second recovery path,
    An eighth transistor configured to perform an on / off operation according to a second mode control signal and connected to the third node; And
    And a ninth transistor configured to perform an on / off operation according to the inverted output signal and connected between the first node and the eighth transistor.
  10. The method of claim 1, wherein the power control unit,
    A tenth transistor connected between the first node and the ground voltage;
    An eleventh transistor connected between the first latch unit and the ground voltage; And
    And a twelfth transistor connected between the second latch unit and the ground voltage.
  11. The flip-flop circuit of claim 10, wherein the power control unit is turned on in the active mode to supply power to the first latch unit, the second latch unit, and the sense amplifier.
  12. The method of claim 1, wherein the first latch unit,
    A thirteenth transistor connected between the positive power supply voltage and a fifth node on which the output signal appears and performing an on / off operation according to a voltage of the second node;
    A fourteenth transistor connected to the fifth node and configured to receive the clock signal;
    A fifteenth transistor connected between the fourteenth transistor and the power control unit and configured to perform an on / off operation according to a voltage of the second node; And
    A first latch coupled to the fifth node, the first latch storing the output signal;
    And the transistors constituting the thirteenth transistor and the first latch have an absolute value of a threshold voltage higher than that of the fourteenth and fifteenth transistors.
  13. The method of claim 1, wherein the second latch unit,
    A sixteenth transistor connected between the positive power supply voltage and a sixth node having the inverted output signal and performing an on / off operation according to the voltage of the third node;
    A seventeenth transistor connected to the sixth node and receiving the clock signal;
    An eighteenth transistor connected between the seventeenth transistor and the power control unit and configured to perform an on / off operation according to a voltage of the third node; And
    A second latch coupled to the sixth node, the second latch storing the output signal;
    And the transistors constituting the sixteenth transistor and the second latch have an absolute value of a threshold voltage higher than that of the seventeenth and eighteenth transistors.
  14. In the operating method of the flip-flop circuit consisting of a sense amplifier, a node setting unit, a first latch unit, a second latch unit, a data recovery unit and a power control unit,
    Sensing a data signal at a high level of a clock signal to update the data signal or to operate in an active mode for storing the data signal; And
    In an inactive mode in which the power control unit having a higher threshold voltage than a transistor configuring the node setting unit, the data recovery unit, or the sense amplifier unit is turned off, and the operation of the sense amplifier unit is blocked to preserve the data signal stored in the active mode. A method of driving a flip-flop circuit comprising the step of operating.
  15. The method of claim 14, wherein the inactive mode,
    Operating in a sleep mode that cuts off power supply of the power control unit, operates the node setting unit, sets an output terminal of the sense amplifier unit to a positive power supply voltage, and blocks data updates of the first latch unit and the second latch unit; step; And
    Operating in the wake-up mode following the sleep mode and operating the power control unit and the data recovery unit to recover a signal in the active mode to the output terminal of the sense amplifier. How to drive a circuit.
  16. The method of claim 15,
    Before the sleep mode, operating the power control unit and the data recovery unit, and operating in the sleep-in mode to restore the signal in the active mode to the output terminal of the sense amplifier by blocking the operation of the node setting unit A method of driving a flip-flop circuit comprising a.
KR1020080111055A 2008-11-10 2008-11-10 Flip-Flop Circuit of having Multi-threshold Voltage CMOS and Method of driving the same KR101020940B1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100305710B1 (en) * 1999-08-03 2001-09-29 정명식 Sense amplifier-based CMOS flip-flop with enhanced output transition speed
KR100519787B1 (en) 2002-11-07 2005-10-10 삼성전자주식회사 Mtcmos flip-flop circuit capable of retaining data in sleep mode
KR20050104530A (en) * 2004-04-29 2005-11-03 삼성전자주식회사 Mtcmos flip-flop, mtcmos circuit including the same, and method for generating the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100305710B1 (en) * 1999-08-03 2001-09-29 정명식 Sense amplifier-based CMOS flip-flop with enhanced output transition speed
KR100519787B1 (en) 2002-11-07 2005-10-10 삼성전자주식회사 Mtcmos flip-flop circuit capable of retaining data in sleep mode
KR20050104530A (en) * 2004-04-29 2005-11-03 삼성전자주식회사 Mtcmos flip-flop, mtcmos circuit including the same, and method for generating the same

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