KR101013833B1 - Circuit connection structure and printed circuit board - Google Patents

Abstract

By gradually increasing the wiring widths of the signal wirings 104a, 104b, 105a, and 105b of the differential signal wirings 104 and 105 of the first and second sets, while suppressing attenuation in the wiring, The opening widths of the slits 104s and 105s formed in the GND layer 102 directly below each differential signal wiring are also changed. This realizes impedance matching. Further, by alternately arranging the wide and narrow sides of the wiring widths of the two sets of differential signal wirings 104 and 105, the width of the entire wiring area is reduced.

Description

CIRCUIT CONNECTION STRUCTURE AND PRINTED CIRCUIT BOARD}

The present invention relates to a printed wiring board which transmits digital signals at high speed.

In printed wiring boards, since the signal is attenuated by the DC resistance component of the wiring conductor, the transmission waveform quality is adversely affected. Therefore, the longer the signal wiring to be transmitted is, the larger the attenuation becomes and the signal integrity of the signal is lowered. In recent years, it has been found that for signals in the frequency band of 1 GHz or more, the effect of skin effect and dielectric loss is very large, resulting in much larger attenuation of the signal. Therefore, in the signal transmission of the gigahertz order in the printed wiring board, the attenuation of the signal has become one of the problems to be solved in order to secure the integrity of the signal.

As an index for evaluating the attenuation of the signal, the transmission characteristic (S21) parameter is known. The transmission characteristic (S21) parameter is obtained by forming a transmission line as a network as shown in Fig. 13A, and quantifying the ratio (transmittance) of the signal transmitted from the input port Port1 to the output port Port2 of the network in this case. . In addition, it is the transmission characteristic (S12) parameter that the ratio (transmittance) of the signal transmitted from the input terminal Port2 of the network to the output terminal Port1 is quantified.

Using this transmission characteristic S121, the relationship between the frequency and attenuation of the signal to be transmitted will be described. FIG. 13B shows an example of a general transmission characteristic S21 of a signal transmitted through a signal wiring provided in a printed wiring board. In Fig. 13B, the vertical axis represents the transmission characteristic S21 (dB) of the S parameter, and the horizontal axis represents the frequency (Hz) of the signal to be transmitted. In the frequency band of 1 GHz or less, the attenuation by the DC resistance of the wiring conductor is dominant, and the attenuation gradually increases as the frequency increases. This phenomenon is caused by skin effect or dielectric loss of high frequency signal. In particular, in the frequency band of 1 GHz or more, since the loss due to the skin effect and the dielectric loss is larger than the DC loss, the attenuation increases rapidly. Moreover, a large attenuation is observed at a specific frequency, which is due to resonance between the inductance component and the capacitance component of the wiring conductor.

The deterioration of signal integrity includes not only the signal attenuation but also the impedance mismatch of the wiring. In other words, if a mismatch occurs in the impedance of the wiring, the transmission signal repeatedly reflects at the mismatch point, thereby greatly reducing the integrity of the signal. The impedance mismatch greatly varies not only at the connection point of the wiring, but also due to changes in the width of the wiring, the distance from other wiring, and the dielectric constant around the wiring. A typical printed wiring board is designed such that, for example, the impedance characteristic is unified to 50 Ω in single-ended wiring and 100 Ω in differential wiring.

The impedance Zo of the wiring of the microstrip line structure can be calculated by the following formula (1).

......(식 1)

(Equation 1)

In Equation 1, epsilon r is the dielectric constant of the dielectric layer of the printed wiring board to be the lower layer of the wiring layer, h is the thickness of the insulating layer from the GND layer to the wiring layer, W is the width of the wiring, and t is the thickness of the wiring.

In addition, when the wiring at this time is a differential signal wiring, the differential impedance Zdiff can be calculated by the following expression (2).

Zdiff 2 × Zo (1-0.48 x exp (-0.96 x S / h)) (Equation 2)

In Equation 2, h is the thickness from the GND layer to the wiring layer, and S is the spacing between two wirings forming the differential wiring.

The impedance Zo of the strip line structure can be calculated by the following expression (3).

......(식 3)

(Equation 3)

In Equation 3, epsilon r is the dielectric constant of the dielectric layer of the printed wiring board to be the lower layer of the wiring layer, W is the width of the wiring, and t is the thickness of the wiring.

In the case where the wiring is a differential signal wiring, the differential impedance Zdiff can be calculated by the following expression (4).

Zdiff 2 × Zo (1-0.374 x exp (-2.9 x S / h)) (Equation 4)

In Equation 4, h is the spacing between two GND layers sandwiching the wiring, and S is the spacing between two wirings forming the differential wiring.

A countermeasure against impedance mismatch due to a change in wiring width has been proposed in Japanese Patent Laid-Open No. 2006-173239. This patent document describes a structure when connecting wiring on a printed wiring board to a connector. Since the land size of the connector is set larger than the width of the wiring, the width of the wiring in the vicinity of the land is set larger in accordance with the land size of the connector. In this case, the impedance mismatch caused by the large width of the wiring is suppressed by setting the lower dielectric layer in a portion where the width of the wiring is enlarged.

Japanese Unexamined Patent Application Publication No. 2005-340506 discloses a method of correcting impedance mismatch by changing the width of a wiring. This patent document describes a differential signal wiring having a first wiring and a second wiring for interconnecting a driver element and a receiver element mounted on a printed wiring board. The first wiring and the second wiring are connected to respective electrode terminals of the driver element and the receiver element. In this case, since the space | interval between electrode terminals is set larger than the width between 1st and 2nd wiring, the space | interval between the 1st wiring and 2nd wiring provided in parallel is gradually increased in the vicinity of an electrode terminal, The first wiring and the second wiring are connected to each electrode terminal. By increasing the width of the impedance between the first and the second wiring as the distance between the first and the second wiring increases as the gap between the first and the second wiring increases. I suppress it.

As a countermeasure for suppressing the deterioration of the integrity of a signal due to the attenuation of the signal by the DC resistance component of the wiring conductor, it has conventionally been known to increase the wiring width. By enlarging the wiring width, the cross-sectional area through which signals are transmitted becomes large, so that the DC resistance component can be reduced.

However, when wiring width is made thick, the impedance characteristic of wiring will fall. If the impedance characteristic falls, impedance mismatch occurs, and the integrity of the signal falls.

The impedance characteristic is improved by widening the space | interval between wirings. Therefore, when the wiring width is set large, the impedance characteristic can be set to a predetermined value by widening the interval between the wirings. However, when the distance between the wirings is widened, the wiring area on the printed wiring board increases, and at the same time, it is necessary to set the terminal width of the semiconductor package or connector to which the wiring is connected. This is a major obstacle to miniaturization of printed wiring boards and semiconductor packages in recent years.

Accordingly, it is an object of the present invention to provide a printed wiring board which ensures signal integrity by suppressing signal attenuation and impedance mismatch without increasing the wiring area of the printed wiring board.

The printed wiring board of the present invention has a differential signal wiring layer in which at least two sets of differential signal wiring are arranged in parallel, and a GND layer disposed via an insulating layer under the differential signal wiring layer. The at least two sets of differential signal wirings interconnect the first area and the second area of the printed wiring board. The two wirings constituting one pair of the differential signal wirings of the two sets of differential signal wirings have the same wiring width from the first region to the second region at the same rate and the distance between the two wirings is constant. . The other pair of differential signal wirings of the two sets of differential signal wirings are arranged adjacent to the set of differential signal wirings, and the two wirings constituting the other set of differential signal wirings are separated from the first region. The wiring width is increased at the same rate toward the region, and the spacing between the two wirings is constant. The GND layer is formed under the set of differential signal wirings, and includes a first slit having an opening width decreasing from the first region to the second region, and under the other set of differential signal wirings. A second slit is formed in which the opening width increases from the first region to the second region.

Other features of the present invention will become apparent from the following description of exemplary embodiments with reference to the accompanying drawings.

According to the present invention, signal integrity can be secured by suppressing signal mismatch and impedance mismatch. In this case, since the wiring band of a printed wiring board does not increase, a printed wiring board and a semiconductor package can be miniaturized.

Exemplary embodiments of the invention are described below with reference to the accompanying drawings.

(First Embodiment)

FIG. 1: is a schematic diagram which shows the printed circuit board which mounted the electronic component on the printed wiring board which concerns on 1st Embodiment. In FIG. 1, the printed circuit board includes a plurality of differential signal wirings 12 for connecting the printed wiring board 100, the semiconductor package 10, the connector 11, and the semiconductor package 10 to the connector 11. Has The semiconductor package 10 is mounted in the first region, and the connector 11 is mounted in the second region.

The printed wiring board according to the present embodiment has a signal wiring layer and a GND layer laminated at least through an insulating layer.

FIG. 2A, FIG. 2B, and FIG. 3A and FIG. 3C show two pairs (or two pairs) of differential signal wirings among the differential signal wirings 12 shown in FIG. 2A is a plan view when the printed wiring board is seen from above, and FIG. 2B is a plan view of the GND layer. 3A and 3B are sectional views 3A-3A and 3B-3B of the printed wiring board 100 in FIGS. 2A and 2B.

The printed wiring board 100 has a structure in which the insulating layer 103, the GND layer 102, the insulating layer 101, and the differential signal wiring layer 106 are stacked. In the signal wiring layer 106, differential signal wirings 104 and 105 are arranged in parallel. The differential signal wiring 104 has two wirings 104a and 104b, and the differential signal wiring 105 has two wirings 105a and 105b.

As shown in Fig. 3A, the wiring widths of the wirings 104a and 104b are set to Wa1 and Wa2, and the interval between the wiring 104a and the wiring 104b is set to Wga. In addition, the wiring widths of the wirings 105a and 105b are set to Wb1 and Wb2, and the interval between the wiring 105a and the wiring 105b is set to Wgb. The interval between the differential signal wirings 104 and 105 is Ws, and the width of the entire differential signal wirings 104 and 105 is W.

In FIG. 2A, the widths of the wirings 104a and 104b are narrowed at the same ratio in the direction indicated by the arrow X, and are always the same at each position in the arrow X direction. The distance Wga between the wiring 104a and the wiring 104b is always constant regardless of the width of the wiring 104a and 104b.

Similarly, the widths Wb1 and Wb2 of the wirings 105a and 105b are increasing at the same rate in the arrow X direction, and are always the same at each position in the arrow X direction. The interval between the wiring 105a and the wiring 105b is always constant regardless of the width of the wiring 105a and 105b.

Also, if signals of the same characteristics are transmitted through the differential signal wirings 104 and 105, the ratio of the widths of the wirings 104a and 104b decreases in the direction of the arrow X and the wirings 105a and 105b. The ratios in which the widths increase in the direction of the arrow X can be set equal to each other. Therefore, the interval Ws between the differential signal wirings 104 and 105 and the width W of the entirety of the differential signal wirings 104 and 105 can be set to be constant, thereby minimizing the wiring area.

In the GND layer 102 shown in FIG. 2B, slits 104s and 105s are formed immediately below the differential signal wirings 104 and 105. As shown in FIG. The term "slit" refers to a band in which conductors constituting GND are not provided. As shown in FIG. 2A, the wiring 104 is wider in the direction opposite to the arrow X direction, and the wiring 105 is wider in the arrow X direction. Usually, when the wiring width becomes wider, the impedance characteristic is lowered. However, in the present invention, the slit is disposed in the GND layer under the wiring layer to cancel the lowered impedance characteristic.

The slit width of the slit 104s is Wsa, and the slit width of the slit 105s is Wsb. As the wiring widths Wa1 and Wa2 of the wirings 104a and 104b shown in FIGS. 2A and 3A narrow toward the arrow X direction, the slit width Wsa of the slit 104s gradually narrows. That is, the slit width Wsa in the 3A-3A cross section shown in FIG. 3A is larger than the slit width Wsa in the 3B-3B cross section shown in FIG. 3B. In addition, as the wiring widths Wb2 and Wb1 of the wirings 105a and 105b shown in FIGS. 2A and 3A widen toward the arrow X direction, the slit width Wsb of the slit 105s gradually increases. That is, the slit width Wsb taken along the 3A-3A cross section shown in FIG. 3A is narrower than that taken along the 3B-3B cross section shown in FIG. 3B.

Although FIG. 2A and FIG. 2B, and FIG. 3A and FIG. 3B show two sets of differential signal wirings, alternately as shown in FIG. 4A and FIG. 4B while maintaining the relationship between the dimensions described in the above embodiments. It is also possible to arrange three or more sets of differential signal wirings 104 and 105. In this case, the differential impedance can be matched by alternately arranging the wide side and the narrow side of the differential signal wiring and setting the distance between all the differential signal wiring to be constant.

Example 1

Simulation models corresponding to FIGS. 2A and 2B and FIGS. 3A and 3B were created. The model is designed so that the differential impedance of the differential signal wirings 104 and 105 is 100?. In the simulation model according to the first embodiment, the wiring widths Wa2 and Wa1 of the respective wirings 104a and 104b of the differential signal wiring 104 gradually move from 0.15 mm to 0.10 mm toward the arrow X direction. It is getting narrower. On the other hand, the wiring widths Wb2 and Wb1 of the respective wirings 105a and 105b of the differential signal wiring 105 gradually increase from 0.10 mm to 0.15 mm toward the arrow X direction, respectively. The interval Wga between the wiring 104a and the wiring 104b and the interval Wgb between the wiring 105a and the wiring 105b were 0.15 mm, respectively. The two sets of differential signal wirings have the same structure, and the distance Ws between the jaws 104 and 105 of the differential signal wiring was 0.5 mm. In this case, the entire width W of the two differential signal wirings 104 and 105 was 1.3 mm. The thickness of the insulating layer was 0.1 mm, and the length of the differential signal wiring was 50 cm.

The width Wsa of the slit of the GND layer formed under the differential signal wiring 104 is gradually narrowed from 0.15 mm to 0 mm in the arrow X direction. The width Wsb of the slit of the GND layer provided below the differential signal wiring 105 gradually increases from 0 mm to 0.15 mm in the direction of the arrow X.

The electromagnetic field simulation and the circuit simulation of the simulation model in Example 1 were performed to calculate the transmission characteristics S21 in the arrow X direction. The result was shown in FIG. 6 graphically. As a result of the simulation, the differential impedance of the differential signal wirings 104 and 105 was about 100?.

In addition, the above-mentioned transmission characteristic S21 and the transmission characteristic S12 of the arrow X direction and the reverse direction in the model of Example 1 are shown in FIG. The transmission characteristic S21 and the transmission characteristic S12 almost overlap in the graph of FIG. That is, the results show that the transmission characteristics when the wires are transmitted from the wider side are the same as the transmission characteristics when they are transmitted from the narrower side of the wire, and the transmission characteristics do not change with the direction of the differential signal wiring. It does not indicate.

(Comparative Example 1)

The simulation model of the printed wiring board of the comparative example 1 is demonstrated with reference to FIG. 5A and 5B. 5A is a plan view of the printed wiring board, and FIG. 5B is a 5B-5B cross-sectional view of the printed wiring board 600 in FIG. 5A. The printed wiring board 600 has a structure in which the GND layer 602, the insulating layer 601, and the wiring layer 603 are stacked. Differential signal wirings 604 and 605 are arranged in parallel in the wiring layer 603. The wirings 604a and 604b forming the differential signal wiring 604 and the wirings 605a and 605b forming the differential signal wiring 605 are all the same wiring width We, and the width of each wiring is the respective wiring width. Is constant in the extending direction. In addition, the space | interval between wiring 604a and 604b and the space | interval between wiring 605a and 605b are the same value Wg, and are constant in the extension direction of each wiring. In addition, the width W of the two sets of differential signal wirings 604 and 605 is also constant in the extending direction of each wiring. In addition, slits are not formed in the GND layer 602 under the wiring layer 603.

The simulation model of Comparative Example 1 was designed using (Equation 1) and (Equation 2) so that the differential impedance was almost 100 Ω using the same wiring area width as that of Example 1 for comparison with Example 1. . The wiring width We of the wirings 604a, 604b, 605a, and 605b is 0.11 mm, the spacing Wg between the wiring 604a and the wiring 604b, and between the wiring 605a and the wiring 605b. The thickness Wg of all was 0.18 mm. The interval Ws between the differential signal wirings 604 and 605 was 0.5 mm. Therefore, the total width of the two sets of differential signal wirings was 1.3 mm as in the first embodiment. The thickness of the insulating layer was 0.1 mm, the thickness t of the conductor was 0.035 mm, and the length of the differential signal wiring was 50 cm.

The electromagnetic field simulation and the circuit simulation of the simulation model in Comparative Example 1 were carried out, and the transmission characteristics S ₂₁ were calculated. The result was shown in FIG. 6 graphically.

As shown in Fig. 6, in the first embodiment, the transmission characteristic S21 is greatly deteriorated due to the resonance point at 4 GHz. On the other hand, in the case of Comparative Example 1, the transmission characteristic S21 is greatly deteriorated due to the resonance point near 2.7 GHz. Therefore, it can be seen that the transmission characteristic S21 of Example 1 is significantly improved compared with Comparative Example 1. That is, when the same impedance characteristic is maintained in the width of the same wiring region, the configuration of Example 1 is reduced to a greater width than that of Comparative Example 1.

(Comparative Example 2)

Next, the wiring width We of the wirings 604a, 604b, 605a, and 605b of the simulation model of Comparative Example 1, the spacing Wg between the wiring 604a and the wiring 604b, and the wiring. A simulation model of Comparative Example 2 was created in the same manner as in Comparative Example 1 except that the distance Wg between 605a and the wiring 605b was changed. In Comparative Example 2, the width of the wiring region was not taken into consideration and was designed such that the resonance point of the transmission characteristic S21 was around 4 GHz as in Example 1.

In order to improve the transmission characteristic (S21) compared with the comparative example 1, it is necessary to set only the width | variety of each wiring widely. However, if the wiring width is set wide, the single ended impedance is lowered. Therefore, in order to maintain the differential impedance at 100?, It is necessary to increase the distance between the differential signal wirings. The simulation model of Comparative Example 2 was designed using (Formula 1) and (Formula 2) so that the differential impedance was almost 100 ?. The widths We of the wirings 604a, 604b, 605a, and 605b are 0.14 mm, and the interval Wg between the wiring 604a and the wiring 604b, and the wiring 605a and the wiring 605b. The interval Wg between them was all 0.4 mm. The distance Ws between the two sets of differential signal wirings 604 and 605 was 0.5 mm. Therefore, the total width of the two sets of differential signal wirings was 1.86 mm as in the first embodiment. The thickness of the insulating layer was 0.1 mm, and the length of the differential signal wiring was 50 cm.

The electromagnetic field simulation and the circuit simulation of the simulation model of Comparative Example 2 were carried out, and the transmission characteristic (S21) was calculated. The result was shown in FIG. 6 graphically.

As shown in FIG. 6, the transmission characteristic S21 of the comparative example 2 has a resonance point near 4 GHz similar to Example 1, and the attenuation amount is almost the same. However, while the total wiring width of Example 1 is 1.3 mm, the width of the entire wiring area of Comparative Example 2 is 1.86 mm, which indicates that the width of the wiring area becomes very large.

The simulation parameters of Example 1 and Comparative Examples 1 and 2 are summarized in Table 1.

(2nd Embodiment)

8A and 8B and 9A and 9B show a second embodiment of the present invention. The printed wiring board 200 is interposed between the insulating layer 203, the GND layer 202, the insulating layer 201, the differential signal wiring layer 206, and the differential signal wiring layer 206 via the insulating layer 207. The formed GND layer 208 has a stacked structure. 8A is a plan view of the differential signal wiring layer 206 of the printed wiring board 200, and FIG. 8B is a plan view of the GND layer 208. 9A and 9B are cross-sectional views 9A-9A and 9B-9B of the printed wiring board 200 in FIG. 8A, respectively. In the differential signal wiring layer 206, differential signal wirings 204 and 205 are arranged.

The differential signal wiring 204 has two wirings 204a and 204b, and the differential signal wiring 205 has two wirings 205a and 205b. In addition, the slit 204s and the slit 205s are formed in the GND layer 202 similarly to the first embodiment. Unlike the case of the GND layer 202, the GND layer 208 is not provided with slits.

In the second embodiment, the first embodiment shown in FIGS. 2A and 2B, and FIGS. 3A and 3B differs from the first through the insulating layer 207 on the differential signal wirings 204 and 205. Thus, the GND layer 208 is disposed. The effect of the present invention can be realized not only by the microstrip structure in the first embodiment but also by the strip structure in the second embodiment. In particular, from the viewpoint of radiation noise, the second embodiment is more effective.

(Third Embodiment)

10A to 10C and Figs. 11A and 11B show a third embodiment of the present invention. The printed wiring board 300 has an insulating layer 307 directly over the insulating layer 303, the GND layer 302, the insulating layer 301, the differential signal wiring layer 306, and the differential signal wiring layer 306. The formed GND layer 308 has a stacked structure together. 10A is a plan view of the differential signal wiring layer 306 of the printed wiring board 300 viewed from above, and FIG. 10B is a plan view of the GND layer 308. 11A and 11B are cross-sectional views 11A-11A and 11B-11B of the printed wiring board 300 in FIG. 10A, respectively. In the differential signal wiring layer 306, differential signal wirings 304 and 305 are arranged.

The differential signal wiring 304 has two wirings 304a and 304b, and the differential signal wiring 305 has two wirings 305a and 305b. In the GND layer 302, slits 304s and slit 305s are formed as in the case of the first embodiment. In the GND layer 308, as in the case of the first embodiment, slits 304t and slits 305t are formed.

The third embodiment differs from the second embodiment shown in Figs. 8A and 8B, and Figs. 9A and 9B in the slit 304t and the GND layer disposed on the differential signal wirings 304 and 305. (305t) is formed. The effect of the present invention is that the impedance of the differential signal wirings 304 and 305 is adjusted by the slit of two GND layers sandwiched between the differential signal wirings 304 and 305. Therefore, the impedance adjustment range of the differential signal wirings 304 and 305 is wide, and it is possible to widen the wiring width of the wirings 304a, 304b, 305a, and 305b.

(Fourth Embodiment)

12A and 12B show a fourth embodiment of the present invention. In this embodiment, what is different from the 1st embodiment shown to FIG. 2A and 2B is the structure of the slit formed in the GND layer 102. FIG. 12A and 12B, the same members as those in FIGS. 2A and 2B are denoted by the same reference numerals, and description thereof is omitted. 12A and 12B as in the case of FIGS. 2A and 2B, the left end of the differential signal wiring is the first region of the printed wiring board and the right end is the second region of the printed wiring board.

12A and 12B, four slits 404a, 404b, 405a, and 405b are formed in the GND layer 102. The slit 404a is formed just under the wiring 104a of the signal wiring layer 106, and the opening width thereof becomes wider as the width of the wiring 104a increases from the second region to the first region. The slit 404b is formed directly under the wiring 104b, and as the width of the wiring 104b increases from the second region to the first region, the opening width thereof becomes larger as in the case of the slit 404a. .

Further, the slit 405a is formed just under the wiring 105a of the signal wiring layer 106, and the opening width thereof is narrowed as the width of the wiring 105a is narrowed from the second region to the first region. . Further, the slit 405b is formed just under the wiring 105b, and as the width of the wiring 105b is narrowed from the second region to the first region, the opening width is narrow as in the case of the slit 405a. ought.

Thus, by forming the slit for each wiring, the differential impedance of the differential wiring can be adjusted more precisely.

According to the present invention, it is possible to ensure signal integrity by suppressing signal attenuation and impedance mismatch. In this case, since the wiring area of the printed wiring board does not increase, the printed wiring board and the semiconductor package can be miniaturized.

Although the invention has been described with respect to exemplary embodiments, it is to be understood that the invention is not limited to the exemplary embodiments disclosed. The following claims are to be accorded the broadest interpretation so as to encompass all such modifications and equivalent constructions and functions.

1 is a plan view of a printed circuit board according to a first embodiment;

2A and 2B are plan views showing a printed wiring board according to Example 1;

3A and 3B are sectional views showing a printed wiring board according to Example 1;

4A and 4B are plan views showing a printed wiring board according to the first embodiment;

5A and 5B are a plan view and a sectional view of a printed wiring board according to Comparative Example 1, respectively;

6 is a graph showing the transmission characteristics (S21) of Example 1 and Comparative Examples 1 and 2;

7 is a graph showing the transmission characteristics S21 and S12 of Example 1;

8A and 8B are plan views showing a printed wiring board according to a second embodiment;

9A and 9B are cross-sectional views showing a printed wiring board according to a second embodiment;

10A, 10B, and 10C are plan views showing a printed wiring board according to the third embodiment;

11A and 11B are cross-sectional views illustrating a printed wiring board according to a third embodiment;

12A and 12B are cross-sectional views showing a printed wiring board according to a fourth embodiment;

13A and 13B are schematic diagrams and graphs illustrating transmission characteristics S21.

<Description of the symbols for the main parts of the drawings>

(100), (200), (300): printed wiring board

(101), (103), (201), (203), (207), (303), (307), and (601): insulating layer

(102), (202), (208), (301), (302), (308), and (305): GND layer

(104), (105), (204), (205), (304), (305), (604), and (605): differential signal wiring

104a, 104b, 105a, 105b, 204a, 204b, 205a, 205b, 304a, 304b, 305a, 305b, 604a ), 604b, 605a, 605b: wiring

(104s), (105s), (204s), (205s), (304s), (305s), (304t), (305t), (404a), (404b), (405a), (405b): slit

(106), (206), (306): differential signal wiring layer (600): printed circuit board

603: wiring layer

Claims (7)

A GND layer 102; An insulating layer 101; A signal wiring layer 106 adjacent to the GND layer via an insulating layer, interconnecting the first region and the second region of the printed wiring board, and having at least two sets of differential signal wirings 104 and 105 arranged in parallel. Made of Of the two sets of differential signal wirings, the two wirings 104a and 104b constituting the pair of differential signal wirings 104 decrease in the same width from the first region to the second region, In addition, the interval between the two wirings 104a and 104b is constant, Of the two sets of differential signal wirings, the other set of differential signal wirings 105 are disposed adjacent to the set of differential signal wirings 104 and the two wirings constituting the other set of differential signal wirings 105 ( 105a) and 105b increase the width of wiring from the first region to the second region at the same ratio, and the spacing between the two wiring 105a and 105b is constant, The GND layer has a first slit (104s) formed under the set of differential signal wirings, the opening width of which decreases from the first region to the second region, and under the other set of differential signal wirings. And a second slit (105s) having an opening width from the first region to the second region, wherein the second slit (105s) is formed. The method of claim 1, The rate at which the wiring widths of the two wirings 104a and 104b constituting the pair of differential signal wirings 104 decreases, and the two wirings 105a constituting the other set of differential signal wirings 105 And the ratio at which the wiring width of 105b increases is the same, and the wiring area widths of the two sets of differential signal wirings 104 and 105 are constant across the first area and the second area. Printed wiring board, characterized in that. The method of claim 2, The ratio in which the opening width of the first slit 104s decreases and the ratio in which the opening width of the second slit 105s increases are identical to each other between the first region and the second region. Printed wiring board. The method of claim 1, A printed wiring board comprising a GND layer (208) disposed over the signal wiring layer via an insulating layer. The method of claim 4, wherein A third slit (304t) formed on the set of differential signal wirings, the opening width of which is reduced from the first region to the second region, in the GND layer disposed on the signal wiring layer; And a fourth slit (305t) formed on the set of differential signal wirings and having an opening width increasing from the first region to the second region. A GND layer 102; An insulating layer 101; A signal wiring layer 106 adjacent to the GND layer via an insulating layer, interconnecting the first region and the second region of the printed wiring board, and having at least two sets of differential signal wirings 104 and 105 arranged in parallel. Made of Of the two sets of differential signal wirings, the two wirings 104a and 104b constituting the pair of differential signal wirings 104 decrease in the same width from the first region to the second region. In addition, the spacing between the two wirings 104a and 104b is constant, Of the two sets of differential signal wirings, the other set of differential signal wirings 105 is arranged adjacent to the set of differential signal wirings 104 and includes two wirings constituting the other set of differential signal wirings 105 ( 105a) and 105b increase the width of wiring from the first region to the second region at the same ratio, and the spacing between the two wiring 105a and 105b is constant, The GND layer is formed under the set of differential signal wirings so as to correspond to the two wirings constituting the set of differential signal wirings, and the opening width decreases from the first region to the second region. Two slits 404a and 404b and two wirings under the other pair of differential signal wirings are formed corresponding to the second pair of differential signal wirings, and the first area is formed from the first region. A printed wiring board, characterized in that two slits (405a) and (405b) having an opening width increasing toward two regions are formed. A printed wiring board and a first electronic component and a second electronic component mounted on the printed wiring board, respectively, The printed wiring board, A GND layer 102; An insulating layer 101; Adjacent to the GND layer via the insulating layer, the first electronic component and the second electronic component mounted on a printed wiring board are interconnected, and at least two sets of differential signal wirings 104 and 105 are disposed in parallel. The signal wiring layer 106 is provided, Of the two sets of differential signal wirings, the two wirings 104a and 104b constituting the pair of differential signal wirings 104 are provided at the same ratio of wiring width from the first electronic component to the second electronic component. Decrease, and the width between the two wirings 104a and 104b is constant, Of the two sets of differential signal wirings, the other set of differential signal wirings 105 are arranged adjacent to the set of differential signal wirings, and the two wirings 105a constituting the other set of differential signal wirings 105 are provided. And 105b, the wiring width increases from the first electronic component to the second electronic component at the same rate, and the spacing between the two wiring 105a and 105b is constant, A first slit (104b) formed under the set of differential signal wirings, the opening width of which is reduced from the first electronic component to the second electronic component, and the other set of differential signal wirings in the GND layer; And a second slit (105s) formed below the second electronic component, the opening width of which is increased from the first electronic component to the second electronic component.

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