KR101007715B1 - Liquid crystal display apparatus and method of manufacturing the same - Google Patents

Abstract

Disclosed are a liquid crystal display device and a method for manufacturing the same, wherein the process is simplified, has a reduced size, and can reduce peeling of a substrate. The liquid crystal display device includes a first substrate, a second substrate, a liquid crystal layer, and a sealant. The first substrate includes an upper substrate, a common electrode, and a seal line formed at a periphery of the upper substrate. The second substrate includes a lower substrate, a thin film transistor, a common voltage line formed at a portion corresponding to the seal line, and having a common voltage applied thereto, and an organic layer having a first opening exposing a portion of the common voltage line. And opposes the first substrate. The sealant is formed at a portion corresponding to the seal line and electrically connects the common electrode and the common voltage line through the first opening to include a conductive material. Thus, the use of conductive sealants and openings can simplify the process, reduce the size, and reduce the exfoliation of the upper substrate.

Description

Liquid crystal display and its manufacturing method {LIQUID CRYSTAL DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME}

1 is a plan view illustrating a liquid crystal display according to a first exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along line AA ′ in FIG. 1.

3A to 3K are cross-sectional views illustrating a method of manufacturing the liquid crystal display shown in FIG. 1.

4 is a plan view illustrating a liquid crystal display according to a second exemplary embodiment of the present invention.

FIG. 5 is a cross-sectional view taken along line BB ′ in FIG. 4.

6A to 6K are cross-sectional views illustrating a method of manufacturing the liquid crystal display shown in FIG. 4.

Explanation of symbols on the main parts of the drawings

50: seal line 70: display area

100: upper substrate 102: black matrix

104: color filter 106: common electrode

108: liquid crystal layer 110: spacer                 

112 pixel electrode 114 organic film

116: inorganic insulating film 118a: source electrode

118a ': data line 118b: gate electrode

118b ': gate line 118c: drain electrode

118d: storage capacitor line 118e: common voltage line

119 thin film transistor 120 lower substrate

122: sealant 130: first opening

132a, 132b: second opening

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a method for manufacturing the same, and more particularly, to a liquid crystal display device and a method for manufacturing the same, which can simplify the process, have a reduced size, and reduce the peeling of the substrate.

A liquid crystal display (LCD) applies an electric field to a liquid crystal material having an anisotropic dielectric constant injected between an array substrate and a color filter substrate on which a thin film transistor is formed. The display device obtains a desired image signal by controlling the intensity of the electric field and controlling the amount of light transmitted through the substrate.

Conventional liquid crystal display devices include a first substrate, a second substrate, a liquid crystal layer and a sealant.

The first substrate includes an upper substrate, a black matrix (BM), a color filter, a common electrode, and a spacer, and the second substrate includes a lower substrate, a thin film transistor, An inorganic insulating film, an organic film, and a pixel electrode are included. The liquid crystal layer is interposed between the first substrate and the second substrate and sealed by a sealant.

In order to manufacture the liquid crystal display, first, a gate electrode, a gate line, a storage capacitor line, and a common voltage line are formed on a lower substrate. Subsequently, a gate insulating film is coated on the lower substrate on which the gate electrode, the gate line, and the storage capacitor line are formed. Thereafter, a source electrode and a drain electrode are formed on the gate insulating layer. The source electrode and the drain electrode are formed using a deposition, patterning, and etching process.

Subsequently, an inorganic insulating film and an organic film are sequentially applied to the entire surface of the lower substrate on which the thin film transistor and the storage capacitor line are formed. Thereafter, a portion of the organic layer and the inorganic insulating layer are removed to form a contact hole exposing a portion of the drain electrode.

Subsequently, a transparent conductive material is applied onto the organic film on which the contact hole is formed. The transparent conductive material may be indium tin oxide (ITO) or indium zinc oxide (IZO). Subsequently, a part of the transparent conductive material is removed by patterning and etching to form a pixel electrode on a part of the surface of the organic layer.

Accordingly, a second substrate including the lower substrate, the thin film transistor, the storage capacitor line, the common voltage line, the inorganic insulating film, the organic film, and the pixel electrode is formed.

Subsequently, a black matrix is formed on the upper substrate. Subsequently, a color filter is formed on the upper substrate on which the black matrix is formed. Thereafter, a transparent conductive material is coated on the upper substrate on which the black matrix and the color filter are formed to form a common electrode to form the first substrate. Subsequently, a spacer is formed on the common electrode to maintain a cell gap between the first substrate and the second substrate.

Thus, a first substrate including the upper substrate, the black matrix, the color filter, the common electrode, and the spacer is formed.

Thereafter, a sealant is formed along a seal line on the first substrate. The seal line is disposed along the periphery of the first substrate.

Subsequently, a short point is formed on the first substrate. The short point is formed at a position corresponding to the common voltage line. The common electrode of the first substrate is electrically connected to the common voltage line of the second substrate by the short point. The short point includes a conductive spacer.

Subsequently, the first substrate and the second substrate are bonded to each other. Subsequently, a liquid crystal layer is interposed between the first substrate and the second substrate.                         

Finally, the liquid crystal layer is sealed.

However, when the process of forming the short point is performed separately, the process becomes complicated and the cost increases. In addition, since the common voltage line is formed separately from the sealant, the size of the liquid crystal display increases.

In addition, since the adhesion between the sealant and the organic film is weak, a problem arises in that the first substrate is peeled off from the second substrate.

SUMMARY OF THE INVENTION A first object of the present invention for solving the above problems is to provide a liquid crystal display device in which the process is simplified, has a reduced size, and can reduce the peeling of the substrate.

A second object of the present invention is to provide a method for manufacturing a liquid crystal display device suitable for manufacturing the liquid crystal display device.

A liquid crystal display according to an exemplary embodiment of the present invention for achieving the first object includes a first substrate, a second substrate, a liquid crystal layer, and a sealant. The first substrate includes an upper substrate, a common electrode formed on the front surface of the upper substrate, and a seal line formed at a periphery of the upper substrate. The second substrate may include a lower substrate, a thin film transistor formed on a surface of the lower substrate, a common voltage line formed at a portion corresponding to the seal line, and having a common voltage applied thereto, and a lower portion formed with the thin film transistor and the common voltage line. And an organic layer formed on an entire surface of the substrate and having a first opening that exposes a portion of the common voltage line, and faces the first substrate. The liquid crystal layer is interposed between the first substrate and the second substrate. The sealant is formed at a portion corresponding to the seal line, and electrically connects the common electrode and the common voltage line through the first opening to include the conductive material, and connects the first substrate and the second substrate. To combine.

In order to manufacture the liquid crystal display according to the exemplary embodiment of the present invention, a first electrode is formed by forming a common electrode on a front surface of the upper substrate in which a seal line is defined at a periphery of the upper substrate. Form. Subsequently, a common voltage line is formed on a portion corresponding to the seal line on the lower substrate. Subsequently, a thin film transistor is formed on the lower substrate. Thereafter, an organic layer is coated on the entire surface of the lower substrate on which the common voltage line and the thin film transistor are formed. Subsequently, a portion of the organic layer is removed to form a first opening that exposes a portion of the common voltage line to form a second substrate. Thereafter, a sealant including a conductive material is formed in a portion of the upper substrate corresponding to the seal line. Subsequently, the first substrate and the second substrate are coupled using the sealant to electrically connect the common electrode and the common voltage line through the first opening. Finally, a liquid crystal layer is interposed between the first substrate and the second substrate.

Thus, the use of conductive sealants and openings can simplify the process, have a reduced size, and reduce delamination of the substrate.                     

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Example 1

1 is a plan view illustrating a liquid crystal display according to a first exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line AA ′ of FIG. 1.

1 to 2, the liquid crystal display includes a first substrate, a second substrate, a liquid crystal layer 108, and a sealant 122. The first substrate includes an upper substrate 100, a black matrix 102, a color filter 104, a common electrode 106, and a spacer 110. The second substrate includes a lower substrate 120 and a thin film transistor. 119, a gate line 118b ′, a data line 118a ', a storage capacitor line 118d, an inorganic insulating layer 116, an organic layer 114, and a pixel electrode 112. The liquid crystal layer 108 is interposed between the first substrate and the second substrate and sealed by a sealant 122.

The first substrate and the second substrate include a seal line 50 and a display region 70. The seal line 50 is disposed at the periphery of the first substrate or the second substrate and the sealant 122 is formed. The display area 70 is an area defined by the seal line 50, and the thin film transistor 119, the pixel electrode 112, and the like are formed to display an image.

The upper substrate 100 and the lower substrate 120 use glass of a transparent material that can pass light. The glass is alkali free. In the case where the glass has an alkali property, when alkali ions are eluted in the liquid crystal cell in the glass, the liquid crystal specific resistance is lowered to change the display characteristics, lower the adhesion between the seal and the glass, and adversely affect the operation of the thin film transistor 119. Gives.

The black matrix 102 is formed on the upper substrate 100 to block light. The black matrix 102 improves image quality by blocking light passing through an area in which the liquid crystal cannot be controlled. The black matrix 102 is formed by applying an opaque material and then removing a portion thereof.

The color filter 104 is formed on the upper substrate 100 on which the black matrix 102 is formed to selectively transmit only light having a predetermined wavelength. In the case of a liquid crystal display having a color filter on array substrate (COA) structure, the color filter may be formed on the second substrate.

The common electrode 106 is formed on the upper substrate 100 on which the black matrix 102 and the color filter 104 are formed. The common electrode 106 includes a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

The spacer 110 is formed on the common electrode 106 to maintain a cell gap between the first substrate and the second substrate.

The thin film transistor 119 is formed on the lower substrate and includes a source electrode 118a, a gate electrode 118b, and a drain electrode 118c. The thin film transistor 119 is formed on the lower substrate 120 through deposition, patterning, and etching processes.                     

The gate electrode 118b is separated from the source electrode 118a and the drain electrode 118c by the gate insulating layer 126. An amorphous silicon pattern is disposed on a portion of the gate insulating layer 126 corresponding to the gate electrode 118b, and two N + amorphous silicon patterns spaced apart from each other on the amorphous silicon pattern. Is placed. The source electrode 118a and the drain electrode 118c are disposed on the two spaced apart N + amorphous silicon patterns, respectively.

The gate line 118b 'is connected to the gate electrode 118b of the thin film transistor 119 to transmit a selection signal output from a driving circuit (not shown) to the thin film transistor 119, and the data line. 118a 'is connected to the source electrode 118a of the thin film transistor 119 to transfer the data voltage output from the driving circuit (not shown) to the thin film transistor 119. The drain electrode 118c is connected to the pixel electrode 112 through a contact hole.

The storage capacitor line 118d is formed on the lower substrate 120 to overlap a portion of the drain electrode 118c to form a storage capacitor. The storage capacitor maintains a potential difference between the common electrode 106 and the pixel electrode 112.

The inorganic insulating layer 116 insulates the thin film transistor 119 from the liquid crystal layer.

The organic layer 114 is formed on the inorganic insulating layer 116 to insulate the thin film transistor 119 from the liquid crystal layer or the pixel electrode 112. In addition, the distance between the pixel electrode 112 and the common electrode 106 is adjusted by the thickness of the organic layer 114 to form a liquid crystal layer disposed between the pixel electrode 112 and the common electrode 106. 108) is adjusted. The organic layer 114 also serves to flatten bending caused by the thin film transistor 119, the storage capacitor line 118d, or the like.

The organic layer 114 includes a contact hole exposing a part of the drain electrode 118c and a first opening 130 exposing a part of the common voltage line 118e. The position of the first opening 130 is formed at a portion of the seal line 50 corresponding to the common voltage line 118e. In addition, in order to reduce the influence of the resistance of the common electrode 106 itself, a plurality of first openings 130 may be formed. Preferably, the first opening 130 is disposed at each corner of the seal line 50.

The pixel electrode 112 is formed on a portion of the surface of the organic layer 114 and an inner surface of the contact hole and is connected to the drain electrode 118c of the thin film transistor 119 through the contact hole. The pixel electrode 112 controls the liquid crystal in the liquid crystal layer 108 by a voltage applied between the common electrode 106 and the light transmission.

In the case of the transflective liquid crystal display, a transmission window (not shown) for passing light incident from the bottom may be formed at a portion where the pixel electrode 112 is formed.

The common voltage line 118e provides a common voltage. The common voltage line 118e is electrically connected to the storage capacitor line 118d, and is electrically connected to the common voltage line 118e by a conductive sealant 122, which will be described later.

The sealant 122 is disposed in the sealline 50 and includes a conductive material. The conductive material includes a metal powder. Preferably, the metal includes gold, platinum, silver, copper and the like which are not easily oxidized. The sealant 122 electrically connects the common electrode 106 and the common voltage line 118e through the first opening 130.

The liquid crystal layer 108 is interposed between the first substrate 100 and the second substrate 120. The liquid crystal layer 108 is controlled by an electric field formed by the common electrode 106 and the pixel electrode 112 to adjust the transmission of light.

3A to 3K are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to a first embodiment of the present invention.

Referring to FIG. 3A, first, the seal line 50 and the display area 70 are defined on the upper substrate 100. The seal line 50 is disposed along the periphery of the upper substrate 100, and the display area 70 is an area defined by the seal line 50.

Referring to FIG. 3B, the black matrix 102 is formed on the upper substrate 100. The black matrix 102 is formed by applying an opaque material on the upper substrate and then removing a portion thereof.

Subsequently, the color filter 104 is formed on the upper substrate 100 on which the black matrix 102 is formed. In order to form the color filter, a material that passes only light having a specific wavelength is applied to the entire surface of the upper substrate 100 on which the black matrix 102 is formed, and then a part of the color filter is removed. In this case, the upper substrate 100 itself may be dyed without depositing a separate material to form the color filter.

Referring to FIG. 3C, the common electrode 106 is formed by applying ITO, IZO, or the like, which is a transparent conductive material, on the upper substrate 100 on which the black matrix 102 and the color filter 104 are formed.

Subsequently, the spacer 110 is formed on the common electrode 106 to maintain a cell gap between the first substrate and the second substrate. The spacer 110 is formed by applying, exposing and developing photoresist.

Accordingly, a first substrate including the upper substrate 100, the black matrix 102, the color filter 104, the common electrode 106, and the spacer 110 is formed.

Referring to FIG. 3D, the gate electrode 118b, the gate line 118b ′, the storage capacitor line 118d, and the common voltage line 118e are formed on the lower substrate 120. The gate electrode 118b, the gate line 118b ′, the storage capacitor line 118d, and the common voltage line 118e are formed by deposition of a conductive material, pattern formation, and etching.

Referring to FIG. 3E, a gate insulating layer 126 is formed on the lower substrate 120 on which the gate electrode 118b, the gate line 118b ′, the storage capacitor line 118d, and the common voltage line 118e are formed. ), An amorphous silicon layer and an N + amorphous silicon layer are sequentially applied and then patterned to form the amorphous silicon pattern and the N + amorphous silicon patterns.

Thereafter, a source electrode 118a and a drain electrode 118c are formed on the gate insulating layer 126. A portion of the drain electrode 118c overlaps the storage capacitor line 118d to form a storage capacitor. The source electrode 118a and the drain electrode 118c are formed using a deposition, pattern formation, and etching process of a conductive material.

Subsequently, an inorganic insulating layer 116 is coated on the entire surface of the lower substrate 120 on which the thin film transistor 119, the storage capacitor line 118d, and the common voltage line 118e are formed. Preferably, the inorganic insulating film 116 includes silicon nitride.

Referring to FIG. 3F, an organic layer 114 is then coated on the inorganic insulating layer 116. Preferably, the organic layer 114 includes a photoresist and decomposes when irradiated with light such as ultraviolet rays.

Referring to FIG. 3G, the organic layer 114 is exposed using a mask. The mask includes a transparent portion and an opaque portion. In this case, light is blocked to a portion of the organic layer 114 corresponding to the opaque portion of the mask, and light is irradiated to a portion of the organic layer 114 corresponding to the transparent portion of the mask. The polymer compound is present in the part where the light is blocked of the organic layer, but the polymer compound is decomposed in the part where the light is irradiated.

The transparent portion of the mask corresponds to a portion of the drain electrode 118c and a portion of the common voltage line 118e in the seal line 50. Preferably, the transparent portion is disposed at a portion of the drain electrode 118c and a corner portion of the seal line 50, respectively.

Subsequently, the exposed organic film 114 is developed. By the above phenomenon, the portion in which the polymer compound is present remains as it is, but the portion in which the polymer compound is decomposed is removed to correspond to a portion of the drain electrode 118c and a portion of the common voltage line 118e. A portion of the insulating film 116 is exposed.

Subsequently, a portion of the exposed inorganic insulating layer 116 is removed using a photolithography process to expose a contact hole exposing a portion of the drain electrode 118c and a portion of the common voltage line 118e. The opening 130 is formed.

Referring to FIG. 3H, a transparent conductive material such as ITO or IZO is subsequently applied onto the organic layer 114 on which the contact hole is formed. Subsequently, a part of the transparent conductive material is removed through a pattern forming and etching process to contact the drain electrode 118c on a part of the surface of the organic layer 114 and the inner surface of the contact hole. To form.

Accordingly, the lower substrate 120, the thin film transistor 119, the storage capacitor line 118d, the gate line 118b ′, the common voltage line 118e, the inorganic insulating layer 116, and the organic layer A second substrate including the 114 and the pixel electrode 112 is formed.

Referring to FIG. 3I, the sealant 122 is formed on a portion of the common electrode 106 corresponding to the seal line 50 of the first substrate. The sealant may be formed using a screen print method when the size of the liquid crystal display is small, and may be formed using a dispenser nozzle method when the size of the liquid crystal display is large. In this case, the sealant 122 may be formed on the second substrate instead of the first substrate, or may be formed by injection or the like in a state in which the first substrate and the second substrate are combined.

Referring to FIG. 3J, the first substrate and the second substrate are then coupled to each other. The sealant 122 is attached to the second substrate by applying heat to the sealant 122 of the combined first and second substrates or irradiating ultraviolet rays. A portion of the combined sealant 122 is electrically connected to the common voltage line 118e through the first opening 130.

By the coupling, the pixel electrode 112 of the second substrate is opposite to the color filter 104 of the first substrate. The cell gap between the first substrate and the second substrate is maintained by the spacer 110.

Referring to FIG. 3K, the liquid crystal layer 108 is interposed between the first substrate and the second substrate and then sealed. The liquid crystal layer 108 may be formed by a vacuum injection method or a dropping method. In the dropping method, the first substrate is joined to the second substrate after the dropping layer 108 is dropped.

Accordingly, a common voltage may be applied to the common electrode 106 by using the conductive sealant 122 and the first opening 130, and the common voltage line 118e may be applied to the common electrode 106. It can be formed in the seal line 50, the size of the liquid crystal display device is reduced.

Example 2

4 is a plan view illustrating a liquid crystal display according to a second exemplary embodiment of the present invention, and FIG. 5 is a cross-sectional view taken along line BB ′ in FIG. 4.

In the present exemplary embodiment, the remaining components except for the second openings 132a and 132b are the same as those of the first exemplary embodiment, and thus detailed descriptions thereof will be omitted.

When the first substrate and the second substrate are joined by a sealant, the adhesive force between the sealant and the organic layer of the second substrate is smaller than the adhesion between the sealant and the common electrode of the first substrate. . The sealant and the organic layer are easily peeled off due to the insufficient adhesive force, thereby causing a problem in that the liquid crystal is leaked.

Although the adhesive force between the sealant and the lower substrate of the second substrate is greater than that of the organic layer, the sealant alone is difficult to maintain the cell gap between the first substrate and the second substrate, Step) A problem occurs.

In a second preferred embodiment of the present invention, the second opening is formed in the organic layer so that a part of the sealant is in direct contact with the lower substrate to reduce peeling of the sealant.

In particular, since the peeling occurs mainly at the corners of the liquid crystal display, the second opening is preferably adjacent to the corner of the liquid crystal display.                     

4 to 5, the liquid crystal display includes a first substrate, a second substrate, a liquid crystal layer 108, and a sealant 122. The first substrate includes an upper substrate 100, a black matrix 102, a color filter 104, a common electrode 106, and a spacer 110. The second substrate includes a lower substrate 120 and a thin film transistor. 119, a gate line 118b ′, a data line 118a ', a storage capacitor line 118d, an inorganic insulating layer 116, an organic layer 114, and a pixel electrode 112. The liquid crystal layer 108 is interposed between the first substrate and the second substrate and sealed by a sealant 122. The first substrate and the second substrate include a seal line 50 and a display region 70.

The thin film transistor 119 includes a source electrode 118a, a gate electrode 118b, and a drain electrode 118c.

The organic layer 114 exposes a contact hole exposing a portion of the drain electrode 118c, a first opening 130 exposing a portion of the common voltage line 118e, and a portion of the lower substrate 120. Second openings 132a and 132b. Positions of the second openings 132a and 132b correspond to portions in which the gate line 118b ', the data line 118a', the common voltage line 118e, and the like do not exist in the seal line 50. Is formed. In addition, in order to increase the adhesion between the sealant 122 and the lower substrate 120, a plurality of second openings 132a and 132b may be formed. Preferably, the second openings 132a and 132b are disposed at two corner portions of the seal line 50, respectively.                     

The sealant 122 is disposed in the sealline 50 and includes a conductive material. The sealant 122 electrically connects the common electrode 106 and the common voltage line 118e through the first opening 130 and the lower substrate through the second openings 132a and 132b. Contact with 120.

6A to 6K are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to a second exemplary embodiment of the present invention.

6A through 6C, first, the seal line 50 and the display area 70 are defined on the upper substrate 100. Subsequently, the black matrix 102, the color filter 104, the common electrode 106, and the spacer 110 are formed on the upper substrate 100 to form a first substrate.

6D and 6E, the gate electrode 118b, the gate line 118b ′, the storage capacitor line 118d, the common voltage line 118e, and a gate insulating layer are formed on the lower substrate 120. 126, an amorphous silicon pattern, N + amorphous silicon patterns, the source electrode 118a, the drain electrode 118c, and the inorganic insulating layer 116 are formed.

6F and 6G, an organic film 114 is subsequently applied onto the inorganic insulating film 116, and the organic film 114 is exposed using a mask. The mask includes a transparent portion and an opaque portion.

The transparent portion of the mask is a portion of the drain electrode 118c, a portion of the common voltage line 118e in the seal line 50, the gate line 118b ′ in the seal line, and the data line 118a. Corresponds to a part of the portion where the common voltage line 118e does not exist. Preferably, the transparent portion is disposed at a portion of the drain electrode 118c and a corner portion of the seal line 50, respectively.

Subsequently, the exposed organic layer 114 is developed so that a part of the drain electrode 118c, a part of the common voltage line 118e, and a portion where the lines 118b ', 118a', and 118e do not exist. A portion of the inorganic insulating film 116 corresponding to a portion of the portion is exposed.

Subsequently, a portion of the exposed inorganic insulating layer 116 is removed using a photolithography process to expose a portion of the drain electrode 118c and a portion of the common voltage line 118e. Second openings 132a and 132b are formed to expose a portion of the opening 130 and portions where the lines 118b ', 118a' and 118e are not present.

Referring to FIG. 6H, a pixel electrode 112 is formed on the organic layer 114 on which the contact hole is formed, thereby forming the lower substrate 120, the thin film transistor 119, the storage capacitor line 118d, and the A second substrate including a gate line 118b ', the common voltage line 118e, the inorganic insulating layer 116, the organic layer 114, and the pixel electrode 112 is formed.

Referring to FIG. 6I, the sealant 122 is formed on a portion of the common electrode 106 corresponding to the seal line 50 of the first substrate.

Referring to FIG. 6J, the first substrate and the second substrate are then coupled to each other. A portion of the combined sealant 122 is electrically connected to the common voltage line 118e through the first opening 130, and the lower substrate 120 through the second openings 132a and 132b. Contact with

Referring to FIG. 6K, the liquid crystal layer 108 is interposed between the first substrate and the second substrate and then sealed.

Therefore, a part of the sealant 122 is directly contacted with the lower substrate 120 by using the second openings 132a and 132b to prevent peeling of the first substrate. In addition, a portion of the sealant 122 protrudes to increase the contact area between the sealant 122 and the organic layer 114.

According to the present invention as described above, the process can be simplified and reduced in size by using the conductive sealant and the opening, and the peeling of the substrate can be reduced.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the present invention as defined by the following claims It can be understood that

Claims (11)

A first substrate including an upper substrate, a common electrode formed on a front surface of the upper substrate, and a seal line disposed at a periphery of the upper substrate; A lower substrate, a thin film transistor formed on a surface of the lower substrate, a common voltage line formed at a portion corresponding to the seal line, to which a common voltage is applied, and a first opening exposing a portion of the common voltage line; A second substrate including a thin film transistor and an organic layer formed on an entire surface of a lower substrate on which the common voltage line is formed, and facing the first substrate; A liquid crystal layer interposed between the first substrate and the second substrate; And The sealant is formed on a portion corresponding to the seal line, and includes a conductive material to electrically connect the common electrode and the common voltage line through the first opening, and to seal the first substrate and the second substrate. Liquid crystal display comprising a. The liquid crystal display device of claim 1, wherein the conductive material comprises a metal powder. The liquid crystal display device of claim 2, wherein the metal comprises gold, platinum, silver, or copper. The liquid crystal display of claim 1, wherein the first opening is adjacent to a corner of the liquid crystal display. The liquid crystal display device of claim 1, wherein the organic layer includes a second opening exposing a portion of the lower substrate. The liquid crystal display of claim 5, wherein the second opening is adjacent to a corner of the liquid crystal display. The liquid crystal display of claim 5, wherein the second opening is provided in plural. Forming a first substrate including a common electrode disposed on a front surface of the upper substrate and a seal line disposed at a periphery of the upper substrate; Forming a common voltage line on a portion of the lower substrate corresponding to the seal line; Forming a thin film transistor on a lower substrate on which the common voltage line is formed; Coating an organic layer on an entire surface of the lower substrate on which the common voltage line and the thin film transistor are formed; Removing a portion of the organic layer to form a second substrate including a first opening exposing a portion of the common voltage line; Forming a sealant including a conductive material on a portion of the upper substrate corresponding to the seal line; Coupling the first substrate and the second substrate using the sealant to electrically connect the common electrode and the common voltage line through the first opening; And And interposing a liquid crystal layer between the first substrate and the second substrate. The method of claim 8, wherein the conductive material comprises a metal powder. The method of claim 9, wherein the metal comprises gold, platinum, silver, or copper. The method of claim 8, wherein the forming of the second substrate is performed. Removing a portion of the organic layer to form a second opening exposing a portion of the lower substrate.

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