KR100968448B1 - Phase-Change Memory Device and Fabrication Method Thereof - Google Patents

Phase-Change Memory Device and Fabrication Method Thereof Download PDF

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KR100968448B1
KR100968448B1 KR1020070138245A KR20070138245A KR100968448B1 KR 100968448 B1 KR100968448 B1 KR 100968448B1 KR 1020070138245 A KR1020070138245 A KR 1020070138245A KR 20070138245 A KR20070138245 A KR 20070138245A KR 100968448 B1 KR100968448 B1 KR 100968448B1
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South Korea
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layer
conductive layer
phase change
contact
method
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KR1020070138245A
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Korean (ko)
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KR20090070285A (en
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김문회
심규찬
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주식회사 하이닉스반도체
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Abstract

A phase change memory device and a method of manufacturing the same are provided for improving contact resistance between a lower electrode contact and an upper and lower contact material layers in a phase change memory device.
A method of manufacturing a phase change memory device according to the present invention comprises forming an interlayer insulating film on a semiconductor substrate on which a lower structure is formed, and forming a contact hole by patterning an interlayer insulating film of a region where a lower electrode contact is to be formed, and forming a first conductive layer in the contact hole. And sequentially forming the second conductive layer, planarizing the interlayer insulating film to expose the surface, and changing the surface of the first conductive layer to the insulating layer, thereby maintaining a wide contact area between the lower electrode contact and the switching element. In addition, the reset current may be reduced by minimizing the contact area between the lower electrode contact and the phase change material layer.
PRAM, BEC, Contact Area

Description

Phase Change Memory Device and Fabrication Method Thereof

The present invention relates to a phase change memory device, and more particularly, to a phase change memory device and a method of manufacturing the same for improving contact resistance between a lower electrode contact and an upper and lower contact material layers in a phase change memory device.

While DRAM has the advantage of low cost and random access, it has the disadvantage of volatile memory, and SRAM used as cache memory has the advantage of random access and speed, but it is not only volatile but also large in size There is a limit to this high. In addition, the flash memory is a nonvolatile memory, which is advantageous in cost, power consumption, etc., but has a disadvantage of slow operation speed.

A memory device developed to overcome the disadvantages of such memory devices may be a phase-change random access memory (PRAM) device. PRAM device A memory device that records and reads information by a phase change of a phase change material having a high resistance in an amorphous state and a low resistance in a crystalline state, and has an advantage of having a faster operation speed and a higher density than a flash memory. .

Phase change material is a material having a different state of crystalline state and amorphous state according to the temperature, in the crystalline state has a lower resistance than the amorphous state and has a regular orderly arrangement of atoms. Representative examples of the phase change material may include a chalcogenide (GST) -based material, which is a compound consisting of germanium (Ge), antimony (Sb), and tellurium (Te).

When the current is applied through the lower electrode in the PRAM device, the temperature of the phase change material layer is changed by Joule heat generated by this, and the crystal structure of the phase change material layer is determined by changing the applied current appropriately. Can be changed to a state. That is, Joule heat causes a phase change between a low resistance crystalline state (SET state) and a high resistance amorphous state (RESET state). In the write and read modes, the current flowing through the phase change film is sensed to determine whether the information stored in the phase change memory cell is data 0 in the set state or data 1 in the reset state.

Therefore, in the PRAM device, the structure of the bottom electrode contact that functions as a heater for heating the phase change material is very important, and the amount of current generated during the reset process during the set / reset process of the PRAM is related to the lifetime and sensing margin of the device. margin and the shrinkage of the device.

1 is a cross-sectional view of a general phase change memory device.

As shown in the figure, after forming the first interlayer insulating film 103 on the semiconductor substrate 101, patterning the first interlayer insulating film 103 in the region where switching elements are to be formed, and then switching element 105 such as a PN diode or the like. ). The second interlayer insulating layer 107 is formed on the entire structure, and a contact hole is formed. Then, a bottom electrode contact (BEC) 109 is formed by filling the contact hole with a conductive layer. Subsequently, the phase change material layer 111 is formed on the entire structure.

In the PRAM device, the BEC 109 may have a small contact resistance with the lower switching device 105 to obtain excellent electrical characteristics. On the other hand, the phase change material layer 111 on the top of the BEC 109 has to minimize the volume of the crystalline or amorphous to maximize the device operation, and therefore the contact resistance between the phase change material layer 111 and the BEC 109 is Higher to reduce reset current.

However, in the current PRAM device, since the BEC 109 serving as a heater of the phase change material layer 111 is formed in the shape of a column having the same upper and lower apertures, the electrical characteristics of the device deteriorate, such as an increase in the reset current. There is a problem.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and has a technical problem to provide a phase change memory device capable of independently controlling upper and lower apertures of a lower electrode contact and a method of manufacturing the same.

Another technical problem of the present invention is to lower the contact resistance between the lower electrode contact and the switching element in the phase change memory device, and to increase the contact resistance between the lower electrode contact and the phase change material layer, thereby improving operation characteristics of the device. A phase change memory device and a method of manufacturing the same are provided.

According to an aspect of the present invention, there is provided a method of fabricating a phase change memory device, by forming an interlayer insulating film on a semiconductor substrate on which a lower structure is formed, and patterning the interlayer insulating film in a region where a lower electrode contact is to be formed. Forming a contact hole; Sequentially forming a first conductive layer and a second conductive layer in the contact hole; Planarizing the exposed interlayer insulating film; And changing the surface of the first conductive layer to an insulating layer.

In addition, a phase change memory device according to an embodiment of the present invention includes a semiconductor substrate; A switching element formed on the semiconductor substrate; A lower electrode contact in contact with the switching element; And a phase change material layer in contact with the lower electrode contact, wherein the lower electrode contact includes an insulating layer formed on a portion of a contact surface of the phase change material layer.

According to the present invention, while maintaining the contact area between the lower electrode contact and the switching element wide, it is possible to minimize the contact area between the lower electrode contact and the phase change material layer to reduce the reset current.

Accordingly, there is an advantage that the device can be stably operated while realizing high integration by maximizing the operating current of the device while applying a low driving current.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

2A to 2F are cross-sectional views of devices for sequentially explaining a method of manufacturing a phase change memory device according to an exemplary embodiment of the present invention.

First, as shown in FIG. 2A, the first interlayer insulating film 203 is formed on the semiconductor substrate 201, and the first interlayer insulating film 203 of the region where switching elements are to be formed is patterned to form the semiconductor substrate 201. Expose Thereafter, a PN diode (not shown) is formed by a selective epitaxial growth (SEG) process to be used as the switching element 205.

Then, the second interlayer insulating film 207 is formed over the entire structure, and the second interlayer insulating film 207 of the region to be formed of BEC is patterned so that the upper surface of the switching element 205 is exposed.

Next, as shown in FIG. 2B, the first conductive layer 209 is formed over the entire structure, and the second conductive layer 211 is formed so as to be embedded in the contact hole as shown in FIG. 2C.

Here, the first conductive layer 209 may be formed using a conductive material that is changed into an insulating material by oxidation, and for example, a conductive material selected from the group containing titanium (Ti) and tantalum (Ta). It can form using. In addition, the second conductive layer 211 is formed of a metal nitride layer in consideration of the embedding property into the contact hole, and for example, using a conductive material selected from the group including titanium nitride (TiN) and tantalum nitride (TaN). Can be formed.

Next, as shown in FIG. 2D, the planarization process is performed to expose the upper surface of the second interlayer insulating layer 207 to remove the second conductive layer 211 and the first conductive layer 209.

In this state, since the BEC 213 is formed by filling the first and second conductive layers 209 and 211 in the contact hole, the BEC 213 and the lower switching element 205 and the subsequent process may be formed. Since the contact area with the phase change material layer is the same, the reset current cannot be optimized.

Therefore, in the present invention, in order to increase the interface resistance between the BEC 213 and the phase change material layer, a portion of the upper portion of the BEC 213 is changed to the insulating layer 215 as shown in FIG. 2E. To this end, the upper portion of the first conductive layer 209 is oxidized by an oxidation process after the planarization process of FIG. 2D. Next, as shown in FIG. 2F, a phase change material layer 217 is formed over the entire structure.

Here, the oxidation process may be any one of a thermal oxidation process and a plasma oxidation process, and the second conductive layer 211 made of a metal nitride layer is not oxidized while the first process made of titanium or tantalum is not oxidized by the oxidation process. The conductive layer 209 is oxidized to change to titanium dioxide (Ti0 2 ) or tantalum dioxide (TaO 2 ).

TiO 2 (TaO 2 ) is an insulating film, and the region acting as a heater for the phase change material layer 217 is limited to the second conductive layer 211, thus minimizing the volume of crystalline or amorphous phase change. have. In addition, the interface resistance between the BEC 213 and the phase change material layer 217 is increased and the reset current is reduced.

On the other hand, since oxidation occurs only on the upper surface of the first conductive layer 209 by the oxidation process, a sufficiently low contact resistance characteristic can be obtained between the switching element 205 and the BEC 213.

In a preferred embodiment of the present invention, before forming the phase change material layer 217 after the oxidation process, the surface of the oxidized insulating layer 215 may be removed by a predetermined height (for example, 5 to 10 μs). A sputtering process using argon (Ar) may be performed.

The phase change memory device described above is composed of a semiconductor substrate, a switching element formed on the semiconductor substrate, a lower electrode contact in contact with the switching element, and a phase change material layer in contact with the lower electrode contact, and the lower electrode contact is a phase change material. And an insulating layer formed on a portion of the contact surface with the layer.

Here, the insulating layer is formed around the upper surface of the lower electrode contact, the lower electrode contact, the first conductive layer extending from the bottom of the insulating layer to the bottom and in contact with the switching element, the first conductive layer and the inside of the insulating layer It further includes a second conductive layer embedded in the.

Those skilled in the art to which the present invention described above belongs will understand that the present invention can be implemented in other specific forms without changing the technical spirit or essential features. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

In the present invention, the contact area between the bottom electrode contact and the switching element and the contact area between the bottom electrode contact and the phase change material layer can be individually controlled, and in particular, the interface current with the phase change material layer is increased to reduce the reset current. You can.

Therefore, according to the present invention, the device can be operated with low current consumption without increasing the size of the phase change memory device, thereby manufacturing a phase change memory device that can be applied to portable devices such as mobile phones, PDAs, and mobile PCs. Can be.

1 is a cross-sectional view of a typical phase change memory device;

2A to 2F are cross-sectional views of devices for sequentially explaining a method of manufacturing a phase change memory device according to an exemplary embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

201: semiconductor substrate 203: first interlayer insulating film

205 switching element 207 second interlayer insulating film

209: first conductive layer 211: second conductive layer

213: BEC 215: insulating layer

217: phase change material layer

Claims (18)

  1. Forming an interlayer insulating film on a semiconductor substrate on which a lower structure is formed, and forming a contact hole by patterning the interlayer insulating film of a region to be formed with a lower electrode contact;
    Sequentially forming a first conductive layer and a second conductive layer in the contact hole;
    Planarizing the exposed interlayer insulating film; And
    Changing the surface of the first conductive layer to an insulating layer;
    Phase change memory device manufacturing method comprising a.
  2. The method of claim 1,
    And the first conductive layer is formed using a conductive material that is changed into an insulating material by oxidation.
  3. The method according to claim 1 or 2,
    The first conductive layer is formed using a conductive material selected from the group consisting of titanium (Ti) and tantalum (Ta).
  4. The method of claim 1,
    And the second conductive layer is formed of a metal nitride layer.
  5. The method according to claim 1 or 4,
    The second conductive layer is formed using a conductive material selected from the group consisting of titanium nitride (TiN) and tantalum nitride (TaN).
  6. The method of claim 1,
    And changing the surface of the first conductive layer into an insulating layer comprises oxidizing an upper portion of the first conductive layer.
  7. The method of claim 6,
    The oxidizing of the upper portion of the first conductive layer is a step of performing a thermal oxidation process or a plasma oxidation process.
  8. The method of claim 1,
    And forming a phase change material layer over the entire structure after the step of changing the surface of the first conductive layer into an insulating layer.
  9. The method of claim 8,
    And removing the insulating layer by a predetermined height before forming the phase change material layer.
  10. The method of claim 9,
    And removing the insulating layer by a height specified by a sputtering process using argon (Ar).
  11. 11. The method according to claim 9 or 10,
    The insulating layer is removed to a thickness of 5 ~ 10Å, the method of manufacturing a phase change memory device.
  12. Semiconductor substrates;
    A switching element formed on the semiconductor substrate;
    A lower electrode contact in contact with the switching element; And
    A phase change material layer in contact with the lower electrode contact;
    The lower electrode contact may include an insulating layer formed on a portion of a contact surface of the phase change material layer; And
    And a first conductive layer formed of a conductive material extending from a lower portion of the insulating layer to a lower portion of the insulating layer and in contact with the switching element, and converted into an insulating material by oxidation.
  13. 13. The method of claim 12,
    The insulating layer is formed around an upper surface of the lower electrode contact;
    The lower electrode contact further comprises a first conductive layer and a second conductive layer embedded in the insulating layer.
  14. delete
  15. The method of claim 13,
    The first conductive layer is a phase change memory device, characterized in that made of a conductive material selected from the group consisting of titanium (Ti) and tantalum (Ta).
  16. The method of claim 13,
    And the second conductive layer is made of a metal nitride layer.
  17. The method according to claim 13 or 16,
    The second conductive layer is a phase change memory device, characterized in that made of a conductive material selected from the group consisting of titanium nitride (TiN) and tantalum nitride (TaN).
  18. The method of claim 13,
    The insulating layer is a phase change memory device, characterized in that the oxide layer on the surface of the first conductive layer.
KR1020070138245A 2007-12-27 2007-12-27 Phase-Change Memory Device and Fabrication Method Thereof KR100968448B1 (en)

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Publication number Priority date Publication date Assignee Title
KR101119222B1 (en) * 2010-01-18 2012-03-20 주식회사 하이닉스반도체 a Method of manufacturing Phase Change RAM having controllable contact area of bottom electrode contact

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006156886A (en) 2004-12-01 2006-06-15 Renesas Technology Corp Semiconductor integrated circuit device and manufacturing method therefor
KR20060105555A (en) * 2005-03-31 2006-10-11 인피니언 테크놀로지스 아게 Connection electrode for phase change material, associated phase change memory element, and associated production process
KR20060133394A (en) * 2005-06-20 2006-12-26 삼성전자주식회사 Phase change memory cells having a cell diode and a bottom electrode self-aligned with each other and methods of fabricating the same
KR20070094194A (en) * 2006-03-16 2007-09-20 주식회사 하이닉스반도체 Method of fabricating phase-change random access memory(pram) device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006156886A (en) 2004-12-01 2006-06-15 Renesas Technology Corp Semiconductor integrated circuit device and manufacturing method therefor
KR20060105555A (en) * 2005-03-31 2006-10-11 인피니언 테크놀로지스 아게 Connection electrode for phase change material, associated phase change memory element, and associated production process
KR20060133394A (en) * 2005-06-20 2006-12-26 삼성전자주식회사 Phase change memory cells having a cell diode and a bottom electrode self-aligned with each other and methods of fabricating the same
KR20070094194A (en) * 2006-03-16 2007-09-20 주식회사 하이닉스반도체 Method of fabricating phase-change random access memory(pram) device

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