KR100953302B1 - Analog Buffer Circuit of having Cascode Structure and Method of operating the same - Google Patents

Abstract

An analog buffer circuit is disclosed that can form a negative feedback path using two cascode connected transistors to accurately and quickly follow an input signal. The analog buffer circuit includes two sampling units to store input signals. The stored input signal determines the operating level of the cascode connected transistors. Also, the analog buffer circuit divides the operation section into a sampling mode, an amplification mode, and a compensation mode to perform a buffer operation by a switching operation. This allows the analog buffer circuit to follow the input signal quickly and accurately.

Analog buffer. Cascode, LTPS

Description

Analog Buffer Circuit of having Cascode Structure and Method of operating the same}

The present invention relates to a flat panel display driving circuit, and more particularly, to a flat panel display driving circuit formed on the same transparent insulating substrate as the display unit.

Recently, in the field of flat panel display devices such as liquid crystal displays, plasma display panels, and field emission displays, a method of integrally forming a driving circuit for driving the display unit on the same insulating substrate as the display unit for thinning the display panel has been introduced. .

Particularly, in a liquid crystal display or a field emission display, a thin film transistor (TFT) is used as a pixel transistor constituting the display unit. Therefore, when a driving circuit is formed on a transparent insulating substrate, a conductive circuit diagram is used using a thin film transistor. There is an advantage to this.

Low Temperature Polycrystalline Silicon (LTPS) technology has the advantage of high current driving capability and easy integration with peripheral circuits, resulting in low cost implementation. Thus, there is a possibility of integrating driving circuits of a TFT-based display having a circuit array. However, LTPS TFTs have poor electrical characteristics compared to single crystal silicon based transistors, including high threshold voltages and uneven electrical characteristics.

Recently, the market associated with portable devices is growing rapidly. Moreover, the devices want portable devices that display compact, high resolution, and high quality images. In order to realize such a high quality display, increasing the resolution of the display reduces the charging time of the load and increases the output load. Therefore, the capability of the analog buffer circuit must be better to charge the output load in a very short time. However, the conventional analog buffer circuit using the LTPS TFT has many problems, such as a large offset voltage and an increased power consumption, due to the poor electrical characteristics of the LTPS.

To solve these problems, many kinds of analog buffer circuits such as differential analog buffer circuit, comparator analog buffer circuit, and source follower analog buffer circuit have been developed. However, these conventional analog buffer circuits are not suitable for high resolution displays for the following reasons.

That is, the conventional differential analog buffer circuit has a problem of input stage mismatching due to the nonuniform electrical characteristics of the polysilicon TFT, and the conventional comparator analog buffer circuit has a static current during the operation of the comparator. There is a problem that consumes a large amount of power. A commonly used source follower type analog buffer circuit has a problem in that operating characteristics are slow because the voltage difference between the gate electrode and the source electrode decreases as the output voltage increases.

An example of a conventional source follower type analog buffer circuit adopted in the above driving circuit integrated flat panel display device is shown in FIG. 1.

1 is a circuit diagram illustrating a source follower type analog buffer circuit according to the prior art.

Referring to FIG. 1, in an analog buffer circuit, first and second transistors M1 and M2 are connected in series between a positive first power supply VDD and a negative second power supply VSS. Configure the source follower. The first switch sw1 is connected between the gate electrode and the input terminal of the first transistor M1. In addition, a third switch sw3 and a second switch sw2 are connected in series between the source electrode and the input terminal of the first transistor M1, and are connected to the fifth switch sw5 connected in series. The fourth switch sw4 is connected in parallel with the third switch sw3 and the second switch sw2.

The first capacitor C1 is connected between the gate electrode and the source electrode of the first transistor M1 via a third switch sw3, and the second capacitor C2 is connected via a fifth switch sw5. Is connected.

In addition, a sixth switch sw6 and a load resistor RL are connected between the source electrode of the first transistor M1 (that is, the drain electrode of the second transistor M2) and the output terminal. The second power supply VSS having a negative constant voltage is applied between the sixth switch sw6 and the load resistor RL with the seventh switch sw7 interposed therebetween.

The load capacitor CL is connected between the output terminal and the ground.

Here, the constant voltage applied to the lower end of the seventh switch sw7 is used as a discharge potential of the output load CL.

The second transistor M2 is supplied with a constant voltage Vbias to its gate electrode, and acts as a current source flowing toward the second power source VSS.

FIG. 2 is a timing diagram for describing an operation of the analog buffer circuit of FIG. 1.

Referring to FIG. 2, first, first, third, fifth, and seventh switches sw1, sw3, sw5, sw7 are in a conductive state in a T1 section, and second, fourth, and sixth switches sw2, sw4, sw6) is in a non-conducting state. Accordingly, the potential of the output load CL is set to VSS. In other words, the output load CL is charged to VSS. In addition, when an input voltage is input from the input terminal to the gate electrode of the first transistor M1, the voltage difference Vgs1 between the gate electrode and the source electrode of the first transistor M1 is changed to the first and second capacitors C1,. C2) is charged.

Thereafter, in the T2 section, the first and fifth switches sw1 and sw5 are turned off, the fourth switch sw4 is turned on, and the third and seventh switches sw3 and sw7 are turned on. In addition, the second and sixth switches sw2 and sw6 maintain a non-conduction state. At this time, as the input voltage Vin is applied to the electrode opposite to the second capacitor C2, the gate voltage of the first transistor M1 changes according to the voltage stored in the second capacitor C2. Therefore, the voltage difference Vgs2 between the gate electrode and the source electrode of the first transistor M1 at this time is charged in the first capacitor C1. At this time, the gate voltage Vg applied to the gate electrode of the first transistor M1 becomes the input voltage Vin + Vgs1 (that is, Vg = Vin + Vgs1).

The voltage Vs of the source electrode of the first transistor M1 is a voltage obtained by subtracting the voltage difference Vgs2 of the gate electrode-source electrode from the gate voltage Vg. (I.e., Vs = Vin + Vgs1-). Vgs2)

Subsequently, in the T3 section, the first, fifth, and sixth switches sw1, sw5, sw6 maintain a non-conduction state, the seventh switch sw7 maintains a conduction state, and the second switch sw2 conducts a state. And the third and fourth switches sw3 and sw4 are in a non-conductive state. At this time, as the input voltage Vin is applied to the electrode opposite to the first capacitor C1, the gate voltage of the first transistor M1 changes according to the voltage stored in the first capacitor C1.

At this time, the gate voltage Vg applied to the gate electrode of the first transistor M1 becomes a voltage obtained by adding the charging voltage Vgs2 of the first capacitor C1 to the input voltage Vin. Vin + Vgs2 Also, when the voltage difference between the gate electrode and the source electrode of the first transistor M1 is Vgs3, the voltage Vs of the source electrode of the first transistor M1 is equal to the gate voltage Vg. The voltage difference Vgs3 of the source electrode is subtracted (that is, Vs = Vin + Vgs2-Vgs3). If (-Vgs2 + Vgs3) = Verr is set, Vs = Vin + Verr.

Thereafter, in the T4 section, the seventh switch sw7 is in a non-conductive state, the sixth switch sw6 is in a conductive state, the second switch sw2 is in a conductive state, and the first to fifth switches (sw1 ~ sw5) will maintain a non-conduction state. At this time, since the input signal Vin is still applied from one input terminal to one terminal of the first capacitor C1, the gate voltage of the first transistor M1 changes according to the charging voltage of the first capacitor C1. . On the other hand, as the sixth switch sw6 is conducted, the load discharged in the previous section is continuously charged through the sixth switch sw6 and the source electrode-drain electrode of the second transistor M2.

At this time, the gate voltage of the first transistor M1 becomes a voltage obtained by adding the charging voltage Vgs2 of the first capacitor C1 to the input voltage Vin. (Ie, Vg = Vin + Vgs2). The voltage Vs of the source electrode of the first transistor M1 becomes a voltage obtained by subtracting the gate electrode-source voltage Vgs3 from the gate voltage Vg (that is, Vs = Vin + Vgs2-Vgs3) where Vgs2 and Vgs3. When these values are about the same, Vs is very close to Vin.

In the conventional analog buffer circuit described above, the voltage difference between the gate electrode and the source electrode of the driving transistor gradually decreases as the output voltage approaches the input voltage by using the source follower structure. It will fall significantly. Therefore, the stabilization time with respect to the output time of the analog buffer circuit will be long.

A first object of the present invention for solving the above problems is to provide an analog buffer circuit having a cascode amplifying structure and capable of quickly and accurately following an input signal through negative feedback.

A second object of the present invention is to provide a method of operating an analog buffer circuit provided by achieving the first object.

The present invention for achieving the first object, the input sampling unit for sampling and storing the input signal; A cascode amplifier for using the input signal stored in the input sampling unit in a negative feedback operation; And a constant current source connected to the cascode amplifier and generating a driving current.

According to another aspect of the present invention, an input sampling unit for sampling and storing an input signal, a cascode amplifier unit, and the cascode amplifier unit for using an input signal stored in the input sampling unit in a negative feedback operation are provided. An operating method of an analog buffer circuit comprising a constant current source connected to a source for generating a drive current, the method comprising: operating in a sampling mode for sampling and storing an input signal using the input sampling unit; And operating in an amplifying mode such that an output signal of the cascode amplifier part follows the input signal by using the input signal stored in the first sampling part of the input sampling part through switching. to provide.

According to the present invention described above, a negative feedback path is formed in the cascode amplifying structure. Therefore, the analog buffer can realize a high gain and can reduce power consumption by shortening the stabilization time of the output signal. In addition, as the stabilization time of the output signal as the load driving signal is shortened, it is easy to ensure sufficient line time for demultiplexing.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. Like reference numerals are used for like elements in describing each drawing.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

Example

3 is a circuit diagram illustrating an analog buffer circuit according to a preferred embodiment of the present invention.

Referring to FIG. 3, the analog buffer circuit includes an input sampling unit 100, a cascode amplifier 200, a constant current source 300, and an output load unit 400.

The input sampling unit 100 samples the input signal Vin and uses the sampled input signal in the negative feedback operation of the cascode amplifier. The input sampling unit 100 has a first sampling unit 110 and a second sampling unit 130.

The first sampling unit 110 includes a first switch SW1, a first capacitor C1, and a second switch SW2. The first switch SW1 is connected between the input terminal and the first node N1, and the first capacitor C1 is connected between the first node N1 and the cascode amplifier 200. In addition, the second switch SW2 is connected between the first node N1 and the constant current source 300.

When the second sampling unit 130 is configured in parallel with the first sampling unit 110, the second sampling unit 130 includes a third switch SW3, a second capacitor C2, and a fourth switch SW4. The third switch SW3 is connected between the input terminal and the second node N2, and the second capacitor C2 is connected between the second node N2 and the cascode amplifier 200. In addition, the fourth switch SW4 is connected between the first node N1 and the constant current source 300.

The cascode amplifier 200 is connected between the positive power supply voltage VDD and the constant current source 300, performs a negative feedback operation, and performs an amplification operation according to a change of the sampled input signal Vin.

The cascode amplifier 200 includes a first transistor M1, a second transistor M2, a third capacitor, a fifth switch SW5, a sixth switch SW6, and a seventh switch SW7.

The first transistor M1 is connected to the second transistor M2 via the positive power supply voltage VDD and the sixth node N6, and the gate of the first transistor M1 is connected to the first capacitor C1 and the second capacitor C2 via the third node N3. It is connected to one end of. The above-described configuration has a common source configuration in which the voltage of the third node N3 is input. Therefore, there is an advantage that a large small signal gain can be secured.

In addition, the fifth switch SW5 is connected between the third node N3 and the sixth node N6. That is, it is connected between the drain and the source of the first transistor M1. If the fifth switch SW5 is turned on, the first transistor M1 is diode connected.

The second transistor M2 is connected between the sixth node N6 and the fifth node N5, and the gate is connected to the fourth node N4. The second transistor M2 has a common gate structure which receives the voltage of the sixth node N6 as a source. Accordingly, the first transistor M1 and the second transistor M2 connected in series have a cascode structure. The cascode structure has an advantage of ensuring stable gain characteristics at high gain and high frequency. Subsequently, a sixth switch SW6 is connected between the drain and the gate of the second transistor. When the sixth switch SW6 is turned on, the second transistor M2 is diode connected.

In addition, the third capacitor C3 is connected between the positive power supply voltage VDD and the fourth node N4. The voltage stored at one end of the third capacitor C3 is supplied to the gate of the second transistor M2 to control the operation of the second transistor M2.

The seventh switch SW7 is connected between the fifth node N5 and the output load unit 400. By turning on the seventh switch SW7, the output signal of the cascode amplifier 200 is transmitted to the output rod 400.

The constant current source 300 is composed of the third transistor M3. The constant current source 300 is connected between the fifth node N5 and the negative power supply voltage VSS. A constant voltage Vbias is applied to the gate terminal of the third transistor M3. The third transistor M3 generates a constant current by the applied constant voltage Vbias. However, in order to operate as the constant current source, the third transistor M3 must operate in the active region.

The output load unit 400 includes a load resistor R _L and a load capacitor C _L. However, since the above-described configuration of the output rod 400 is merely an equivalent circuit representing the output load of the circuit, the output rod 400 may have various configurations in the present invention.

4 is a timing diagram illustrating the operation of the analog buffer circuit shown in FIG. 3 according to a preferred embodiment of the present invention.

Referring to FIG. 4, the analog buffer circuit operates in three stages. That is, the first section T1 indicates a state of operating in the sampling mode, the second section T2 indicates a state of operating in the amplification mode, and the third section T3 indicates a state of operating in the compensation mode. In addition, in FIG. 4, the portion marked as high level in timing indicates the state in which the corresponding switch is turned on, and the portion indicated as low level indicates the state in which the corresponding switch is turned off.

The following describes the operation of the analog buffer circuit in each section.

FIG. 5 is an equivalent circuit diagram illustrating an analog buffer circuit in the first section of FIG. 4.

4 and 5, in the first section T1, the first switch SW1, the third switch SW3, the fifth switch SW6, and the sixth switch SW6 are turned on, and the remaining switches are turned off.

The input signal Vin is transmitted to the first node N1 and the second node N2. In addition, the first transistor M1 and the second transistor M2 are each diode connected. Therefore, the third node N3 and the sixth node N6 are set to the same voltage, and the set voltage is VDD-Vsg1 (Vsg1 is the source-gate voltage difference of the first transistor M1). The fourth node N4 and the fifth node N5 are also electrically shorted to each other, and the voltages of the fourth node N4 and the fifth node N5 are VDD-Vsg1-Vsg2 (where Vsg2 is the source-gate voltage of the second transistor M2). Car).

As a result, the voltage differences Vc1 and Vc2 stored in the first capacitor C1 and the second capacitor C2 in the first period T1 become VDD-Vsg1-Vin. That is, the input signal Vin is sampled and stored through the capacitors C1 and C2. In addition, the voltage difference Vc3 stored at both ends of the third capacitor C3 becomes Vsg1 + Vsg2. The third capacitor C3 stores the voltage difference between the source and gate of the two transistors M1 and M2.

The source-gate voltage differences Vsg1 and Vsg2 of the two transistors M1 and M2 have a characteristic depending on the level of the constant voltage Vbias applied to the gate terminal of the third transistor M3 which is a constant current source. That is, Vsg1 and Vsg2 are determined according to Vbias, which determines the current between the drain and the source of the third transistor M3 operating in the active region. If Vbias has a high value, the driving current Idr increases, and thus Vsg1 and Vsg2 increase.

In summary, the input signal Vin is sampled and stored in two capacitors C1 and C2 in the period T1 which is the sampling period. In addition, the source-gate voltage difference Vsg1 and Vsg2 of the two transistors M1 and M2 corresponding to the driving current Idr are also stored in the third capacitor C3.

FIG. 6 is an equivalent circuit diagram illustrating an analog buffer circuit in the second section of FIG. 4.

4 and 6, in the second period T2, the analog buffer circuit operates in an amplification mode. To this end, the second switch SW2, the third switch SW3 and the seventh switch SW7 are turned on, and the remaining switches are turned off.

First, the voltage of the fifth node N5 was VDD-Vsg1-Vsg2 in the first period T1 which is the sampling mode. However, part of the driving current Idr flowing through the fifth node N5 flows to the output load part due to the turning on of the seventh switch SW7, and the voltage of the fifth node N5 suddenly drops. In addition, the voltage of the third node N3 is also lowered by the coupling due to the voltage difference stored in the capacitor C1. The voltage drop at the third node N3 increases the voltage difference between the source and the gate of the first transistor M1. Therefore, the current flowing through the source-drain of the first transistor M1 increases, and the voltage of the sixth node N6 also increases. This forms a sufficient current to charge the output load portion in addition to the drive current Idr. As a result, the voltage at the output stage increases rapidly.

If the voltage of the fifth node N5 is V5, V5 continuously rises. However, it should be considered that the first capacitor C1 stores the voltage difference of VDD-Vsg1-Vin in the sampling mode. That is, the voltage of the third node N3 considering V5 is VDD-Vsg1-Vin + V5. In addition, the voltage difference between the source and the gate of the first transistor M1 becomes Vin + Vsg1-V5. If V5 exceeds Vin, the first transistor is not turned on or is not operated in the active region. Thus, V5 rises up to Vin.

When the voltage of the third node N3 rises, the current generated by the operation in the active region of the first transistor M1 gradually decreases. This indicates that the voltage at the sixth node N6 gradually decreases. Therefore, the amount of current charged to the output rod portion is gradually reduced. This means that as time passes, the increase amount of the output signal Vout of the output load portion decreases.

In the operation of the amplification mode described above, the cascode amplifier unit constitutes an input sampling unit and a negative feedback circuit, charges the output load unit, and raises the voltage of the output load unit until it approaches Vin.

FIG. 7 is an equivalent circuit diagram illustrating an analog buffer circuit in the third section of FIG. 4.

4 and 7, the analog buffer circuit operates in the compensation mode in the third section T3. That is, in FIG. 6, only the first capacitor C1 is interposed on the negative feedback path, whereas in FIG. 7, the second capacitor C2 is added on the negative feedback path. Therefore, the first capacitor C1 and the second capacitor C2 are disposed on the negative feedback path of the cascode amplifier part. In FIG. 5, the voltage difference stored in the two capacitors C1 and C2 is VDD-Vsg1-Vin. Thus, a coupling operation occurs in two capacitors with respect to the change amount of the voltage V5 of the fifth node N5. This is stronger than the coupling operation that occurs in one first capacitor C1.

That is, even if the voltage drop of the third node N3 is generated by the coupling operation due to the generation of the leakage current at the gate stage for the manufacturing process, the error range is minimized by the effect of the additional second capacitor C2. Therefore, the fifth node N5 can perform a more accurate and quick charging operation on the output load portion, and the output signal Vout can rise to the Vin level quickly and accurately.

In addition, in the present invention, the operation in the compensation mode may be added as necessary. That is, the analog buffer circuit can be used only in the sampling mode and the amplification mode, and the compensation mode can be additionally used to obtain a faster and more accurate output signal. Therefore, the second sampling unit of the input sampling unit may be selectively employed.

8 is a timing diagram illustrating characteristics of a third node and an output signal in an amplification mode according to a preferred embodiment of the present invention.

Referring to FIG. 8, as the amplification mode is entered, the voltage of the third node N3 decreases momentarily and continuously increases. The output signal Vout has a characteristic of following the input signal Vin. The operation of the analog buffer circuit in this amplification mode is the same as described in FIG.

In addition, the analog buffer circuit of FIG. 3 and the conventional analog buffer circuit disclosed in FIG. 1 were simulated using the LTPS process under the conditions shown in Table 1 below.

Table 1 Simulation Conditions

VDD, VSS 8.5 V, -0.5 V Input voltage range 3 V to 5 V Line time 16 μsec Panel size 2.2 inch resolution qVGA (240 × RGB × 320) Load condition C: 12pF, R: 900Ω

FIG. 9 shows the TT state (steady state) and FF state (in the case of the input signals Vin of 2.5V, 3.5V, 4.0V, 4.5V, 5.0V and 5.5V, respectively) in the conventional analog buffer circuit shown in FIG. The figure shows the output voltage characteristics for the state of lower threshold and higher mobility than TT) and SS state (higher threshold and lower mobility than TT). In the figure, Verr is the offset voltage (ie mischarging voltage) in the TT state.

FIG. 10 is a diagram illustrating an offset output voltage characteristic according to an input voltage of the conventional analog buffer circuit shown in FIG. 1.

Referring to FIG. 10, it can be seen that the maximum offset Verr of the output voltage in the conventional analog buffer circuit is 37 mV at a line time of 16 μsec in the SS state.

11 is an analog buffer circuit according to the present invention, when the input voltage (Vin) is 2,5V, 3.0V, 3.5V, 4.0V, 4.5V, 5.0V and 5.5V, respectively, TT state, FF state, SS A diagram showing output voltage characteristics for a state.

Referring to FIG. 11, Verr is an offset voltage in the TT state. Also, in the same drawing, it can be seen that the characteristics of the output voltages for the TT state, the FF state, and the SS state are extremely similar to each other at the same input voltage Vin.

12 is an offset output voltage characteristic versus an input voltage of an analog buffer circuit according to the present invention.

Referring to FIG. 12, it can be seen that the maximum offset (Verr) of the output voltage in the analog buffer circuit according to the present invention is 8 mV at a line time of 16 μsec in the SS state. Here, 16 μsec is a time for 1 to 3 demultiplexing.

As described above, it can be seen that the analog buffer circuit according to the present invention is much closer to the target voltage than the conventional analog buffer circuit within one to three demultiplexing times.

Here, when the output voltage reaches 90% of the target voltage as the stabilization time, it can be seen how quickly the analog buffer circuit charges the output load. As a result of the simulation, it was stabilized at 10 mu sec in the analog buffer circuit according to the present invention and 20 mu sec in the conventional analog buffer circuit shown in FIG. Thus, it can be seen that the analog buffer circuit according to the present invention has a very high and fast charging capacity of the output load.

Finally, the power consumption of the analog buffer circuit according to the present invention is 43.1 µW, which is 73% of the conventional analog buffer circuit shown in FIG.

13 is a view showing the current drive capability characteristics of the conventional analog buffer circuit shown in Figure 1, Figure 14 is a view showing the current drive capability characteristics of the analog buffer circuit according to the present invention.

Referring to FIG. 13, since the conventional analog buffer circuit has a lower load charging capability compared to the analog buffer circuit according to the present invention, the peak current and the quiescent current are 158 μA, 11.99 μA, respectively in the FF state. 127μA, 8.80μA in TT and 103μA and 6.10μA in SS, respectively, require large amounts of operating current. Therefore, the conventional analog buffer circuit consumes a large amount of power.

On the other hand, referring to Figure 14, the analog buffer circuit according to the present invention has a peak current (quiescent current) and quiescent current (31μA, 2.98μA in the FF state, respectively 28μA, 2.18μA, and SS in the TT state, respectively) In the state, it can be seen that it consumes a smaller amount of current than 26 μA and 1.51 μA, respectively.

As described above, since the analog buffer circuit according to the present invention is a cascode type having a sampling mode and a negative feedback mode, the driving speed is much faster than that of the conventional analog buffer circuit. In addition, the analog buffer circuit according to the present invention has very high precision due to the high negative feedback gain. Simulation results show that the maximum offset of the output voltage in the analog buffer circuit according to the present invention is 8mV and the maximum offset of the output voltage in the conventional analog buffer circuit is 37mV. In addition, the power consumption of the analog buffer circuit according to the present invention is 43.1μW, it was confirmed that only 73% of the power consumption of the conventional analog buffer circuit.

1 is a circuit diagram illustrating a source follower type analog buffer circuit according to the prior art.

FIG. 2 is a timing diagram for describing an operation of the analog buffer circuit of FIG. 1.

3 is a circuit diagram illustrating an analog buffer circuit according to a preferred embodiment of the present invention.

4 is a timing diagram illustrating the operation of the analog buffer circuit shown in FIG. 3 according to a preferred embodiment of the present invention.

FIG. 5 is an equivalent circuit diagram illustrating an analog buffer circuit in the first section of FIG. 4.

FIG. 6 is an equivalent circuit diagram illustrating an analog buffer circuit in the second section of FIG. 4.

FIG. 7 is an equivalent circuit diagram illustrating an analog buffer circuit in the third section of FIG. 4.

8 is a timing diagram illustrating characteristics of a third node and an output signal in an amplification mode according to a preferred embodiment of the present invention.

FIG. 9 shows the TT state (steady state) and FF state (in the case of the input signals Vin of 2.5V, 3.5V, 4.0V, 4.5V, 5.0V and 5.5V, respectively) in the conventional analog buffer circuit shown in FIG. The figure shows the output voltage characteristics for the state of lower threshold and higher mobility than TT) and SS state (higher threshold and lower mobility than TT).

FIG. 10 is a diagram illustrating an offset output voltage characteristic according to an input voltage of the conventional analog buffer circuit shown in FIG. 1.

11 is an analog buffer circuit according to the present invention, when the input voltage (Vin) is 2,5V, 3.0V, 3.5V, 4.0V, 4.5V, 5.0V and 5.5V, respectively, TT state, FF state, SS A diagram showing output voltage characteristics for a state.

12 is an offset output voltage characteristic versus an input voltage of an analog buffer circuit according to the present invention.

FIG. 13 is a diagram showing the current driving capability characteristics of the conventional analog buffer circuit shown in FIG.

14 is a view showing the current driving capability characteristics of the analog buffer circuit according to the present invention.

Claims (7)

An input sampling unit for sampling and storing the input signal; A cascode amplifier for using the input signal stored in the input sampling unit in a negative feedback operation; And And a constant current source connected to the cascode amplifier to generate a driving current. The display apparatus of claim 1, wherein the input sampling unit comprises a first sampling unit configured to store the input signal and form a negative feedback path of the cascode amplifier. The first sampling unit, A first switch connected between the input terminal and the first node; A first capacitor connected between the first node and the cascode amplifier; And And a second switch connected between the first node and the constant current source. The method of claim 2, wherein the input sampling unit further comprises a second sampling unit connected in parallel with the first sampling unit, The second sampling unit, A third switch connected between the input terminal and a second node; A second capacitor connected between the second node and the cascode amplifier; And And a fourth switch connected between the second node and the constant current source. The cascode amplifier of claim 2, A first transistor coupled between a positive power supply voltage and a sixth node, the first transistor receiving a voltage stored in the first capacitor; A fifth switch for diode-connecting the first transistor by an on operation; A second transistor connected between the sixth node and a fifth node; A sixth switch for diode-connecting the second transistor by an on operation; A third capacitor connected to the gate terminal of the second transistor; And And a seventh switch connected to the fifth node. The analog buffer circuit of claim 4, wherein the analog buffer circuit further comprises an output load unit connected to the seventh switch to form an output signal. An input sampling unit for sampling and storing an input signal, a cascode amplifier for using the input signal stored in the input sampling unit for the negative feedback operation, and a constant current source for generating a driving current connected to the cascode amplifier unit; In the method of operating an analog buffer circuit comprising: Operating in a sampling mode for sampling and storing an input signal using the input sampling unit; And And operating in an amplifying mode such that an output signal of the cascode amplifier part follows the input signal by using the input signal stored in the first sampling part of the input sampling part through switching. The method of claim 6, wherein after the amplifying mode, the cascode amplifying unit operates in a compensation mode such that the output signal accurately follows the input signal through a switching operation of the second sampling unit configured in parallel with the first sampling unit. Operation method of an analog buffer circuit, characterized in that it further comprises.

Images