KR100949274B1 - Semiconductor device - Google Patents

Abstract

The present invention relates to a delay lock loop of a semiconductor device that occupies a relatively small area and consumes a relatively small amount of current even when a function including a duty ratio correction function is included. And a delay lock means for delaying the internal clock corresponding to the clock edge of the source clock and outputting the delay lock loop clock as a time corresponding to the comparison result, and receiving the delay lock loop clock. Splitting means for splitting and outputting the first clock corresponding to the first edge and the second clock corresponding to the second edge, a first voltage corresponding to the duty ratio of the first clock, and the second clock Voltage generation means for generating a second voltage corresponding to a duty ratio, and for comparing the levels of the first voltage and the second voltage; A clock for delaying the selected clock with a varying delay amount by selecting and driving one of the first clock and the second clock with a driving force that changes in response to an output signal of the voltage comparing means and the voltage comparing means; A semiconductor device having a delay means is provided.

Fixed Loop, Single Loop, Dual Loop, Split, Driving Force

Description

Semiconductor device {SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor design technique, and more particularly, to a delay locked loop of a semiconductor device having a circuit for correcting a duty ratio of a signal output from the semiconductor device, and more particularly, to a function of correcting a duty ratio. The present invention relates to a delay locked loop of a semiconductor device which occupies a relatively small area and consumes a relatively small current even in the included state.

In general, in a synchronous semiconductor memory device such as a double data rate synchronous DRAM (DDR SDRAM), a reference clock and input / output data must always be synchronized in time.

Here, the reference clock refers to external clocks (CLK, CLKB) input mainly from an external device such as a memory controller, so that the synchronous semiconductor memory device must transmit data synchronized with the reference clock in time. This means that the output point of the data transmitted from the synchronous semiconductor memory device and the edge or center of the external clocks CLK and CLKB must match exactly.

However, as shown in the example of the asynchronous semiconductor memory device, the data synchronized to the external clock (CLK, CLKB) is automatically generated by applying an external clock (CLK, CLKB) and a command to output data to a general semiconductor memory device. It is not output.

The reason why the external clocks CLK and CLKB are not synchronized in the semiconductor memory device is as follows.

First, if the external clocks (CLK, CLKB) buffered inside the semiconductor memory device through the input buffering circuit outside the semiconductor memory device are internal clocks, the internal clocks are internal components of the semiconductor memory device-control circuits, peripheral circuits, and cells. It means all the circuits included in semiconductor memory devices such as arrays. As the phase changes as it passes through, when the internal clock reaches the output buffering circuit and outputs to the outside, the internal clock and the external clocks (CLK, CLKB) Not motivated

At this time, since data output from the semiconductor memory device is output in synchronization with the internal clock, there is a phase difference between the data and the external clock CLK and CLKB as much as a phase difference occurs between the internal clock and the external clocks CLK and CLKB. do. That is, the data output from the semiconductor memory device is in an asynchronous state with the external clocks CLK and CLKB.

Therefore, in order to synchronize the phase of the external clocks CLK and CLKB and the input / output data to be outputted in time with respect to the semiconductor memory device, the semiconductor memory devices are inputted from the external clocks CLK and CLKB inputted to the semiconductor memory devices. As a result, the delay of the phase of the internal clock applied to the output pad is compensated back to the internal clock so that the phase of the internal clock is synchronized with the phase of the external clock (CLK, CLKB).

As described above, the circuit for performing the role of making the phase of the internal clock decompensated to the internal clock so that the phase of the internal clock is synchronized with the phase of the external clocks CLK and CLKB is typical. PLL: Phase Locked Loop (DLL) and Delay Locked Loop (DLL).

First, the phase locked loop (PLL) simultaneously synchronizes frequency and phase by using a frequency sequencing function when the frequency of an external clock, which is a reference input from the outside, and the frequency of an internal clock used in a semiconductor memory device, are different from each other. It is a device used to make.

The delay locked loop DLL is an apparatus used to synchronize phase only when the frequency of an external clock serving as a reference input from the outside and the frequency of an internal clock used inside the semiconductor memory device are the same.

Thus, when comparing only the characteristics of the phase delay locked loop (PLL) and the delay locked loop (DLL), the delay locked loop (PLL) has an additional function of frequency sequential function compared to the delay locked loop (DLL). Although the phase locked loop (PLL) is more likely to be used than the DLL, the delayed loop (DLL) is used more than the phase locked loop (PLL).

There are many reasons for this, but the typical reason is that the delay locked loop (DLL) is stronger in noise than the phase locked loop (PLL) and can be implemented in a smaller area.

1 is a block diagram showing the components of a delay locked loop (DLL) of a semiconductor device according to the prior art.

Referring to FIG. 1, a delay locked loop DLL of a semiconductor device according to the related art may include a first delay clock RISING_CLK corresponding to a first clock edge of a source clock REF_CLK in order to achieve delay lock. Detecting the phase difference between the delay fixing unit 100 for generating the second delay clock (FALLING_CLK) corresponding to the second clock edge (falling edge), the first delay clock (RISING_CLK) and the second delay clock (FALLING_CLK) The phase detection unit 120 for outputting the weight selection signal WR_SEL and the weight corresponding to the weight selection signal WR_SEL are reflected when the first delay clock RISING_CLK and the second delay clock FALLING_CLK are delayed and fixed. And a phase mixing unit 140 for mixing the phases of the first delay clock RISING_CLK and the second delay clock FALLING_CLK to output the delay locked loop clocks DLL_CLK_USE and DLL_CLK_DUMMY. In addition, the split unit 110a for splitting the phases of the delay locked loop clocks DLL_CLK_USE and DLL_CLK_DUMMY to generate the first and second phase split clocks RCLKDLL and FCLKDLL is identical to the split unit 160. It has a configuration, but further comprises a dummy split portion (110b) that does not actually operate.

Here, the phase mixing unit 140 may include a second delay corresponding to delay delay between the first delay lock signal LOCK_STATE_R and the second delay clock FALLING_CLK corresponding to the delay lock of the first delay clock RISING_CLK. The delayed enable signal generator 146 for generating the delayed enable signal DCC_EN in which the logic level is determined in response to the fixed signal LOCK_STATE_F, and the weight when the delayed enable signal DCC_EN is activated. A mixing control unit 142 which generates a mixing control signal CTRL for controlling the mixing ratio of the first delay clock RISING_CLK and the second delay clock FALLING_CLK in response to the selection signal WR_SEL, DCC phase mixer 144 and DCC phase for mixing the phases of the first delay clock RISING_CLK and the second delay clock FALLING_CLK at the mixing ratio corresponding to the CTRL and outputting them to the delay locked loop clock DLL_CLK_USE. Has the same configuration as the mixing unit 144, but actually And a behavior does not pile DCC phase mixer 145.

In addition, the delay fixing unit 100 compares the phases of the source clock REF_CLK and the first feedback clock FEB_CLK1 to the first clock edge RISING_CLK of the source clock REF_CLK for a time determined to achieve a delay lock. The phase of the first phase delay unit 102 for delaying the corresponding first clock CLK_IN_R and outputting it as the first delay clock RISING_CLK and the source clock REF_CLK and the second feedback clock FEB_CLK2 are compared. A second phase delay unit 104 for delaying the second clock CLK_IN_F corresponding to the second clock edge FALLING_CLK of the source clock REF_CLK and outputting the second clock clock as the second delay clock FALLING_CLK; The first delay replication model unit 103 and the second delay clock FALLING_CLK for outputting as the first feedback clock FEB_CLK1 reflecting the actual delay condition of the first clock CLK_IN_R in the first delay clock RISING_CLK. Reflects the actual delay condition of the second clock CLK_IN_F to the second feedback clock FEB_CLK2. And a second delay replication model 105 to the output document. The apparatus further includes a clock buffer unit 106 for buffering the external clocks CLK and CLKB input from the outside to output the source clocks REF_CLK and the first and second clocks CLK_IN_R and CLK_IN_F.

Here, the first phase delay unit 102 among the components of the delay fixing unit 100 generates the first delay control signal DELAY_CON1 by comparing the phases of the source clock REF_CLK and the first feedback clock FEB_CLK1. The first phase comparator 1022 and the first delay line for outputting the first clock CLK_IN_R as the first delay clock RISING_CLK by a time determined corresponding to the first delay control signal DELAY_CON1. (1024).

The second phase delay unit 104 of the components of the delay fixing unit 100 generates a second delay control signal DELAY_CON2 by comparing the phases of the source clock REF_CLK and the second feedback clock FEB_CLK2. The second phase comparator 1042 and the second delay line for delaying the second clock CLK_IN_F by the time determined corresponding to the second delay control signal DELAY_CON2 and outputting it as the second delay clock FALLING_CLK. 1044.

Referring to the operation based on the configuration of the delay lock loop according to the prior art as follows.

First, the delay fixing unit 100 of the semiconductor device according to the prior art can be viewed by dividing the operation into two parts, <before delay lock> and <after delay lock>. The difference depends on whether or not the phases of the first and second delay clocks RISING_CLK and FALLING_CLK output from the delay fixing unit are located within a predetermined range, as described in the above-described configuration. That is, if the phases of the first and second delay clocks RISING_CLK and FALLING_CLK are not located within the predetermined range, they are not delayed and may be referred to as <before delayed lock>. The first and second delay clocks (RISING_CLK) If the phase of FALLING_CLK is within the predetermined range, it is said to be delay locked and can be called as <after delay lock>.

In detail, when the delay lock loop of the semiconductor device starts operation in <before delay lock>, the source clocks REF_CLK and the first and second clocks CLK_IN_R and CLK_IN_F are both external clocks CLK and CLKB. Since the clock is generated by buffering, the source clock REF_CLK and the first and second clocks CLK_IN_R and CLK_IN_F are all the same clock.

However, since the first and second clocks CLK_IN_R and CLK_IN_F pass through the first and second delay lines 1024 and 1044, respectively, are delayed by a predetermined initial delay time and are controlled and output so as to have opposite phases. The clock REF_CLK and the first and second delay clocks RISING_CLK and FALLING_CLK are out of phase.

That is, when the first delay clock RISING_CLK corresponds to the first edge of the source clock REF_CLK, which is assumed to be the rising edge, the rising edge is increased after the initial delay time. The second delay clock FALLING_CLK is a rising edge after the initial delay time at the time corresponding to the second edge of the source clock REF_CLK, which is assumed to be a falling edge. ) Will occur.

Thereafter, while the delay lock loop of the semiconductor device starts to operate, the first delay clock RISING_CLK is delayed and output by the time set in the first delay replication model unit 103, and at this time, the first delay replication model unit 103 is output. The delay amount set in the C) delays the first clock CLK_IN_R through the internal components of the semiconductor memory device, which means all circuits included in the semiconductor memory device such as a control circuit, a peripheral circuit, and a cell array. It is configured in the same time as.

Similarly, the second delay clock FALLING_CLK is delayed and output by the time set in the second delay replication model unit 105. At this time, the first delay clock RISING_CLK is output from the first delay replication model unit 103. The delay time and the delay time of the second delay clock FALLING_CLK in the second delay replication model unit 105 are equal to each other. In other words, the delay time of the first clock CLK_IN_R passing through the internal components of the semiconductor memory device and the delay time of the second clock CLK_IN_F passing through the internal components of the semiconductor memory device are the same.

However, in the drawings, the first and second delayed replica models 103 and 105 are not inputted with the first and second delay clocks RISING_CLK and FALLING_CLK, but are delayed fixed loop clocks output from the phase mixing unit 140. It can be seen that (DLL_CLK_USE) and the dummy delay locked loop clock (DLL_CLK_DUMMY) are input to the first and second delayed replication model units 103 and 105, respectively, which means that the phase mixing unit 140 is <before delayed fixed>. This is because the component does not operate in <Only> but only after <Delayed Lock>.

That is, the phase mixing unit 140 operates as a bypass for outputting the input signal as it is in the <before delay lock> and performs an operation of mixing the phases of the signal that is input until after the delay lock.

Therefore, in the <before delay lock>, the delay locked loop clocks DLL_CLK_USE and dummy delays from which the first and second delay clocks RISING_CLK and FALLING_CLK input to the phase mixer 140 are output from the phase mixer 140. It can be regarded as the same clock as the fixed loop clock (DLL_CLK_DUMMY).

The delay lock loop of the semiconductor device according to the prior art operates to change the clocks of the <before delay lock> state having the above state as follows until the <before delay lock> state is terminated.

First, the first delay clock 1024 output from the first delay line 1024 is further controlled by appropriately controlling the first delay line 1024 and further delaying the first clock CLK_IN_R delayed by the initial delay time by the first predetermined time. The rising edge of RISING_CLK) is delayed-locked with the rising edge of the reference clock REF_CLK.

At the same time, the second delay clock 1044 outputs from the second delay line 1044 by appropriately controlling the second delay line 1044 to further delay the second clock CLK_IN_R delayed by the initial delay time by a second predetermined time. The rising edge of FALLING_CLK) is delayed-locked with the rising edge of the reference clock REF_CLK.

At this time, the first delay line 1024 delaying the first clock CLK_IN_R and the second delay line 1044 delaying the second clock CLK_IN_F have different delay amounts. That is, the first schedule time and the second schedule time are different from each other.

As described above, the rising edge of the first delay clock RISING_CLK is synchronized with the rising edge of the reference clock REF_CLK to activate the first delay lock signal LOCK_STATE_R, and the second delay clock. When the rising edge of FALLING_CLK is synchronized with the rising edge of the reference clock REF_CLK and the second delay lock signal LOCK_STATE_F is activated, the delay lock enable signal DCC_EN is activated. Before delay lock> The state is terminated.

Thereafter, the delay locked loop of the semiconductor device operates as a <after delay locked> state, in which the phase mixing unit 140 of the components of the delay locked loop does not operate as a bypass, but receives the first and second inputs. The operation of mixing the phases of the delay clocks RISING_CLK and FALLING_CLK is performed. As a result, the duty ratio of the delayed fixed loop clock DLL_CLK_USE output from the phase mixing unit 140 is corrected to 50 to 50. .

However, looking at the reason for the existence of the delay lock loop described above, it is a device that exists to synchronize the phase of the external clock and the internal clock by compensating the delay time of the internal clock phase due to the operation of the semiconductor device.

That is, when the <before delay> status ends, the internal clock that is the delay locked loop (DLL_CLK_USE, DLL_CLK_DUMMY) is the same as the first and second delay clocks (RISING_CLK, FALLING_CLK) that are considered to be the end points of the status <before delay>. Rising edges are synchronized with the reference clock REF_CLK, which is an external clock. Therefore, at the same time as the end of the <before delay lock> state, the operation of the delay lock loop should be terminated.

However, in recent semiconductor devices, more than one data is output in one cycle of the internal clock, whereas one data is output in an internal clock of one cycle.

For example, a semiconductor memory device that outputs one data at the rising edge of the delay lock loop clock DLL_CLK_USE and one data at the falling edge of the delay lock loop clock DLL_CLK_USE-DDR Many have been developed, including synchronous semiconductor memory devices such as SDRAM, DDR2 SDRAM and DDR3 SDRAM.

In this case, the logic 'high' section from the time when the rising edge of the internal clock occurs to the time when the falling edge occurs is relatively long, and the falling edge occurs. If the logic 'Low' section from the time point to the time when the rising edge occurs is relatively short, sufficient time is available for data input / output in the logic 'High' section of the internal clock. However, not enough time is provided to input / output the logic 'low' section of the internal clock, which may cause data input / output errors.

Therefore, the operation of correcting the duty ratio of the delay lock loop DLL_CLK_USE, which is an internal clock, must be performed at the end of the delay lock loop.

Looking at the specific operation of the mixing controller 140 in the <after the delay lock>, first, the logic 'high' section of the first delay clock (RISING_CLK) is the logic 'high' (High) of the reference clock (REF_CLK) Section and the logic 'high' section of the second delay clock (FALLING_CLK) is the portion that matches the logic section 'low' section of the reference clock (REF_CLK), and the first delay clock. Since (RISING_CLK) and the second delay clock (FALLING_CLK) are in a state where the rising edge is synchronized in the state of <before delay lock>, the falling edge of the first delay clock (RISING_CLK) is detected in the phase detection unit 120. A weight control signal WR_SEL is generated by comparing a falling edge time point and a falling edge time point of the second delay clock FALLING_CLK.

Thereafter, the mixing controller 142 may mix the phases of the first delay clock RISING_CLK and the second delay clock FALLING_CLK with a weight corresponding to the weight control signal WR_SEL in the DCC phase mixer 144. Adjust the value of the mixed control signal CTRL appropriately.

Through this process, the DCC phase mixer 144 generates a delay locked loop clock DLL_CLK_USE having a duty ratio of 50 to 50.

Thereafter, the phase split unit 110a splits the delay locked loop clock DLL_CLK_USE whose duty ratio DUTY RATIO is corrected to 50 to 50, thereby splitting the first edge of the delay locked loop clock DLL_CLK_USE. The second split clock FCLKDLL corresponding to the first split clock RCLKDLL and the second falling edge of the delay locked loop clock DLL_CLK_USE is generated.

In this case, the dummy DCC phase mixing unit 145 and the dummy phase split unit 110b do not need to operate. The reason for the existence of the dummy DCC phase unit 145 and the dummy phase split unit 110b itself is the DCC phase mixing. The components constituting the unit 144 and the phase split unit 110a-an inverter, a transistor, and the like-become a load having a resistance value corresponding to a resistance value of the unit 144 and the phase split unit 110a, and are input to the phase mixing unit 140 in <before delay lockout>. This is because the first and second delay clocks RISING_CLK and FALLING_CLK are bypassed in the same transmission environment. Therefore, in addition to performing the bypass operation in <before delay lock>, it is not necessary to perform any operation in <after delay lock>.

As described above, a delay locked loop clock (DLL_CLK_USE) has been generated through the operations of the <before delayed> state and the <after delayed> state of the delay locked loop.

The first objective was achieved in the <before delay lock> state of the delay lock loop because the internal clock is properly compensated for in order to synchronize the data output from the semiconductor device with the external clock.

The second purpose is to ensure that the duty ratio of the internal clock is exactly 50 to 50 so that the data is not only output from the first edge of the internal clock, but also from the second edge of the internal clock. It was achieved in <After Delay> because it allows output.

However, in order to achieve these two purposes, the method used in the delay lock loop of the semiconductor device according to the related art shown in FIG. 1 is a dual loop (DUAL LOOP) method. Depending on the state, each component of the delay lock loop may be left without actually operating.

For reference, the main difference between the delay locked loop using the dual loop method and the delay locked loop using the single loop method is that the single loop (SINGLE LOOP) is used when delaying the internal clock and the external clock. In the delay lock loop using 1) method, one inner clock is used, and the delay lock loop using the dual loop method uses 2 inner clocks. This is already well known and will not be explained any further.

For example, the mixing controller 140 does not perform the duty correction operation originally intended in the <before delay lock> state, and performs a role of bypassing and outputting the input signal as it is. At this time, the bypass is the same as the state of connecting the wire, it can be seen that it does not actually operate in the <before delay fixed> state.

In addition, the mixing controller 140 mixes the dummy DCC phase which was used as a load having a constant resistance value in the bypass operation of the <before the delay> state while the duty correction operation was originally performed in the <after the delay delay> state. Do not use section 145.

In addition, the delay fixing unit 100, the components related to the first delay clock (RISING_CLK)-the first phase delay unit 102, the first delay replication model unit 103-<before delay lock fixed> and <delay The component related to the second delay clock (FALLING_CLK)-the second phase delay unit 104 and the second delayed replication model unit 105-is used after the fixed delay. The action in the state is meaningless.

This is because the delay locked loop clock DLL_CLK_USE is a clock corresponding to the first delay clock RASING_CLK. If the delay locked loop clock DLL_CLK_USE is a clock corresponding to the second delay clock FALLING_CLK, The components related to the first delay clock RISING_CLK-the first phase delay unit 102 and the first delay replication model unit 103-will be meaningless in the state of <after the delay lock>.

In addition, the dummy phase split unit 110b, which is connected to the output terminal of the phase mixing unit 140 and contrasts with the phase split unit 110a for splitting the delay locked loop clock DLL_CLK_USE, is also bypassed in the state <before delay locked>. It is intended to be used as a load with a constant resistance in operation.

As described above, although each component constituting the delay locked loop is left without being substantially operated, in a dual loop scheme such as a delay locked loop of the semiconductor device according to the related art shown in FIG. All components must be provided for normal operation.

However, in order to solve the problem of the delayed loop using the dual loop method described above, the first purpose of the delayed fixed loop is to use a delayed fixed loop using the single loop method. Proper reverse compensation of the internal clock to ensure that the data output from the semiconductor device is synchronized to the external clock can be easily solved, but the duty ratio of the internal clock, which is the second purpose of the delay lock loop, can be maintained exactly 50 to 50. There was no way.

Therefore, inevitably, a delayed fixed loop using a dual loop method has been used in a semiconductor device, and the area occupied by the delayed fixed loop using a dual loop method in a semiconductor device is too large. Occurs.

For this reason, in a semiconductor device that is being developed to be smaller and smaller in size, it is difficult to miniaturize the semiconductor device when a delay locked loop using a dual loop method is included in the semiconductor device.

In addition, even though some components of each of the components of the delay locked loop using the dual loop method are substantially inoperable and prevented, current input to some components is continuously being consumed. The problem arises that there is a current to be made.

As a result, in a semiconductor device that is being developed to operate at lower power, a problem arises in that it is difficult to operate the semiconductor device at low power when a delay locked loop using a dual loop scheme is included in the semiconductor device. do.

The present invention has been proposed to solve the above-mentioned problems of the prior art, and provides a delayed fixed loop of a semiconductor device that occupies a relatively small area and consumes a relatively small current even in a state including a function of correcting a duty ratio. The purpose is.

According to an aspect of the present invention for achieving the above technical problem, the phase of the source clock and the feedback clock is compared to achieve a delay lock, and the internal clock corresponding to the clock edge of the source clock by the time corresponding to the comparison result Delay fixing means for delaying and outputting as a delay locked loop clock; A splitting means for receiving the delay locked loop clock and splitting the delay locked loop clock into a first clock corresponding to a first edge of the delay locked loop clock and a second clock corresponding to a second edge; Voltage generation means for generating a first voltage corresponding to the duty ratio of the first clock and a second voltage corresponding to the duty ratio of the second clock; Voltage comparing means for comparing a level of the first voltage and the second voltage; And clock delay means for delaying the selected clock with a variable delay amount by selecting and driving one of the first clock and the second clock with a driving force that changes in response to an output signal of the voltage comparing means. A semiconductor device is provided.

According to another aspect of the present invention for achieving the above technical problem, for receiving the source clock to split and output the first clock corresponding to the first edge and the second clock corresponding to the second edge of the source clock Split means; Voltage generation means for generating a first voltage corresponding to the duty ratio of the first clock and a second voltage corresponding to the duty ratio of the second clock; Voltage comparing means for comparing a level of the first voltage and the second voltage; And clock delay means for delaying the selected clock with a variable delay amount by selecting and driving one of the first clock and the second clock with a driving force that changes in response to an output signal of the voltage comparing means. A semiconductor device is provided.

The present invention described above uses a method of correcting the duty ratio at the time of splitting a delay locked loop clock output in a delay locked state in a delay locked loop, so that the delay locked loop operates in a single loop. The present invention is also applicable to a semiconductor device, and when it is used in a semiconductor device, the area occupied by the delay locked loop in the semiconductor device is relatively reduced. As a result, the size of the semiconductor device can be reduced.

In addition, since it can be applied to the delay locked loop operating in a single loop, there is an effect that can implement the same operation as the delay locked loop operating in a dual loop using a relatively small current. As a result, the size of the current consumed by the semiconductor device is reduced.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms, only the embodiments are intended to complete the disclosure of the present invention and to those skilled in the art the scope of the present invention It is provided to inform you completely.

2 is a block diagram illustrating the components of a delay locked loop (DLL) of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 2, the delay locked loop DLL of the semiconductor device according to an exemplary embodiment of the present invention compares the phases of the source clock REF_CLK and the feedback clock FEB_CLK in order to achieve delay lock, and corresponds to the comparison result. Delay height for outputting as the delay locked loop clock DLL_CLK by delaying the internal clock CLK_IN corresponding to the clock edge of the source clock REF_CLK-the rising edge or the falling edge. Responding to the first clock (RCLKDLL) and the second edge (falling edge) corresponding to the first edge (rising edge) of the delay locked loop clock (DLL_CLK) by receiving the government 200 and the delay locked loop clock (DLL_CLK) A split unit 210 for splitting and outputting to the second clock FCLKDLL, a first voltage RCLKVOL corresponding to a duty ratio of the first clock RCLKDLL, and a second clock. A voltage generator 230 for generating a second voltage FCLKVOL corresponding to the duty ratio of FCLKDLL; The first clock with the driving force varying in response to the voltage comparator 250 for comparing the level of the first voltage RCLKVOL and the second voltage FCLKVOL, and the output signals INC and DEC of the voltage comparator 250. A clock delay unit 270 for delaying the selected clock to a variable delay amount by selecting and driving one of the clocks RCLKDLL and the second clock FCLKDLL, in which the second clock FCLKDLL is selected. do. In addition, in response to the delay locked loop clock DLL_CLK, a reset signal RST, an enable signal EN, and a comparison control signal COM_PU for controlling the operations of the voltage generator 230 and the voltage comparator 250 are applied. It further includes an operation control unit 290 to generate.

Here, the voltage generator 230 is activated in response to the first edge of the first clock RCLKDLL and deactivated in response to the first edge of the second clock FCLKDLL. A CRC clock ORCLK and a second CRC clock that is activated in response to the first edge of the second clock FCLKDLL and deactivated in response to the first edge of the first clock RCLKDLL. The duty cycle of the CRC clock generator 234 for generating OFCLK, the first voltage RCLKVOL whose level is determined corresponding to the duty ratio of the first CRC clock ORCLK, and the second CRC clock OFCLK. And a voltage level determination unit 238 for outputting a second voltage FCLKVOL whose level is determined in correspondence with the ratio.

In addition, the delay fixing unit 200 may include a buffering unit 206 for generating a source clock REF_CLK by buffering externally input clocks CLK and CLKB, a source clock REF_CLK, and a feedback clock FEB_CLK. Delay comparison by delaying the phase comparison unit 202 for comparing the phases of the internal clock CLK_IN corresponding to the clock edge of the source clock REF_CLK, which is a rising edge or a falling edge. The delay line 204 is output as a loop clock DLL_CLK, and the delay amount is determined in response to the output signal DELAY_CON of the phase comparator 202, and the internal clock CLK_IN is applied to the delay locked loop clock DLL_CLK. A delay replication model unit 203 is provided for outputting as a feedback clock (FEB_CLK) reflecting the actual delay condition of the path.

FIG. 3 is a detailed circuit diagram illustrating a CRC clock generator included in a voltage generation unit among components of a delay locked loop (DLL) of a semiconductor device in accordance with an embodiment of the present invention shown in FIG. 2.

Referring to FIG. 3, the CRC clock generator 234 provided in the voltage generator 230 among the components of the delay locked loop DLL of the semiconductor device according to the embodiment of the present invention may include a first clock RCLKDLL. The first sensing unit 2342 and the first clock of the second clock FCLKDLL for generating a first toggling signal CRCOD1B for detecting a first edge of the first edge and toggling accordingly. A second sensing unit 2344 for generating a second toggling signal CRCOD2B that senses a edge and thus toggles it, and is activated in response to the first toggling signal CRCOD1B, and A first CRC clock output 2346 for outputting a first CRC clock ORCLK deactivated in response to the second toggle signal CRCOD2B, and activated in response to a second toggling signal CRCOD2B; A second CRC clock output unit 2348 is provided to output a second CRC clock OFCLK which is inactivated in response to the toggling signal CRCOD1B.

Here, the first detection unit 2342 receives the first clock RCLKDLL and outputs the delayed signal by a predetermined time, but outputs a delay Delay1 for outputting the phase by inverting its phase. And a NAND gate ND1 for receiving the RCLKDLLB and the first clock RCLKDLL and outputting the first clock signal CRCOD1B.

In addition, the second detection unit 2344 receives the second clock FCLKDLL and outputs the delayed delay by a predetermined time, but outputs a delay Delay2 for outputting the inverted phase of the delay clock. And a NAND gate ND2 for receiving the FCLKDLLB and the second clock FCLKDLL and outputting the second clock signal as the second toggle signal CRCOD2B.

The first CRC clock output unit 2346 controls the source-drain connected power supply voltage VDD terminal and the CRC clock output terminal CRCND1 in response to the first toggle signal CRCOD1B applied to the gate. To control the connection between the drain-source connected CRC clock output terminal CRCND1 and the pull-down control node PUND1 in response to the PMOS transistor P1 and the first toggle signal CRCOD1B applied to the gate. Controls that the drain-source connected pull-down control node PUND1 and the ground voltage VSS terminal are connected in response to the first NMOS transistor N1 and the inverted signal of the second toggling signal CRCOD2B applied to the gate. A second NMOS transistor N2 and a latch latch1 for preventing the CRC clock output terminal CRCND1 from floating are provided.

In addition, the second CRC clock output unit 2348 controls that the source-drain connected power supply voltage VDD terminal and the CRC clock output terminal CRCND2 are connected in response to the second toggle signal CRCOD2B applied to the gate. To control the connection between the drain-source connected CRC clock output terminal CRCND2 and the pull-down control node PUND2 in response to the PMOS transistor P2, the second toggling signal CRCOD2B applied to the gate. The drain-source connected pull-down control node PUND2 and the ground voltage VSS terminal are connected in response to the first NMOS transistor N3 and the inverted signal of the first toggle signal CRCOD1B applied to the gate. A second NMOS transistor N4 for controlling this, and a latch 2 for preventing the CRC clock output terminal CRCND2 from floating.

FIG. 4 is a timing diagram illustrating waveforms of signals input / output in the CRC clock generator according to the exemplary embodiment of the present invention shown in FIG. 3.

Referring to FIG. 4, a signal input to the CRC clock generator 234 according to an embodiment of the present invention includes a first clock RCLKDLL and a second clock FCLKDLL, and the output signal includes a first CRC. It can be seen that there is a clock ORCLK and a second CRC clock OFCLK. In addition, it can be seen that the inputted first clock RCLKDLL and the second clock FCLKDLL are signals having phases opposite to each other.

Specifically, when the first clock RCLKDLL is activated with logic 'high', the first clock signal CRCOD1B is activated with the logic 'low' (①) and the first toggle is detected. In response to the activation of the ring signal CRCOD1B, the first CRC clock ORCLK is activated with logic 'High' (②). In addition, the first CRC clock ORCLK is activated at a logic 'high' and the second CRC clock OFCLK is deactivated at the logic 'low' (8). In addition, the first toggling signal CRCOD1B is deactivated to the logic 'high' in response to the output clock RCLKDLLB of the delay Delay1, which is activated as the logic 'low' after a predetermined time. 3), however, the first CRC clock ORCLK activated with logic 'High' maintains the activation state of logic 'High' due to the latch.

Thereafter, when the second clock FCLKDLL is activated with logic 'high', the second clock signal CRCOD2B is activated with the logic 'low' (④) by detecting the second clock (FCLKDLL). In response to the activation of the ring signal CRCOD2B, the second CRC clock OFCLK is activated (5) to a logic 'high'. In addition, the second CRC clock OFCLK is activated at a logic 'high' and the first CRC clock ORCLK is deactivated (6) at a logic 'low'. After the predetermined time passes, the second toggle signal CRCOD2B is deactivated to logic 'high' in response to the output clock FCLKDLLB of the delay Delay2 that is activated as logic 'low'. (7) However, the second CRC clock OFCLK activated with logic 'High' maintains the activation state of logic 'High' due to the latch.

As a result, a first CRC clock ORCLK and a second CRC clock OFCLK are generated in which the activation period and the inactivation period of each other are completely opposite.

FIG. 5 is a circuit diagram illustrating in detail a voltage level determining unit included in a voltage generation unit among components of a delay locked loop (DLL) of a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 5, the voltage level determining unit 238 included in the voltage generation unit 230 among the components of the delay locked loop DLL of the semiconductor device according to the embodiment of the present invention may include a first CRC clock ORCLK. A first voltage level determiner 2382 for determining the level of the first voltage RCLKVOL applied to the first voltage output terminal RCLKVD and the second CRC clock OFCLK according to the ratio of the activation period to the inactivation period To the second voltage level determination unit 2384 and the reset signal RST to determine the level of the second voltage FCLKVOL applied to the second voltage output terminal FCLKVD according to the ratio of the activation section to the inactivation section In response, an equalization control unit 2386 is provided to control equalization of the levels of the first voltage output terminal RCLKVD and the second voltage output terminal FCLKVD.

Here, the first voltage level determination unit 2382 generates the distribution voltage DIVVOL1 by dividing the level of the power supply voltage VDD at the first division ratio in the activation period of the first CRC clock ORCLK. In the inactivation period of the CRC clock ORCLK, the voltage divider 2382A for dividing the level of the power supply voltage VDD at the second distribution ratio to generate the distribution voltage DIVVOL1, and activating the first CRC clock ORCLK. A voltage level mixing unit 2382B is configured to determine the level of the first voltage RCLKVOL by mixing the level of the divided voltage DIVVOL1 generated in the section and the level of the divided voltage DIVVOL1 generated in the inactive section.

The voltage divider 2382A of the components of the first voltage level determiner 2382 includes a first resistor R1 connected in series between a power supply voltage VDD terminal and a ground voltage VSS terminal, and a first resistor and a first resistor. A distribution node DIVND1 having two NMOS transistors N1 and N2 and having a drain-source connection according to the duty ratio of the first CRC clock ORCLK applied to the gate. ) And the level of the distribution voltage DIVVOL1 applied to the distribution node DIVND1 by changing the amount of current flowing between the control node PUND1 and the pull-down control node PUND1, and the second NMOS transistor N2 is connected to the gate. The drain-source connected pull-down control node PUND1 and the ground voltage VSS terminal are connected in response to the enabled enable signal EN.

Among the components of the first voltage level determining unit 2382, the voltage level mixing unit 2382B includes a capacitor C1 connected in parallel with the second resistor R2 connected in series with the distribution node DIVND1. The level of the divided voltage DIVVOL1 is changed at a speed corresponding to a predetermined time constant (τ).

That is, the first voltage level determiner 2382 controls the level of the first voltage RCLKVOL to be relatively low when the activation period of the first CRC clock ORCLK is relatively longer than the inactivation period. When the deactivation section of the CRC clock ORCLK is relatively longer than the activation section, the level of the first voltage RCLKVOL is relatively increased.

In addition, the second voltage level determiner 2384 generates the distribution voltage DIVVOL2 by dividing the level of the power supply voltage VDD at the first distribution ratio in the activation period of the second CRC clock OFCLK. In the inactivation section of the CRC clock OFCLK, the voltage distribution section 2384A for dividing the level of the power supply voltage VDD by the second distribution ratio to generate the distribution voltage DIVVOL2, and the activation section of the second CRC clock OFCLK. A voltage level mixing unit for determining the level of the second voltage FCLKVOL by mixing the level of the divided voltage DIVVOL2 generated in the control circuit and the level of the divided voltage DIVVOL2 generated in the inactive section of the second CRC clock OFCLK. 2384B.

The voltage divider 2384A of the components of the second voltage level determiner 2384 includes the first resistor R3 and the first and second connected in series between the power supply voltage VDD terminal and the ground voltage VSS terminal. The distribution node DIVND2 having NMOS transistors N3 and N4 and having a drain-source connection according to the duty ratio of the second CRC clock OFCLK applied to the gate is provided. ) And the level of the distribution voltage DIVVOL2 by changing the amount of current flowing between the P1 and the pull-down control node PUND2, and the second NMOS transistor N4 is applied to the enable signal EN applied to the gate. In response, the drain-source connected pull-down control node PUND2 and the ground voltage VSS terminal are connected to each other.

Further, the voltage level mixing unit 2384B among the components of the second voltage level determining unit 2384 includes a capacitor C2 connected in parallel with the second resistor R4 connected in series with the distribution node DIVND2. The level of the voltage DIVVOL2 is changed at a speed corresponding to a predetermined time constant (τ).

That is, the second voltage level determiner 2342 controls the level of the second voltage FCLKVOL to be relatively low when the activation period of the second CRC clock OFCLK is relatively longer than the inactivation period. When the deactivation section of the CRC clock OFCLK is relatively longer than the activation section, the level of the second voltage FCLKVOL is relatively increased.

The equalization control unit 2386 may include an NMOS transistor for controlling the connection of the drain-source-connected first voltage output terminal RCLKVD and the second voltage output terminal FCLKVD in response to a reset signal RST applied to the gate. N5).

FIG. 6 is a circuit diagram illustrating in detail a voltage comparator among components of a delay locked loop (DLL) of a semiconductor device in accordance with an embodiment of the present invention illustrated in FIG. 2.

Referring to FIG. 6, the voltage comparator 250 of the components of the delay locked loop DLL of the semiconductor device according to the embodiment of the present invention is applied with a first voltage RCLKVOL applied through a first input terminal (+). And a comparator 252 for outputting the comparison signal COMP_SIG by comparing the level of the second voltage FCLKVOL applied through the second input terminal (-) and the comparison control signal CMP_PU when the comparison signal is activated. In response to COMP_SIG, an increase / decrease signal output unit 254 for activating and outputting any one of the increase and decrease signals INC and DEC is provided.

Here, the increase / decrease signal output unit 254 receives the first NAND gate ND1 for receiving and outputting the comparison signal COMP_SIG and the comparison control signal CMP_PU, and the output signal of the first NAND gate ND1. The first inverter INT1 output as the increase signal INC, the inverted signal of the comparison signal COMP_SIG, the second NAND gate ND2 for receiving and outputting the comparison control signal CMP_PU, and the second NAND gate ( And a second inverter INT2 that receives the output signal of ND2) and outputs it as a reduction signal DEC.

FIG. 7 is a detailed circuit diagram illustrating the clock delay unit 270 of the delay locked loop DLL of the semiconductor device in accordance with the embodiment of the present invention.

Referring to FIG. 7, the clock delay unit 270 of the components of the delay locked loop DLL of the semiconductor device according to the embodiment stores data CTRL <0: 4> having a predetermined initial value. The value of the data CTRL <0: 4> stored at a predetermined rate is increased in response to the increase signal INC output from the voltage comparator 250, and is stored at the predetermined rate in response to the decrease signal DEC. The clock is connected to the data storage unit 272 for reducing the value of the data CTRL <0: 4> and one of the clock terminals of the first clock RCLKDLL terminal and the second clock FCLKDLL terminal. In the drawing, the second clock FCLKDLL is driven, and has a clock driver 274 whose driving force changes in response to the value of the data CTRL <0: 4> stored in the data storage unit 272. .

Here, the clock driver 274 includes a plurality of driving elements 274A, 274B, 274C, 274D, and 274E connected in parallel to one of the clock terminals of the first clock RCLKDLL stage and the second clock FCLKDLL stage. ), And each of the driving elements 274A, 274B, 274C, 274D, and 274E are independently turned on / off in response to the data CTRL <0: 4> values stored in the data storage unit 272.

At this time, each of the driving elements 274A, 274B, 274C, 274D, and 274E may have different driving forces, or may have the same driving force.

That is, as shown in the drawings, each of the driving elements 274A, 274B, 274C, 274D, and 274E may be inverters having different sizes or inverters having the same size.

In addition, when the driving elements 274A, 274B, 274C, 274D, and 274E provided in the clock driver 274 are inverters as shown in the drawings, the configuration of each inverter will be described in detail. Like the general inverter, 274A, 274B, 274C, 274D, and 274E receive the clock from one of the clock stages of the first clock RCLKDLL stage and the second clock FCLKDLL stage, and then invert the driving force with a predetermined driving force. The first PMOS transistors P1A, P1B, P1C, P1D, and P1E, the first NMOS transistors N1A, N1B, N1C, N1D, and N1E, and the data CTRL <0: 4> stored in the data storage unit 272 Second PMOS transistors (P2A, P2B, P2C, P2D, P2E) and second NMOS transistors (N2A, N2B, N2C, N2D, N2E) for controlling the respective inverters on and off in response to the value do.

Here, in order to change the sizes of the respective inverters 274A, 274B, 274C, 274D, and 274E, the first and second NMOS transistors N1A and N1B included in the respective inverters 274A, 274B, 274C, 274D, and 274E may be used. , N1C, N1D, N1E, N2A, N2B, N2C, N2D, N2E, and first and second PMOS transistors (P1A, P1B, P1C, P1D, P1E, P2A, P2B, P2C, P2D, P2E) ) And length are different.

For example, each of the inverters 274A, 274B, 274C, 274D, and 274E may have the same length and different widths as follows.

When the current driving ratio of the general NMOS transistor and the PMOS transistor is '2', the widths of the first and second NMOS transistors N1A and N2A of the first inverter 274A are '1W'. The first and second PMOS transistors P1A, The width of P2A is '2W', and the widths of the first and second NMOS transistors N1B and N2B of the second inverter 274B are '2W'. The widths of the first and second PMOS transistors P1B and P2B are different. The width of the first and second NMOS transistors N1C and N2C of the third inverter 274C is 4W, and the width of the first and second PMOS transistors P1C and P2C is 8W. The widths of the first and second NMOS transistors N1D and N2D of the fourth inverter 274D are '8W', and the widths of the first and second PMOS transistors P1D and P2D are '16W'. The widths of the first and second NMOS transistors N1E and N2E of 274E are '16W' so that the widths of the first and second PMOS transistors P1E and P2E are '32W'.

In this state, the first and second NMOS transistors N1A and N2A and the first and second NMOS transistors 274A of the data CTRL <0: 4> stored in the data storage unit 272 according to the value of CTRL <0>. The first and second PMOS transistors P1A and P2A are configured to be controlled on / off, and the first and second NMOS transistors N1B and N2B of the second inverter 274B according to the value of CTRL <1>. And the first and second PMOS transistors P1B and P2B are controlled to be turned on and off, and according to the value of CTRL <2>, the first and second NMOS transistors N1C, N2C and the first and second PMOS transistors P1C and P2C are configured to be controlled on / off, and according to the value of CTRL <3>, the first and second NMOS transistors of the fourth inverter 274D N1D and N2D and the first and second PMOS transistors P1D and P2D are configured to be controlled on / off, and the first and second NMOS of the fifth inverter 274E according to the value of CTRL <4>. The transistors N1E and N2E and the first and second PMOS transistors P1E and P2E are turned on / off (O). n / Off) control, the clock driver 274 of the first clock (RCLKDLL) stage and the second clock (FCLKDLL) stage in accordance with the data (CTRL <0: 4>) stored in the data storage unit 272 The magnitude of the driving force for driving any one clock stage can vary.

FIG. 8 is a timing diagram illustrating waveforms according to an operation of a clock driver among the components of the clock delay unit illustrated in FIG. 7.

Referring to FIG. 8, each of the driving elements 274A, 274B, 274C, 274D, and 274E included in the clock driver 274 among the components of the clock delay unit 270 illustrated in FIG. 7 are shown in FIG. 7. As described above, when the clock inputted to the respective inverters 274A, 274B, 274C, 274D, and 274E is referred to as 'A', it is output from the respective inverters 274A, 274B, 274C, 274D, and 274E. It can be seen that the delay amount of the clock 'B' varies depending on the data CTRL <0: 4> stored in the data storage unit 272.

Specifically, when the initial value of the data CTRL <0: 4> stored in the data storage unit 272 is' 10000 ', the clocks' outputted from the respective inverters 274A, 274B, 274C, 274D and 274E The initial delay value of B 'may be referred to as' D0'.

In this state, when the data CTRL <0: 4> stored in the data storage unit 272 is changed to '01111', the clock 'B' output from each inverter 274A, 274B, 274C, 274D, or 274E is output. It can be seen that the delay value of 'becomes' D1' which is larger than 'D0'.

In addition, when the data CTRL <0: 4> stored in the data storage unit 272 is changed to '01110', the clock 'B' output from each of the inverters 274A, 274B, 274C, 274D, and 274E is output. It can be seen that the delay value is 'D2' which is larger than 'D1'.

However, when the data CTRL <0: 4> stored in the data storage unit 272 is changed to '10001', the clock 'B' output from each of the inverters 274A, 274B, 274C, 274D, and 274E is output. It can be seen that the delay value is 'D-1' which is smaller than 'D0'.

In addition, when the data CTRL <0: 4> stored in the data storage unit 272 is changed to '10010', the clock 'B' output from each of the inverters 274A, 274B, 274C, 274D, and 274E is output. It can be seen that the delay value is 'D-2' which is smaller than 'D-1'.

As described above, the driving force of the clock driver 274 is changed according to the data CTRL <0: 4> stored in the data storage unit 272, so that the first clock RCLKDLL stage connected to the clock delay unit 270 and The second clock FCLKDLL may be delayed and transmitted by a variable delay amount of a clock transmitted to any one of the clock stages.

The delay lock loop (DLL) operation of the semiconductor device according to the exemplary embodiment of the present invention will be described as follows.

First, the delay lock 200 shown in FIG. 2 is a single loop method, and is very similar to the operation of <before delay lock> of a delay lock loop operated in a dual loop method shown in FIG. similar.

That is, the delay amount of the delay line 204 is properly adjusted so that the internal clock CLK_IN, which has been synchronized with the source clock REF_CLK at the beginning of operation, can be synchronized again after being delayed by a delay time predetermined by the delay replication model unit 203. That's how it's controlled. Accordingly, the delay locked loop clock DLL_CLK is a clock in which a source clock REF_CLK and a clock edge-a rising edge or a falling edge-are synchronized.

Subsequently, the split unit 210 receives the delay locked loop clock DLL_CLK and the second clock FCLKDLL corresponding to the first clock RCLKDLL and the second falling clk corresponding to the first edge. The first edge (rising edge) and the second edge (falling clk) of the delay locked loop clock (DLL_CLK) are opposite to each other-the first edge may be a falling edge. . In this case, since the second edge becomes a rising edge, the first clock RCLKDLL and the second clock FCLKDLL have phases opposite to each other.

FIG. 9 is a timing diagram illustrating waveforms of signals input and output in a delay locked loop DLL of a semiconductor device according to example embodiments.

Referring to FIG. 9, it can be seen that as described above, the first clock RCLKDLL and the second clock FCLKDLL output from the splitter 210 have a phase opposite to each other and toggle.

In detail, the CRC clock generator 234 of the voltage generator 230 receives the first clock RCLKDLL to generate the first CRC clock ORCLK, and receives the second clock fclkdll to receive the second CRC. Generate a clock OFCLK.

At this time, when comparing the waveforms of the first and second clocks RCLKDLL and FCLKDLL generated with the waveforms of the first and second CRC clocks ORCLK and OFCLK, the first and second clocks are compared with the first and second clocks RCLKDLL and FCLKDLL. It can be seen that the first and second CRC clocks ORCLK and OFCLK are identical except that they are delayed for a certain time.

However, the biggest difference between the first and second clocks RCLKDLL and FCLKDLL and the first and second CRC clocks ORCLK and OFCLK is a delay that delays the clock itself in the case of the first and second clocks RCLKDLL and FCLKDLL. Although the amount changes, i.e., the output comes earlier or later depending on the delay time while maintaining the ratio of the activation interval length to the inactivation interval length, but the first and second CRC clocks ORCLK and OFCLK And the ratio of the length of the activation section to the length of the inactivation section changes according to the change of the second clocks RCLKDLL and FCLKDLL.

Therefore, the duty ratio of the first and second clocks RCLKDLL and FCLKDLL, which were not 50 to 50 at the time of initial operation, does not remain as 50 to 50 as time passes. However, when comparing only the first edge (rising edge) of the first clock (RCLKDLL) and the first edge (rising edge) of the second clock (FCLKDLL) it can be seen that the time point is different. That is, the time from the first edge of the first clock RCLKDLL to the first edge of the second clock FCLKDLL is referred to as a first time and the first time of the second clock FCLKDLL. If the time from the rising edge to the first edge of the first clock RCLKDLL is referred to as the second time, the ratio of the first time and the second time is not 50 to 50 at the time of initial operation. As it passes by, it gets closer to 50-50.

In this case, the first time corresponds to the activation period of the first CRC clock ORCLK and the deactivation period of the second CRC clock OFCLK, and the second time is the deactivation period and the first time of the first CRC clock ORCLK. 2 The time corresponding to the activation period of the CRC clock OFCLK.

Referring to FIG. 9, which is the result of the simulation, the duty ratios of the first and second clocks RCLKDLL and FCLKDLL do not vary, but the duty ratios of the first and second CRC clocks ORCLK and OFCLK vary. have.

Specifically, in the initial operation, the ratio of the inactivation period to the activation period of the first CRC clock ORCLK is 46.4%, but the ratio of the inactivation period to the activation period of the first CRC clock ORCLK is 49.4 after a certain time passes. It can be seen that it becomes%.

Similarly, during the initial operation, the ratio of the inactivation interval to the activation interval of the second CRC clock OFCLK is 53.6%, but the ratio of the inactivation interval to the activation interval of the second CRC clock OFCLK is 50.6% after a certain time. It can be seen that.

Also, in the initial operation in which the duty ratios of the first and second CRC clocks ORCLK and OFCLK are relatively large, the first and second voltages corresponding to the duty ratios of the first and second CRC clocks ORCLK and OFCLK may be reduced. Although the levels of RCLKVOL and FCLKVOL are relatively different, the duty cycles of the first and second CRC clocks ORCLK and OFCLK during the initial operation in which the duty ratios of the first and second CRC clocks ORCLK and OFCLK are relatively widened. It can be seen that the levels of the first and second voltages RCLKVOL and FCLKVOL corresponding to the ratios differ relatively little.

In this case, it can be seen that the reset signal RST and the comparison control signal CMP_PU are periodically activated to control the operations of the voltage generator 230 and the voltage comparator 250.

In addition, it can be seen that the increase signal INC and the decrease signal DEC output from the voltage comparator 250 are also appropriately activated according to the operation of the delay lock loop.

At this time, the situation in which the increase signal (INC) is activated rather than the decrease signal (DEC) is shown in many waveforms, the value is changed depending on the ratio of the duty ratio of the first and second CRC clock (ORCLK, OFCLK) Can be.

Similarly, the output signal CTRL <0: 4> of the data storage unit 272 among the components of the voltage delay unit 270 for changing the driving force of the clock driver 274 among the components of the clock delay unit 270. It can also be seen that it is properly activated according to the operation of the delay lock loop.

In addition, the output signal CTRL <0: 4> of the data storage unit 272 among the components of the voltage delay unit 270 is an increase signal INC rather than the decrease signal DEC among the output signals of the voltage comparator 250. It is shown as a waveform more affected by the value, which may also vary depending on the ratio of duty ratios of the first and second CRC clocks ORCLK and OFCLK.

As described above, according to the exemplary embodiment of the present invention, a dual loop is used by using a method of correcting a duty ratio at a time of splitting a delay locked loop clock output in a delay locked state. The duty ratio of delayed fixed loop clock (DLL_CLK), which is delayed and outputted, can be corrected to 50 to 50 even in delayed fixed loops that operate in a single loop type with a simple configuration compared to delayed fixed loops that operate in a method. have.

In order to compensate for the duty ratio conventionally used a delayed fixed loop operating in a dual loop (dual loop) method, a delayed fixed loop operating in a single loop method (single loop) proposed in the present invention to a semiconductor device When used, the area occupied by the delayed fixed loop in the semiconductor device may be relatively reduced, and thus, the size of the semiconductor device may be easily reduced.

In addition, the delay locked loop operating in the dual loop method has a larger current consumption than the delay locked loop operating in the single loop method, and the delay locked loop proposed by the present invention is a single loop ( It operates in a single loop) mode, so it can be operated using relatively little current. For this reason, when the delayed fixed loop operating in the single loop method according to the present invention is used for the semiconductor device, the amount of current consumed in the semiconductor device can be reduced.

The present invention described above is not limited to the above-described embodiments and drawings, and various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be obvious to those with knowledge.

For example, in the above-described embodiment, the first edge is expressed as if it is the same as the rising edge, and the second edge is often expressed as if it is the same as the falling edge. It is expressed as the same as (rising edge), and includes the case where the first edge is expressed as the same as the falling edge (falling edge).

In addition, the logic gate and the transistor illustrated in the above-described embodiment should be implemented in different positions and types depending on the polarity of the input signal.

1 is a block diagram showing the components of a delay locked loop (DLL) of a semiconductor device according to the prior art.

2 is a block diagram showing components of a delay locked loop (DLL) of a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a detailed circuit diagram illustrating a CRC clock generation unit provided in a voltage generation unit among components of a delay locked loop (DLL) of a semiconductor device according to an embodiment of the present invention shown in FIG. 2.

FIG. 4 is a timing diagram showing waveforms of signals input / output in a CRC clock generator according to the embodiment of the present invention shown in FIG.

FIG. 5 is a circuit diagram illustrating in detail a voltage level determining unit included in a voltage generation unit among components of a delayed fixed loop (DLL) of a semiconductor device according to the embodiment of the present invention shown in FIG. 2.

FIG. 6 is a circuit diagram illustrating a voltage comparison unit among components of a delay locked loop (DLL) of a semiconductor device in accordance with an embodiment of the present invention illustrated in FIG.

FIG. 7 is a circuit diagram illustrating in detail a clock delay unit 270 of components of a delay locked loop (DLL) of a semiconductor device in accordance with an embodiment of the present invention shown in FIG. 2.

FIG. 8 is a timing diagram illustrating waveforms according to an operation of a clock driver among the components of the clock delay unit illustrated in FIG. 7.

9 is a timing diagram illustrating waveforms of signals input and output in a delay locked loop (DLL) of a semiconductor device according to an exemplary embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

100, 200: delayed fixing unit 110a, 210: phase split unit

110b: dummy phase split unit 230: voltage generator

250: voltage comparison unit 270: clock delay unit

290: operation control unit 234: CRC clock generation unit

238: voltage level determining unit 272: data storage unit

274: clock driver

Claims (29)

Delay lock means for comparing the phases of the source clock and the feedback clock to achieve delay lock, and delaying the internal clock corresponding to the clock edge of the source clock by a time corresponding to the comparison result and outputting the delay clock as a delay locked loop clock; A splitting means for receiving the delay locked loop clock and splitting the delay locked loop clock into a first clock corresponding to a first edge of the delay locked loop clock and a second clock corresponding to a second edge; Voltage generation means for generating a first voltage corresponding to the duty ratio of the first clock and a second voltage corresponding to the duty ratio of the second clock; Voltage comparing means for comparing a level of the first voltage and the second voltage; And A clock delay means for delaying one of the clocks of the first clock and the second clock, the delayed amount being changed corresponding to the output signal of the voltage comparing means; A semiconductor device comprising a. The method of claim 1, And operation control means for generating a reset signal, an enable signal, and a comparison control signal for controlling the operation of said voltage generating means and said voltage comparing means in response to said delay locked loop clock. The method of claim 2, The voltage generation means, A first CRC clock activated in response to the first edge of the first clock and deactivated in response to the first edge of the second clock, and activated in response to the first edge of the second clock; A CRC clock generator for generating a second CRC clock which is deactivated in response to the first edge; And A voltage level determining unit for outputting the first voltage whose level is determined corresponding to the duty ratio of the first CRC clock and the second voltage whose level is determined corresponding to the duty ratio of the second CRC clock. A semiconductor device characterized in that it comprises. The method of claim 3, The CRC clock generator, A first sensing unit for generating a first toggling signal for sensing a first edge of the first clock and toggling accordingly; A second sensing unit for generating a second toggling signal which senses a first edge of the second clock and toggles it accordingly; A first CRC clock output unit configured to output the first CRC clock activated in response to the first toggling signal and deactivated in response to the second toggling signal; And And a second CRC clock output unit configured to output the second CRC clock that is activated in response to the second toggling signal and deactivated in response to the first toggling signal. The method of claim 3, The voltage level determiner, A first voltage level determiner configured to determine a level of the first voltage applied to a first voltage output terminal according to a ratio of an activation period to an inactivation period of the first CRC clock; A second voltage level determiner configured to determine a level of the second voltage applied to a second voltage output terminal according to a ratio of an activation period to an inactivation period of the second CRC clock; And And an equalization control unit for controlling equalization of the level of the first voltage output terminal and the second voltage output terminal in response to the reset signal. The method of claim 5, The first voltage level determiner, If the activation period of the first CRC clock is relatively longer than the deactivation period, the first voltage is controlled to be relatively low, and if the deactivation period of the first CRC clock is relatively longer than the activation period, the first A semiconductor device characterized by controlling so that the level of one voltage is relatively high. The method of claim 5, The first voltage level determiner, In the activation period of the first CRC clock, the distribution voltage is generated by dividing the level of the power supply voltage by the first division ratio, and in the inactivation period of the first CRC clock, the distribution of the power supply voltage is divided by the second distribution ratio. A voltage divider for generating a voltage; And And a voltage level mixing unit configured to determine the level of the first voltage by mixing the level of the divided voltage generated in the activation period of the first CRC clock and the level of the divided voltage generated in the inactive period of the first CRC clock. A semiconductor device characterized in that. The method of claim 5, The second voltage level determiner, If the activation period of the second CRC clock is relatively longer than the deactivation period, the second voltage level is controlled to be relatively low, and if the deactivation period of the second CRC clock is relatively longer than the activation period, the first A semiconductor device characterized by controlling so that the level of two voltages becomes relatively high. The method of claim 5, The second voltage level determiner, In the activation period of the second CRC clock, the power supply voltage is divided by a first division ratio to generate a distribution voltage. In the inactivation period of the second CRC clock, the power distribution voltage is divided by a second distribution ratio. A voltage divider for generating a; And A voltage level mixing unit configured to determine the level of the second voltage by mixing the level of the divided voltage generated in the activation period of the second CRC clock and the level of the divided voltage generated in the inactive period of the second CRC clock. A semiconductor device characterized in that it comprises. The method of claim 2, The voltage comparison means, A comparator for comparing a level of the first voltage applied through a first input terminal with a level of the second voltage applied through a second input terminal to output a comparison signal; And an increase / decrease signal output unit configured to activate and output any one of an increase and a decrease signal in response to the comparison signal when the comparison control signal is activated. The method of claim 1, The clock delay means, A data storage unit for storing data having a predetermined initial value and increasing or decreasing the value of the data at a predetermined rate in response to an output signal of the voltage comparing means; And And a clock driver for driving a clock which is connected to any one of the clock stages of the first clock stage and the second clock stage, and whose driving force is changed in correspondence to the value of the data stored in the data storage. Semiconductor device. The method of claim 11, The clock driver, A plurality of driving elements connected in parallel to either one of the first clock stage and the second clock stage in parallel, and each driving element is independently turned on / off corresponding to a data value stored in the data storage unit; A semiconductor device, characterized in that the controlled off. The method of claim 12, Each driving element has a different driving force. The method of claim 12, Each drive element is a semiconductor element, characterized in that the inverter having a different size. The method of claim 1, The delay fixing means, A buffering unit configured to generate the source clock by buffering an externally input clock; A phase comparison unit for comparing phases of the source clock and the feedback clock; A delay line delaying an internal clock corresponding to a clock edge of the source clock and outputting the delayed clock as a delay locked loop clock, the delay amount being determined in response to an output signal of the phase comparator; And And a delay replication model unit in the delay lock loop clock for outputting the feedback clock by reflecting an actual delay condition of the internal clock path. Splitting means for receiving a source clock and splitting the source clock into a first clock corresponding to a first edge of the source clock and a second clock corresponding to a second edge of the source clock; Voltage generation means for generating a first voltage corresponding to the duty ratio of the first clock and a second voltage corresponding to the duty ratio of the second clock; Voltage comparing means for comparing a level of the first voltage and the second voltage; And A clock delay means for delaying one of the clocks of the first clock and the second clock, and changing the delay amount corresponding to the output signal of the voltage comparing means; A semiconductor device comprising a. The method of claim 16, And operation control means for generating a reset signal, an enable signal, and a comparison control signal for controlling operations of the voltage generating means and the voltage comparing means in response to the source clock. The method of claim 17, The voltage generation means, A first CRC clock activated in response to the first edge of the first clock and deactivated in response to the first edge of the second clock, and activated in response to the first edge of the second clock; A CRC clock generator for generating a second CRC clock which is deactivated in response to the first edge; And A voltage level determining unit for outputting the first voltage whose level is determined corresponding to the duty ratio of the first CRC clock and the second voltage whose level is determined corresponding to the duty ratio of the second CRC clock. A semiconductor device characterized in that it comprises. The method of claim 18, The CRC clock generator, A first sensing unit for generating a first toggling signal for sensing a first edge of the first clock and toggling accordingly; A second sensing unit for generating a second toggling signal which senses a first edge of the second clock and toggles it accordingly; A first CRC clock output unit configured to output the first CRC clock activated in response to the first toggling signal and deactivated in response to the second toggling signal; And And a second CRC clock output unit configured to output the second CRC clock that is activated in response to the second toggling signal and deactivated in response to the first toggling signal. The method of claim 18, The voltage level determiner, A first voltage level determiner configured to determine a level of the first voltage applied to a first voltage output terminal according to a ratio of an activation period to an inactivation period of the first CRC clock; A second voltage level determiner configured to determine a level of the second voltage applied to a second voltage output terminal according to a ratio of an activation period to an inactivation period of the second CRC clock; And And an equalization control unit for controlling equalization of the level of the first voltage output terminal and the second voltage output terminal in response to the reset signal. The method of claim 20, The first voltage level determiner, When the activation period of the first CRC clock is relatively long compared to the inactivation period, the level of the first voltage is controlled to be relatively low, and when the inactivation period of the first CRC clock is relatively longer than the activation period. And controlling the level of the first voltage to be relatively high. The method of claim 20, The first voltage level determiner, In the activation period of the first CRC clock, the distribution voltage is generated by dividing the level of the power supply voltage by the first division ratio, and in the inactivation period of the first CRC clock, the distribution of the power supply voltage is divided by the second distribution ratio. A voltage divider for generating a voltage; And A voltage level mixing unit configured to determine the level of the first voltage by mixing the level of the divided voltage generated in the activation period of the first CRC clock and the level of the divided voltage generated in the inactive period of the first CRC clock. A semiconductor device characterized in that it comprises. The method of claim 20, The second voltage level determiner, If the activation period of the second CRC clock is relatively longer than the deactivation period, the second voltage level is controlled to be relatively low, and if the deactivation period of the second CRC clock is relatively longer than the activation period, the first A semiconductor device characterized by controlling so that the level of two voltages is relatively high. The method of claim 20, The second voltage level determiner, In the activation period of the second CRC clock, the power supply voltage is divided by a first division ratio to generate a distribution voltage. In the inactivation period of the second CRC clock, the power distribution voltage is divided by a second distribution ratio. A voltage divider for generating a; And A voltage level mixing unit configured to determine the level of the second voltage by mixing the level of the divided voltage generated in the activation period of the second CRC clock and the level of the divided voltage generated in the inactive period of the second CRC clock. A semiconductor device characterized in that it comprises. The method of claim 17, The voltage comparison means, A comparator for comparing a level of the first voltage applied through a first input terminal with a level of the second voltage applied through a second input terminal to output a comparison signal; And an increase / decrease signal output unit configured to activate and output any one of an increase and a decrease signal in response to the comparison signal when the comparison control signal is activated. The method of claim 16, The clock delay means, A data storage unit for storing data having a predetermined initial value and increasing or decreasing the value of the data at a predetermined rate in response to an output signal of the voltage comparing means; And And a clock driver for driving a clock which is connected to any one of the clock stages of the first clock stage and the second clock stage, and whose driving force is changed in correspondence to the value of the data stored in the data storage. Semiconductor device. The method of claim 26, The clock driver, A plurality of driving elements connected in parallel to either one of the first clock stage and the second clock stage in parallel, and each driving element is independently turned on / off corresponding to a data value stored in the data storage unit; A semiconductor device, characterized in that the controlled off. The method of claim 27, Each driving element has a different driving force. The method of claim 27, Each drive element is a semiconductor element, characterized in that the inverter having a different size.

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