KR100920844B1 - Semiconductor memory apparatus - Google Patents

Abstract

PURPOSE: A semiconductor memory device is provided to reduce an occupied dimension of a memory cell by controlling a voltage supplied to a source, a drain, and a gate of an FBC(Floating Body Cell) transistor according to an operation mode. CONSTITUTION: A semiconductor memory device includes a memory cell block(19), a word line driver(12), a source line driver(13), and a bit line driver(16). The memory cell block includes a gate connected to a word line, a drain and a source connected to a bit line and a source line. The memory cell block includes a plurality of FBC transistors which form a transistor pair by sharing the source line. The word line driver supplies a voltage to the word line according to an operation mode. The source line driver supplies a voltage to the source line according to the operation mode. The bit line driver supplies a voltage to the bit line according to the operation mode.

Description

Semiconductor Memory Apparatus

The present invention relates to a semiconductor memory device, and more particularly, to a memory cell of a semiconductor memory device and a control circuit thereof.

In general, DRAM (Dynamic Random Access Memory) has a large number of memory cells consisting of one transistor and one capacitor to store data. However, the memory cell of such a structure is not easy to reduce the area of the memory core region, and thus served as a technical limitation in improving the integration degree of the semiconductor memory device. Thus, a floating body cell (FBC) technology has been developed to implement a transistor and a capacitor of a memory cell into one transistor.

Hereinafter, with reference to the accompanying drawings will be described in more detail for the FBC technology.

1 is a cross-sectional view of a transistor implementing an FBC, and exemplarily shows an N-type transistor.

As shown, a transistor implementing FBC has an N-type impurity doped in the source 1 and the drain 2, like a typical N-type MOS transistor, and the source 1 and the drain ( The gate electrode 3 and the gate oxide film 4 are formed in a predetermined region of the upper layer of 2). However, the insulating layer 5 is provided at the center of the body region, and thus the body region has a characteristic of being divided into the floating body portion 6 and the substrate portion 7. At this time, the floating body portion 6 and the substrate portion 7 are doped with P-type impurities.

As the insulating layer 5 is provided between the floating body portion 6 and the substrate portion 7, the insulating layer 5 is applied to the source 1, the drain 2, and the gate electrode 3, respectively. Holes accumulate in the floating body portion 6 due to the voltage levels, resulting in the effect of forming a virtual capacitor in the FBC. Due to the characteristics of the capacitor generated as described above, the transistor may be utilized as a memory cell in which a switching transistor and a memory cell are combined.

In order to implement the above-described FBC technology, during the read operation and the write operation, the source, the drain, and the gate of the transistor must receive the correct voltage. In addition, the FBC technology requires support for a hold operation as well as a read and write operation. In the write operation, a distinction between an operation of inputting a logic value '1' and an operation of inputting a logic value '0' is required. Do.

As such, Table 1 summarizes the levels of the source, drain, and voltage to be applied to the source according to each operation.

TABLE 1

Light "1" action Light "0" behavior Lead behavior Hold action Source voltage 2.5V 2.5V 2.5V 0 V Drain voltage 0 V 0.5 V Don't care Don't care Gate voltage 0.5 V 0.5 V -1.0V -1.5V

As can be seen from Table 1, the cell transistor in the FBC technology has to be applied to the source, drain and gate, respectively, the voltage level set according to each situation in performing the operation divided into four types. For this purpose, a circuit for supplying the above voltages to the source, the drain and the gate of the cell transistor should be provided for each operation.

To date, the above-described FBC technology has been difficult to be utilized as a memory cell of a semiconductor memory device because circuits for supplying respective voltages to the source, drain and gate of each cell transistor have not been developed. to be. Therefore, in order to apply the FBC technology to improve the integration of semiconductor memory devices, the development of related circuits is urgently required.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and there is a technical problem to provide a semiconductor memory device in which FBC technology is implemented in a cell transistor in a memory core region.

In addition, the present invention has another technical problem to provide a semiconductor memory device that improves the degree of integration by reducing the area occupied by the memory core area.

According to an embodiment of the present invention, a semiconductor memory device includes a gate connected to a word line, a drain and a source connected to a bit line and a source line, respectively, and the transistor is shared by the source line. A memory cell block including a plurality of FBC transistors forming a pair; A word line driver supplying a voltage to the word line in accordance with an operation mode; A source line driver supplying a voltage to the source line according to an operation mode; And a bit line driver supplying a voltage to the bit line according to an operation mode, wherein the bit line driver distinguishes whether or not to enter a write operation mode by using a column write indication signal. The logic value is determined to drive the driving data to the first light drain voltage or the second light drain voltage level.

In addition, a semiconductor memory device according to another embodiment of the present invention, the first FBC transistor; A second FBC transistor sharing a source with the first FBC transistor; A word line driver providing one of a write gate voltage, a read gate voltage, and a hold gate voltage to the first and second FBC transistors; A source line driver providing an active source voltage or a hold source voltage to the first and second FBC transistors; And a bit line driver providing a first write drain voltage or a second write drain voltage to the first and second FBC transistors, wherein the first FBC transistor and the second FBC transistor are connected to different word lines. It is characterized by.

The semiconductor memory device of the present invention controls the voltage supplied to the source, drain, and gate of the FBC transistor according to the operation mode, thereby creating the effect of reducing the occupied area of the memory cell by implementing the FBC technology in the cell transistor.

In addition, the semiconductor memory device of the present invention uses the FBC transistor as a cell transistor, thereby creating an effect of reducing the occupied area of the memory core region and improving the degree of integration.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

2 is a block diagram illustrating a configuration of a memory core region of a semiconductor memory device according to an embodiment of the present invention.

As shown, the semiconductor memory device according to an embodiment of the present invention, the row command control means 10 for generating a low read command signal rd_r and a low write command signal wt_r in response to the low command cmd_r. ); a row address decoder 11 which decodes n bits of row addresses add_r <1: n> to generate a plurality of row select signals xs; A word line driver (12) for activating any one of a plurality of word lines (WL) in response to the read instruction signal (rd), the write instruction signal (wt), and the plurality of row select signals (xs); A source line driver (13) for activating any one of a plurality of source lines (SL) in response to whether the read instruction signal (RD), the write instruction signal (wt), and the plurality of word lines (WL) are activated; Column command control means 14 for generating a column read instruction signal rd_c and a column write instruction signal wt_c in response to the column command cmd_c; A sense amplifier 15 that senses and amplifies output data d_out in response to the column read instruction signal rd_c and transmits the amplified output data to a data input / output bus IOBUS; A bit line driver 16 driving data transmitted from the data input / output bus IOBUS in response to the column write instruction signal wt_c to generate driving data d_drv; a column address decoder 17 for decoding a m bit column address add_c <1: m> to generate a plurality of column select signals ys; The driving data d_drv is transmitted to any one of the plurality of bit lines BL in response to the plurality of column selection signals ys, or data transmitted by any one of the plurality of bit lines BL is transmitted. A bit line mux 18 which is transmitted as the output data d_out to the sense amplifier 15; And a memory cell block 19 connected to the plurality of word lines WL, the plurality of source lines SL, and the plurality of bit lines BL, and having a plurality of memory cells.

Here, the memory cell block 19 includes a plurality of memory cells implementing FBC transistors, and the word line WL is provided as many as the number of rows of the plurality of memory cells and the source line SL. Is provided as many as one-half of the number of word lines WL, and the bit lines BL are provided as many as columns of a plurality of memory cells.

The low command cmd_r instructs an active operation so that the low read command signal rd_r and the column read command signal rd_c or the low write command signal wt_r and the column write command signal wt_c are When enabled, the memory cell block 19 performs a data input or output operation. To this end, the row address decoder 11 activates any one of the plurality of row select signals xs, and the column address decoder 17 activates any one of the plurality of column select signals ys. . Thereafter, the word line driver 12 activates any one of the plurality of word lines WL in response to the activated row select signal xs, and the bit line mux 18 selects the activated column. One of the plurality of bit lines BL is activated in response to the signal ys. The source line driver 13 activates any one of the plurality of source lines SL in response to the activated word line WL of the plurality of word lines WL.

Configurations such as the row command control means 10, the row address decoder 11, the column command control means 14, the sense amplifier 15 and the column address decoder 17 are generally semiconductor memory devices. As the components provided in the, corresponding to the configuration that can be easily implemented by those skilled in the art, more detailed description will be avoided.

The word line driver 12 classifies a read operation mode, a write operation mode, and a hold operation mode by using the low read instruction signal rd_r and the low write instruction signal wt_r, and writes according to respective operation modes. One of the gate voltage, the read gate voltage, and the hold gate voltage is supplied to the activated word line WL.

The source line driver 13 distinguishes a hold operation mode from an active operation mode, that is, a read operation mode and a write operation mode, by using the low read indication signal rd_r and the low write indication signal wt_r. The active source voltage or the hold source voltage is supplied to the active source line SL according to the operation mode.

The bit line driver 13 distinguishes whether or not to enter a write operation mode by using the column write indication signal wt_c, and determines whether a logic value of data is '0' or '1' during a write operation. The driving data d_drv is driven to the first write drain voltage or the second write drain voltage level.

The names of the gate voltage, the source voltage and the drain voltage are such that the word line WL is connected to a gate of a cell transistor in the memory cell block 19, and the source line SL is connected to a source of a cell transistor. This is given because the bit line BL is connected to the drain of the cell transistor. According to each operation mode, voltage generators for varying the voltage levels of the gate voltage, the source voltage and the drain voltage may be implemented using various kinds of voltage generators provided in a semiconductor memory device, which are described by those skilled in the art. It is not special.

FIG. 3 is a detailed configuration diagram of the memory cell block shown in FIG. 2 and illustrates only the arrangement relationship of the sixteen cell transistors for convenience of description.

As shown, the memory cell block 19 includes 16 cell transistors CTR <1:16> connected in series and in parallel and connected to a drain and a drain, a source and a source, respectively. Four word lines WL <1: 4> are connected to the gates of each cell transistor, and two source lines SL <1: 2> are connected to the sources of each cell transistor, respectively, and four bit lines. (BL <1: 4>) is respectively connected to the drain of each cell transistor.

As described above, since the cell transistor of the present invention is manufactured by implementing the FBC technology, each memory cell need not be provided with a switching transistor and a cell capacitor, and each transistor performs the function of the memory cell. Here, in order for each transistor to perform read, write and hold operations, the voltages applied to the gate, the source and the drain must have a voltage level set according to the operation mode. Therefore, each cell transistor is configured to operate in each operation mode according to the voltage provided through the word line WL, the voltage provided through the source line SL, and the voltage provided through the bit line BL. Can be implemented.

FIG. 4 is a detailed configuration diagram of the word line driver illustrated in FIG. 2 and illustrates only a configuration of providing a voltage to any one of the plurality of word lines WL <i> for convenience of description. It will be readily apparent to those skilled in the art that the configuration shown in the drawings is provided with the number of word lines WL.

As illustrated, the word line driver 12 may include a corresponding row select signal xs <i among the low write instruction signal wt_r, the low read instruction signal rd_r, and the plurality of row select signals xs. A first operation mode determination unit 122 generating a write mode signal wtmd, a read mode signal rdmd, and a first hold mode signal hdmd1 in response to > And the write gate voltage Vgwt, the read gate voltage Vgrd, and the hold gate voltage in response to the write mode signal wtmd, the read mode signal rdmd, and the first hold mode signal hdmd1. And a first switching unit 124 for supplying Vghd to the corresponding word line WL <i>.

The first operation mode determination unit 122 may include a first NAND gate ND1 configured to receive the row select signal xs <i> and the low write instruction signal wt_r; A first inverter IV1 receiving the output signal of the first NAND gate ND1 and outputting the write mode signal wtmd; A second NAND gate ND2 receiving the row select signal xs <i> and the low read command signal rd_r; A second inverter IV2 receiving the output signal of the second NAND gate ND2 and outputting the read mode signal rdmd; And a first NOR gate NR1 for receiving the low write instruction signal wt_r and the low read instruction signal rd_r and outputting the first hold mode signal hdmd1.

In addition, the first switching unit 124 may include a third inverter IV3 receiving the write mode signal wtmd; A first pass gate PG1 transferring the write gate voltage Vgwt to the word line WL <i> in response to the write mode signal wtmd and the output signal of the third inverter IV3; A fourth inverter IV4 receiving the read mode signal rdmd; A second pass gate PG2 transferring the read gate voltage Vgrd to the word line WL <i> in response to the read mode signal rdmd and the output signal of the fourth inverter IV4; A fifth inverter IV5 receiving the first hold mode signal hdmd1; And a third pass gate PG3 that transfers the hold gate voltage Vghd to the word line WL <i> in response to the first hold mode signal hdmd1 and the output signal of the fifth inverter IV5. );

Here, the levels of the write gate voltage Vgwt, the read gate voltage Vgrd, and the hold gate voltage Vghd may vary according to the characteristics of the cell transistor, but preferably 0.5 V and −1.0, respectively. V, -1.5V.

The first operation mode determination unit 122 may check the write mode signal wtmd when the row select signal xs <i> is enabled while the low write instruction signal wt_r is enabled. Let it be. The first switching unit 124 supplies the write gate voltage Vgwt to the word line WL <i> in response to the write mode signal wtmd being enabled.

On the other hand, when the row select signal xs <i> is enabled in the state in which the low read command signal rd_r is enabled, the first operation mode determiner 122 enables the read mode signal rdmd. Enable). The first switching unit 124 supplies the read gate voltage Vgrd to the word line WL <i> in response to the read mode signal rdmd being enabled.

On the other hand, if neither the low write indication signal wt_r nor the low read indication signal rd_r is enabled, the first operation mode determination unit 122 enables the first hold mode signal hdmd1. . The first switching unit 124 supplies the hold gate voltage Vhdmd to the word line WL <i> in response to the first hold mode signal hdmd1 being enabled.

FIG. 5 is a detailed configuration diagram of the source line driver illustrated in FIG. 2 and illustrates only a configuration of providing a voltage to one of the plurality of source lines SL <i> for convenience of description. It will be readily understood that the configuration shown in the drawings is provided with the number of source lines SL.

As illustrated, the source line driver 13 may generate a source line activation signal slact depending on whether the first adjacent word line WL <j> or the second adjacent word line WL <j + 1> is activated. Enable unit 132 for generating a); A second operation mode determination unit (134) configured to generate a second hold mode signal (hdmd2) in response to the low write indication signal (wt_r) and the low read indication signal (rd_r); And the active source voltage Vsac and the second hold source voltage Vshd to the corresponding source line SL <i> in response to the source line activation signal slact and the second hold mode signal hdmd2. It includes; the second switching unit 136 to supply.

The enable unit 132 has a first adjacent word line WL <j> and a second adjacent word line WL <j + 1> connected to an input terminal, and outputs the source line activation signal slact. It includes a second NOR gate (NR2).

In addition, the second operation mode determination unit 134 receives the low write instruction signal wt_r and the low read instruction signal rd_r and outputs the second hold mode signal hdmd2 to the third norgate ( NR3);

The second switching unit 136 may include: a first transistor TR1 having a source line activation signal applied to a gate terminal and an active source voltage Vsac applied to a source terminal; A second transistor having the second hold mode signal hdmd2 input to a gate terminal, a source terminal connected to a drain terminal of the first transistor TR1, and a source terminal connected to the source line SL <i>; TR2); A third transistor TR3 having the second hold mode signal hdmd2 input to a gate terminal thereof and a drain terminal thereof connected to the source line SL <i>; And a fourth transistor TR4 to which the source line activation signal slact is input to a gate terminal, a drain terminal is connected to a source terminal of the third transistor TR3, and the hold source voltage Vshd is applied to a source terminal. It includes;

Here, the first adjacent word line WL <j> and the second adjacent word line WL <j + 1> may be arranged in a cell transistor arrangement in the memory cell block 19 which can be seen through FIG. 3. In this case, the word lines are arranged on both sides of the source line SL <i>. Referring to FIG. 3, it can be seen that the source line SL is provided with only half of the number of word lines WL. Referring to FIG. 5, the source lines SL <i> are two adjacent word lines. It can be seen that (WL <j>, WL <j + 1>) can only be activated when it is activated.

Meanwhile, the levels of the active source voltage Vsac and the hold source voltage Vshd may vary according to characteristics of the cell transistor, but are preferably 2.5V and 0V, respectively.

By the above-described configuration, the source line activation signal slact may be activated only when the first adjacent word line WL <j> and the second adjacent word line WL <j + 1> are activated. have. The second hold mode signal hdmd2 is enabled when both the low write instruction signal wt_r and the low read instruction signal rd_r are disabled.

Accordingly, when the source line activation signal slact is enabled and an active operation mode, that is, a write operation mode and a read operation mode is performed, the active source voltage Vsac is supplied to the source line SL <i>. do. On the other hand, when the source line activation signal slact is enabled and the hold operation mode is performed, the hold source voltage Vshd is supplied to the source line SL <i>.

FIG. 6 is a detailed configuration diagram of the bit line mux shown in FIG. 2 and illustrates only a configuration connected to four BL <1: 4> of a plurality of bit lines for convenience of description. Accordingly, four column selection signals (ys <1: 4>) are also input to the configuration shown.

As illustrated, the bit line mux 18 receives the driving data d_drv from the bit line driver 16 and outputs the output data d_out to the sense amplifier 15. ; A fifth transistor TR5 having a first column selection signal ys <1> input to a gate terminal and disposed between a first bit line BL <1> and the input / output node Ni; A sixth transistor TR6 input to the gate end of the second column select signal ys <2> and disposed between the second bit line BL <2> and the input / output node Ni; A seventh transistor TR7 having a third column select signal ys <3> input to a gate terminal and disposed between a third bit line BL <3> and the input / output node Ni; And an eighth transistor TR8, in which a fourth column select signal ys <4> is input to a gate terminal, and disposed between the fourth bit line BL <4> and the input / output node Ni.

By such a configuration, the bit line mux 18 does not distinguish between the read operation mode, the write operation mode, and the hold operation mode, and the column address decoder 17 causes the m address column address (add_c <1: m). A plurality of bit lines BL and the input / output node Ni are connected under the control of the plurality of column selection signals ys decoded and output. In the write operation mode, since the sense amplifier 15 is deactivated and the bit line driver 16 is activated, the driving data d_drv may be transferred to the memory cell through one bit line BL. On the other hand, in the read operation mode, since the bit line driver 16 is inactivated and the sense amplifier 15 is activated, the output data d_out output from one of the memory cells through the designated bit line BL. May be output through the sense amplifier 15.

FIG. 7 is a detailed configuration diagram of the bit line driver shown in FIG. 2 and shows only some components for convenience of description. The configuration shown in the drawing can be understood as a circuit configuration for providing driving data d_drv to the input / output node Ni shown in FIG.

As illustrated, the bit line driver 16 may include a first write drain voltage (hereinafter referred to as a low level write voltage Vwl) or a second in response to input data d_in transmitted from the data input / output bus IOBUS. A third switching unit 162 selectively outputting a write drain voltage (hereinafter, referred to as a high level write voltage Vwh); And a data output unit 164 outputting the output signal of the third switching unit 162 as the driving data d_drv <i> in response to the column write instruction signal wt_c.

The third switching unit 162 may include a sixth inverter IV6 receiving the input data d_in; A fourth pass gate PG4 configured to pass the low level write voltage Vwl in response to the data input control signal cntdin and the output signal of the sixth inverter IV6; And a fifth pass gate PG5 configured to pass the high level write voltage Vwh in response to the data input control signal cntdin and the output signal of the sixth inverter IV6.

In the data output unit 164, the column write instruction signal wt_c is input to a gate terminal, an output signal of the third switching unit 162 is applied to a drain terminal, and the driving data d_drv <i through a source terminal. And a ninth transistor TR9 that outputs >

Here, the low level write voltage Vwl and the high level write voltage Vwh are voltages of levels that the driving data d_drv <i> should have when inputting data having a logic value of '0', respectively. As the voltage of the level that should be in and other cases, each potential level can vary according to the characteristics of the cell transistor, but is preferably 0.5V and 0V, respectively.

According to the above-described configuration, when the logic value of the input data d_in is '0', the fourth passgate PG4 of the third switching unit 162 is turned on, so that the low level The write voltage Vwl is transmitted to the data output unit 164. On the other hand, when the logic value of the input data d_in is '1', the fifth pass gate PG5 of the third switching unit 162 is turned on, so that the high level write voltage Vwh is the data. It is transmitted to the output unit 164.

The ninth transistor TR9 of the data output unit 164 receives a signal transmitted from the third switching unit 162 only when the column write instruction signal wt_c is enabled, and the driving data d_drv < i>). As a result, the driving data d_drv <i> has a significant value only in the write operation mode and has a voltage level corresponding to the logic value of the input data d_in.

As described above, the semiconductor memory device of the present invention may implement a memory cell block using a transistor implementing FBC technology. To this end, a plurality of word lines connected to gates of a plurality of cell transistors of a memory cell block, a plurality of source lines connected to a source, and a plurality of bit lines connected to a drain are provided, and a voltage set according to each operation mode. Is applied. With this configuration, the cell transistors implementing the FBC can perform operations according to respective operation modes by dividing logic values and hold operations of data input during read and write operations. As such, by implementing the memory cell using the FBC technology, the occupied area of the memory core region can be significantly reduced, and the integration degree of the semiconductor memory device can be significantly improved.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the embodiments described above are to be understood in all respects as illustrative and not restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 is a cross-sectional view of a transistor implementing FBC,

2 is a block diagram showing a configuration of a memory core region of a semiconductor memory device according to an embodiment of the present invention;

3 is a detailed configuration diagram of the memory cell block shown in FIG. 2;

4 is a detailed configuration diagram of the word line driver shown in FIG. 2;

5 is a detailed configuration diagram of the source line driver shown in FIG. 2;

6 is a detailed block diagram of the bit line mux shown in FIG.

FIG. 7 is a detailed configuration diagram of the bit line driver shown in FIG. 2.

<Description of the symbols for the main parts of the drawings>

10: row command control means 11: row address decoder

12: word line driver 13: source line driver

14 column command control means 16 bit line driver

17: column address decoder 19: memory cell block

Claims (21)

A memory cell block including a plurality of floating body cell (FBC) transistors each having a gate connected to a word line, a drain connected to a bit line and a source line, and a source, and sharing a source line to form a pair of transistors; A word line driver supplying a voltage to the word line in accordance with an operation mode; A source line driver supplying a voltage to the source line according to an operation mode; And A bit line driver supplying a voltage to the bit line according to an operation mode; Including; The bit line driver may use the column write indication signal to distinguish whether the device enters the write operation mode, determine the logic value of the data during the write operation, and move the driving data to the first write drain voltage or the second write drain voltage level. And driving the semiconductor memory device. The method of claim 1, And the plurality of FBC transistors of the memory cell block perform a read operation, a write operation, or a hold operation according to voltages applied to the gate, the drain, and the source, respectively. The method of claim 1, The word line driver may distinguish between a read operation mode, a write operation mode, and a hold operation mode by using a low read indication signal and a low write indication signal, and read gate voltage, write gate voltage, and hold gate voltage according to each operation mode. And supplying any one of them to a word line activated by a row select signal. The method of claim 3, wherein The word line driver, An operation mode determination unit configured to generate a write mode signal, a read mode signal, and a hold mode signal in response to the low write indication signal, the low read indication signal, and the row selection signal; And A switching unit configured to supply one of the write gate voltage, the read gate voltage, and the hold gate voltage to the word line in response to the write mode signal, the read mode signal, and the hold mode signal; A semiconductor memory device comprising a. The method of claim 3, wherein The source line driver may distinguish between an active operation mode and a hold operation mode by using the low read indication signal and the low write indication signal, and activate an active source voltage or a hold source voltage to a source line that is activated according to each operation mode. Supplying a semiconductor memory device. The method of claim 5, wherein The source line driver, An enable unit configured to generate a source line enable signal according to whether the first adjacent word line or the second adjacent word line is activated; An operation mode determination unit configured to generate a hold mode signal in response to the low write indication signal and the low read indication signal; And A switching unit configured to supply the active source voltage or the hold source voltage to the source line in response to the source line activation signal and the hold mode signal; A semiconductor memory device comprising a. The method of claim 6, And the first adjacent word line and the second adjacent word line are word lines connected to respective gates of cell transistors sharing the source line. The method of claim 3, wherein Low command control means for generating the low read indication signal and the low write indication signal in response to a low command; And A row address decoder configured to decode a plurality of row addresses to generate a plurality of row selection signals; The semiconductor memory device further comprises. delete The method of claim 1, The bit line driver, A switching unit selectively outputting the first light drain voltage or the second light drain voltage in response to input data transmitted from a data input / output bus; And A data output unit outputting the output signal of the switching unit as the drive data in response to the column write instruction signal; A semiconductor memory device comprising a. The method of claim 10, Column command control means for generating a column read instruction signal and the column write instruction signal in response to a column command; A sense amplifier which senses and amplifies output data in response to the column read instruction signal and transfers the output data to the data input / output bus; A column address decoder for decoding a plurality of column addresses and generating a plurality of column selection signals; And A bit line mux for transmitting the driving data to any one of the plurality of bit lines in response to the plurality of column selection signals, or for transmitting the data transmitted by any one of the plurality of bit lines to the sense amplifier as the output data. ; The semiconductor memory device further comprises. A first floating body cell transistor; A second FBC transistor sharing a source with the first FBC transistor; A word line driver providing one of a write gate voltage, a read gate voltage, and a hold gate voltage to the first and second FBC transistors; A source line driver providing an active source voltage or a hold source voltage to the first and second FBC transistors; And A bit line driver providing a first write drain voltage or a second write drain voltage to the first and second FBC transistors; Including; And the first FBC transistor and the second FBC transistor are connected to different word lines. The method of claim 12, Wherein the first and second FBC transistors perform a read operation, a write operation, or a hold operation in response to voltages provided by the word line driver, the source line driver, and the bit line driver, respectively. Memory device. The method of claim 12, The word line driver may distinguish a read operation mode, a write operation mode, and a hold operation mode by using a low read indication signal and a low write indication signal, and the read gate voltage, the write gate voltage, and the read operation mode according to each operation mode. And one of the hold gate voltages is supplied to a word line connected to the first FBC transistor or a word line connected to the second FBC transistor. The method of claim 14, The word line driver, An operation mode determination unit configured to generate a write mode signal, a read mode signal, and a hold mode signal in response to the low write indication signal and the low read indication signal; And A switching unit configured to supply one of the write gate voltage, the read gate voltage, and the hold gate voltage to the word line in response to the write mode signal, the read mode signal, and the hold mode signal; A semiconductor memory device comprising a. The method of claim 14, The source line driver may distinguish between an active operation mode and a hold operation mode by using the low read indication signal and the low write indication signal, and convert an active source voltage or a hold source voltage into the first FBC transistor according to each operation mode. And the source line, which is commonly connected to a source of the transistor and a source of the second FBC transistor. The method of claim 16, The source line driver, An operation mode determination unit configured to generate a hold mode signal in response to the low write indication signal and the low read indication signal; And A switching unit configured to supply the active source voltage or the hold source voltage to the source line in response to the hold mode signal; A semiconductor memory device comprising a. The method of claim 14, And low command control means for generating the low read command signal and the low write command signal in response to a low command. The method of claim 12, The bit line driver may use the column write indication signal to distinguish whether the device enters the write operation mode, determine the logic value of the data during the write operation, and determine driving data as the first write drain voltage or the second write drain voltage. And driving at a level to provide to each drain of the first and second FBC transistors. The method of claim 19, The bit line driver, A switching unit selectively outputting the first light drain voltage or the second light drain voltage in response to input data transmitted from a data input / output bus; And A data output unit outputting the output signal of the switching unit as the drive data in response to the column write instruction signal; A semiconductor memory device comprising a. The method of claim 19, And column command control means for generating the column write instruction signal in response to a column command.

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