KR100905469B1 - A thin film transistor and the method thereof - Google Patents

Abstract

The thin film transistor substrate according to the present invention includes a gate wiring for transmitting a scan signal, a data wiring crossing the insulation with the gate wiring to transfer an image signal, and a thin film transistor connected to the gate wiring and the data wiring. A thin film transistor substrate comprising: a shorting bar connected to a predetermined area of a gate line and a data line and formed of a conductive semiconductor material.

Static electricity, shorting bar, polysilicon

Description

A thin film transistor substrate and a method of manufacturing the same

1A is a layout view of a thin film transistor substrate according to a first exemplary embodiment of the present invention.

FIG. 1B is a cross-sectional view taken along line Ib-Ib 'of FIG. 1A.

2A to 2F are diagrams sequentially illustrating a manufacturing process of the thin film transistor substrate according to the first embodiment.

3 is a layout view of a thin film transistor substrate according to a second exemplary embodiment of the present invention.

4 is a layout view of a thin film transistor substrate according to a third exemplary embodiment of the present invention.

5A is a layout view of a thin film transistor substrate according to a fourth exemplary embodiment of the present invention.

FIG. 5B is a cross-sectional view taken along lines Vb-Vb 'and Vb' Vb of FIG. 5A.

6A through 6D are diagrams sequentially illustrating a manufacturing process of a thin film transistor substrate according to a fourth exemplary embodiment of the present invention.

7A is a layout view of a thin film transistor substrate according to a fifth exemplary embodiment of the present invention.

FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb ′ of FIG. 7A.

※ Explanation of symbols on main parts of drawing ※

110: insulating substrate 111: shading pattern

121: gate line 123: gate electrode                 

125: gate pad 131: sustain electrode line

133 sustain electrode 140 gate insulating film

153: source region 154: channel region

155: drain region 157: holding region

171: data line 173: source electrode

175: drain electrode

The present invention relates to a thin film transistor substrate having a shorting bar.

The thin-film transistor substrate (TFT) is used as a circuit board for independently driving each pixel in a liquid crystal display device, an organic electroluminescence (EL) display device, or the like. The thin film transistor substrate includes a scan signal line or a gate line for transmitting a scan signal and an image signal line or data line for transmitting an image signal, a thin film transistor connected to the gate line and a data line, and a pixel connected to the thin film transistor. A gate insulating layer covering and insulating an electrode, a gate wiring, and an interlayer insulating layer covering and insulating a thin film transistor and a data wiring.

Since the thin film transistor substrate is an insulator on which the gate wiring and the data wiring are formed, the static electricity generated during the manufacturing process flows into the wiring and is present locally.

Even if a small amount of static electricity flows in, the voltage is increased by being present locally at the flowed portion, thereby causing damage to devices such as thin film transistors and causing disconnection of wiring.

Therefore, a shorting bar or a guard ring connects all the gate wirings and the data wirings inside and outside the gate pad and the data pad to reduce static electricity defects, thereby preventing or preventing static electricity. Doing.

When the shorting bar is used, the thin film transistor and the bar are separated in the final process of manufacturing the thin film transistor substrate. Therefore, the end portion of the shorting bar made of metal may be corroded while being exposed to the outside air.

Accordingly, an object of the present invention is to provide a thin film transistor substrate that does not corrode the shorting bar even when exposed to outside air.

The thin film transistor substrate according to the present invention for achieving the above object is formed on the insulating substrate and the gate wiring for transmitting the scan signal, the data wiring, the gate wiring and the data wiring to transfer the image signal by being insulated from the gate wiring; A thin film transistor substrate including thin film transistors connected to each other, the thin film transistor substrate further comprising a shorting bar connected to a predetermined region of the gate line and the data line and formed of a conductive semiconductor material.

More specifically, an insulating substrate, an active layer including a source region, a drain region, and a channel region formed on the substrate, a gate insulating layer formed on the active layer, a gate line formed in a predetermined region on the gate insulating layer, and a gate pad A first interlayer insulating layer formed on the gate wiring, the first contact hole exposing the source region and the second contact hole exposing the drain region; A data line including a data line connected to the source region through a sphere, a drain electrode connected to the drain region through a second contact hole, and a data pad formed at one end of the data line, and formed on the data line and exposing the drain electrode. A second interlayer insulating layer including a third contact hole, a second interlayer insulating layer The semiconductor device may include a shorting bar formed on the same layer as the pixel electrode, the source region, or the drain region connected to the drain electrode through the third contact, and connected to the gate pad and the data pad.

Another thin film transistor substrate for achieving the above object is an insulating substrate, an active layer including a source region, a drain region, a channel region, a gate line, a gate electrode formed in a predetermined region on the gate insulating layer, A gate wiring including a gate pad, a data metal piece spaced apart from the gate line by a predetermined distance, and separated up and down with a gate line therebetween, a data pad formed in a predetermined region of the data metal piece, and formed on a substrate and having one end of the data metal piece An interlayer insulating layer including first and second contact holes exposing the second and second ends, a third contact hole exposing the drain region, and an interlayer insulating layer formed on the interlayer insulating layer and adjacent to each other through the first and second contact holes. It is formed on the data connection part and the interlayer insulating layer which contact and connect data metal pieces. And a shorting bar formed on the same layer as the pixel electrode, the source region, and the drain region connected to the drain region through the third contact hole and connected to the data pad and the gate pad.

And an insulating substrate, a gate wiring including a gate line, a gate electrode, and a gate pad, a gate insulating layer formed on the gate wiring, and a semiconductor layer and a semiconductor layer formed in a predetermined region on the gate insulating layer. An interlayer insulating layer including an ohmic contact layer formed in an area other than a predetermined region, a data line formed on the ohmic contact layer, a data line including a data pad, a source electrode and a drain electrode, and a contact hole exposing the drain electrode The pixel electrode may be connected to the drain electrode through the contact hole, and the shorting bar may be formed of the same material as the ohmic contact layer and may be connected to the gate pad and the data pad.

A method for forming such a substrate may include forming an amorphous silicon layer on an insulating substrate, crystallizing the amorphous silicon layer, and then patterning to form first and second polycrystalline silicon patterns, and first and second polycrystalline silicon. Forming a gate insulating layer on the pattern and forming first and second contact holes by a photolithography process; a gate line formed in a predetermined region on the gate insulating layer, a gate electrode which is a part of the gate line, and one end of the gate line Forming a gate wiring including a gate pad formed through the first contact hole and connected to the second polycrystalline silicon pattern, and doping the n-type or p-type impurity to the first polycrystalline silicon pattern using the gate wiring as a mask To form an active layer including a source region, a drain region, and a channel region that is not doped with impurities, and simultaneously impure in the second polycrystalline silicon pattern. Forming a shorting bar by doping with water, forming a third contact hole exposing the source region and a fourth contact hole exposing the drain region and a fifth contact hole exposing the second contact hole on the gate wiring; Data including a data line connected to the source region through the third contact hole, a drain electrode connected to the drain region through the fourth contact hole, and a data pad connected to the shorting bar through the second and fifth contact holes on the interlayer insulating layer. Forming a wiring, forming a sixth contact hole exposing the drain electrode on the data wiring, and forming a pixel electrode connected to the drain electrode through the sixth contact hole on the second interlayer insulating layer. do.

Or forming an amorphous silicon layer on the insulating substrate, crystallizing the amorphous silicon layer, and then patterning to form the first and second polycrystalline silicon patterns, and forming a gate insulating layer on the first and second polycrystalline silicon patterns. Forming a first contact hole and a second contact hole by a photolithography process; a gate line including a gate line on the gate insulating layer, a gate pad connected to the second polysilicon pattern through the first contact hole, and a gate electrode; Forming a data metal piece including a data pad connected to the second polycrystalline silicon pattern through a second contact hole; n-type or p on the first polycrystalline silicon pattern and the second polycrystalline silicon pattern using the gate wiring and the data metal piece as a mask; The active layer and the shorting bar including a source region doped with dopants, a drain region, and a channel region not doped with impurities. Forming, forming an interlayer insulating layer over the gate wiring and the data metal piece, a third contact hole exposing the source region to the interlayer insulating layer, a fourth contact hole exposing the drain region, and a fifth contact exposing the data metal piece And forming a pixel electrode connected to the source region, the drain region, and the data metal piece through the third, fourth, and fifth contact holes on the interlayer insulating layer.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

It will now be described in detail with reference to the drawings with reference to embodiments of the present invention.

[Examples 1 and 2]

FIG. 1A is a schematic layout view of a thin film transistor substrate according to an exemplary embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along line Ib-Ib 'of FIG. 1A.

As illustrated, a plurality of gate lines 121, 123, and 125 are formed in one direction on the substrate 110, and a plurality of gate lines 121, 123, and 125 intersect with the gate lines 121, 123, and 125 to define the pixel area PX. Data lines 171, 173, 175, and 179 are formed. The storage electrode wirings 131, 133, and 135 for increasing the storage capacitance are formed so as to be positioned between the gate wirings 121, 123, and 125.

One end of each of the data wires 171, 173, 175, and 179, the gate wires 121, 123, and 125, and the sustain electrode wires 131, 133, and 135 is connected to the shorting bar 201 to flow into each wire. The static electricity to be delivered to the shorting bar 201.

In more detail, the blocking layer 111 is formed on the transparent insulating substrate 110. An active layer 150 including a source region 153, a channel region 154, a drain region 155, and a storage region is formed in a predetermined region on the blocking layer 111. The shorting bar 201 is formed on the same layer as the active layer 150. The shorting bar 201 is formed of the same material as the source region 153 or the drain region 155. The storage region 157 overlaps with the storage electrode 133 to increase the storage capacitance.

A gate insulating layer 140 having first, second, and third contact holes 161, 162, and 163 exposing the shorting bar 201 is formed on the active layer 150 and the shorting bar. The gate line 121 formed on the gate insulating layer 140 in one direction, the gate electrode 123 which is a part of the gate line 121, and the gate pad 125 formed at one end of the gate line 121. Gate wirings 121, 123, and 125 are formed. The gate pad 125 is connected to the shorting bar 201 through the first contact hole 161.

In addition, the storage electrode wirings 131, 133, and 135 are used to increase the storage capacitance, and include the storage electrode line 131, the storage electrode 133, and the storage pad 135. 121 is formed to be parallel to the predetermined distance apart. At this time, the storage electrode 133, which is a part of the storage electrode line 131, is formed to overlap the storage region 157. In addition, the holding pad 135 is connected to the shorting bar 201 through the third contact hole 163.                     

The fourth contact hole 164 exposing the source region 153, the fifth contact hole 165 exposing the drain region 155, and the sixth contact hole exposing the second contact hole 162 may be disposed on the gate line. A first interlayer insulating layer 801 including 166 is formed. The data line 171 and the fifth contact hole 165 intersect with the gate line 121 on the first interlayer insulating layer 801 and are connected to the source region 153 through the fourth contact hole 164. Data lines 171, 173, 175, and 179 including a drain electrode 175 connected to the drain region 155, and a data pad 179 connected to the shorting bar 201 through second and sixth contact holes. Is formed.

The second interlayer insulating layer 802 including the seventh contact hole 167 is formed on the data line, and the drain electrode 175 is formed on the second interlayer insulating layer 802 through the seventh contact hole 167. The pixel electrode 190 to be connected is formed.

In order to increase the resistance of the shorting bar 201 than the first embodiment, the shorting bar 201 may be zigzag as shown in FIG. 3 (second embodiment).

A method of forming a thin film transistor substrate according to a first embodiment of the present invention will be described with reference to FIGS. 2A to 2F.

First, as shown in FIG. 2A, the blocking layer 111 and the amorphous silicon layer are sequentially stacked on the transparent insulating substrate 110. The first and second polycrystalline silicon patterns 150a and 150b are formed by heat treatment of the amorphous silicon layer and crystallization thereof, followed by patterning by a photolithography method.

In this case, glass, quartz, or sapphire may be used as the transparent insulating substrate 110. The blocking layer 111 is formed by depositing silicon oxide (SiO ₂ ) or silicon nitride (SiNx), and an amorphous silicon layer. Silver is formed by depositing amorphous silicon by Chemical Vapor Deposition (CVD). And heat treatment uses a laser annealing (furnace annealing) or furnace annealing (furnace annealing).

As shown in FIG. 2B, the gate insulating layer 140 is formed on the polycrystalline silicon patterns 150a and 150b and then patterned by a photolithography process to form first, second and third contact holes 161, 162 and 163. do.

As illustrated in FIG. 2C, the conductive layers are formed on the first, second, and third contact holes 161, 162, and 163, and then patterned by a photolithography process to form the gate wirings 121, 123, 125, and the storage electrode wirings ( 131, 133, and 135.

The gate pad 125, the data pad 179, and the sustain pad 135 may each have a second polycrystalline silicon pattern (via the first contact hole 161, the second contact hole 162, and the third contact hole 163). 150b).

Thereafter, high concentration impurities are implanted into the first and second polycrystalline silicon patterns 150a and 150b using the gate wirings 121, 123 and 125 and the sustain electrode wirings 131, 133 and 135 as masks. The first polysilicon pattern 150a may be an active layer 150 including a source region 153, a drain region 155, a channel region 154, and a storage region 157. The second polycrystalline silicon pattern 150b may be a shorting bar 201 for preventing static electricity.

The channel region 154 is a region where impurities are not implanted and is disposed under the gate electrode 123 to separate the source region 153 and the drain region 155. In the storage region 157, impurities are not implanted, and the storage region 157 is disposed under the storage electrode 133 to increase the storage capacitance.

As shown in FIG. 2D, an insulating material is deposited on the entire surface of the substrate to form a first interlayer insulating layer 801.

Thereafter, the fourth contact hole 164 exposing the source region 153, the fifth contact hole 165 exposing the drain region 155, and the second contact hole are exposed to the first interlayer insulating layer 801. The sixth contact hole 166 exposing the portion is formed.

As illustrated in FIG. 2E, a conductive layer is formed on the first interlayer insulating layer 801 and then patterned to form a data line 171 including a data line 171, a data pad 179, and a drain electrode 175. 173, 175.

The data line 171 is formed to cross the gate line 121 to define the pixel area PX, and is connected to the source area 153 through the first contact hole 161. The drain electrode 175 is connected to the drain region 155 through the second contact hole 162, and the data pad 179 shows through the sixth contact hole 166 and the second contact hole 162. Connect with the putting bar 201.

Thereafter, an insulating material is stacked on the first interlayer insulating layer 801 to form a second interlayer insulating layer 802.

A seventh contact hole 167 exposing the drain electrode 175 is formed in the second interlayer insulating layer 802 by a photolithography method. The pixel electrode 190 is formed by depositing and patterning a transparent conductive metal on the second interlayer insulating layer 802. The pixel electrode 190 is connected to the drain electrode 175 through the seventh contact hole 187. (See Figure 1A)

Third Embodiment

As shown in FIG. 4, the shorting bar includes a first shorting bar connected to the gate pad 125 and a second shorting bar connected to the data pad 179.

That is, after completing the manufacturing process of the first embodiment, the predetermined region of the shorting bar connected to the gate pad 125 and the data pad 179 is cut or scribed with a laser and separated.

[Example 4]

FIG. 5A is a schematic layout view of a thin film transistor substrate according to a fourth exemplary embodiment of the present invention, and FIG. 5B is a cross-sectional view taken along lines Vb-Vb 'and Vb'-Vb of FIG. 5A.

As illustrated, a blocking layer 111 is formed on the transparent insulating substrate 110. An active layer 150 including a source region 153, a channel region 154, a drain region 155, and a storage region is formed in a predetermined region on the blocking layer 111. The shorting bar 201 is formed on the same layer as the active layer 150. The shorting bar 201 is formed of the same material as the source region 153 or the drain region 155. The storage region 157 increases the storage capacitance to a region overlapping the storage electrode 133.

A gate insulating layer 140 having first, second, and third contact holes 161, 162, and 163 exposing the shorting bar 201 is formed on the active layer 150 and the shorting bar. Gate wirings 121, 123, and 125, data metal pieces 171a, and sustain electrode wirings 131, 133, and 135 are formed on the gate insulating layer 140.                     

The gate wires 121, 123, and 125 are formed on one end of the gate line 121, the gate electrode 123, which is a part of the gate line 121, and the gate line 121, which are formed to extend in one direction. And 125. The gate pad 125 is connected to the shorting bar 201 through the first contact hole 161.

The data metal piece 171a is spaced apart from the gate line 121 by a predetermined distance and extends in a direction perpendicular to the gate line 121, and is formed on the same layer as the gate line 121. That is, the data metal piece 171a is formed not to be connected to the gate line 121 between two adjacent gate lines 121. Here, the data metal piece 171a which is spaced apart from the first or last gate line by a predetermined distance and is not located between the gate line and the gate line includes a data pad 179 for receiving an image signal from an external circuit. The data pad 179 is connected to the shorting bar 201 through the second contact hole 162.

In addition, the storage electrode wirings 131, 133, and 135 are used to increase the storage capacitance, and include the storage electrode line 131, the storage electrode 133, and the storage pad 135. 121 is formed to be parallel to the predetermined distance apart. At this time, the storage electrode 133, which is a part of the storage electrode line 131, is formed to overlap the storage region 157. In addition, the holding pad 135 is connected to the shorting bar 201 through the third contact hole 163.

An interlayer insulating layer 160 is formed on the gate wirings 121, 123, and 125 and the data metal piece 171a.                     

The data connector 171b, the pixel electrode 190, the auxiliary gate pad 95, and the auxiliary data pad 97 are formed on the interlayer insulating layer 160.

The data connector 171b is connected to the data metal piece 171a through the sixth contact hole 166 formed in the interlayer insulating layer 160, and the source region 153 and the fourth contact hole 164. It is connected. That is, the data metal pieces 171a separated by the data connection part 171b are connected across the gate line 121.

The pixel electrode 190 is connected to the drain region 155 through the fifth contact hole 165. The auxiliary gate pad 95 is connected to the gate pad 125 through the seventh contact hole 167, and the auxiliary data pad 97 is connected to the auxiliary data pad 97 through the eighth contact hole 168. do.

In order to increase resistance of the shorting bar as in the second and third embodiments, the shorting bar may be formed in a zigzag pattern, or may be separated from the first shorting bar connected to the gate pad 125 and the second shorting bar connected to the data pad 179. Can be formed (not shown).

A method of forming a thin film transistor having such a structure will be described with reference to FIGS. 6A to 6D.

First, as shown in FIG. 6A, the blocking layer 111 and the amorphous silicon layer are laminated and heat treated on the transparent insulating substrate 110 to crystallize the amorphous silicon layer. Thereafter, the amorphous silicon layer is patterned to form first and second polycrystalline silicon patterns 150a and 150b.

After the gate insulating layer 140 is formed on the first and second polycrystalline silicon patterns 150a and 150b, the first, second and third contact holes 161, 162 and 163 are formed by a photolithography process.                     

As shown in FIG. 6B, the conductive layer is formed on the gate insulating layer 140 and then patterned by a photolithography process to form the gate wirings 121, 123, and 125 and the data metal piece 171a.

In this case, the gate pad 125, the data pad 179, and the sustain pad 135 are connected to the second polycrystalline silicon pattern 150b through first, second, and third contact holes, respectively.

As shown in FIG. 6C, the source wirings 153, the drain region 155, and the impurities are doped with high concentrations of n-type or p-type impurities using the gate wirings 121, 123, 125, and the data metal piece 171a as a mask. The active layer 150 and the shorting bar 201 including the undoped channel region 154 are formed.

As shown in FIG. 6D, an interlayer insulating layer 160 is formed over the gate wirings 121, 123, 125 and the data metal piece 171a. In addition, a fourth contact hole 164 exposing the source region 153, a fifth contact hole 165 exposing the drain region 155, and a sixth contact hole exposing the data metal piece 171a may be exposed by a photolithography process. 166, a seventh contact hole 167 exposing the gate pad 125, and an eighth contact hole 168 exposing the data pad 179.

The data connection part 171b and the fifth contact which are connected to the source region 153 through the first contact hole 161 and the data metal piece 171a through the sixth contact hole 165 on the interlayer insulating layer 160. The pixel electrode 190 connected to the drain region 155 is formed through the sphere 164. The auxiliary data pad 95 is connected to the gate pad 125 through the seventh contact hole, and the auxiliary data pad 179 is connected to the data pad 179 through the eighth contact hole. (See Figure 5A)

[Example 5]

Although the thin film transistor substrate using polycrystalline silicon has been described above, it can be applied to the thin film transistor substrate using amorphous silicon.

7A is a schematic layout view of a thin film transistor substrate according to a sixth exemplary embodiment of the present invention, and FIG. 7B is a cross-sectional view taken along line VIIb-VIIb ′ of FIG. 7A.

A gate line including a gate line 121, a gate electrode 123, and a gate pad 125 is formed on the transparent insulating substrate 110. The gate insulating layer 140 including the first contact hole 181 exposing the gate pad 125 is formed on the gate lines 121, 123, and 125.

The semiconductor layer 154 formed of a semiconductor material such as amorphous silicon is formed on the gate insulating layer 140 corresponding to the gate electrode 123. The ohmic contact layers 161, 163, 165, 167, and 169 formed by highly doping n-type or p-type impurities in a semiconductor material such as amorphous silicon in a predetermined region of the gate insulating layer including the semiconductor layer 154. And a shorting bar 201 is formed. The shorting bar 201 is connected to the gate pad 125 through the first contact hole 181.

Data lines 171, 173, 175, 177, and 179 are formed on the ohmic contacts 161, 163, and 165 and the shorting bar 202. The data lines 171, 173, 175, and 179 are branches of the data line 171 and the data line 171 that vertically intersect the gate line 121 to define the pixel area PX, and are the ohmic contact layer 163. It is connected to one end of the source electrode 173 and the data line 171 which is also connected to and is separated from the data pad 179 and the source electrode 173 for receiving an image signal from the outside, and with respect to the gate electrode 123. And a drain electrode 175 formed over the ohmic contact layer 165 opposite the source electrode 173. The data pad 179 is formed to partially overlap the shorting bar.

The second contact hole 182 exposing the drain electrode 175, the third contact hole 183 exposing the gate pad 125, and the fourth contact hole 184 exposing the data pad 125 are disposed on the substrate. The protective layer 180 having the fifth contact hole 185 exposing the storage capacitor electrode 177 is formed.

The pixel electrode 190 connected to the drain electrode 175 is formed on the passivation layer 180 through the second and fifth contact holes 182 and 185, respectively.

In the present exemplary embodiment, the shorting bar may be formed to be separated into a first shorting bar connected to the gate pad 125 and a second shorting bar connected to the data pad 179, or may be formed in a zigzag pattern (not shown).

The shorting bar according to the present invention has been described with respect to the shorting bar connected to each data pad and the gate pad by connecting the data line and the gate line to one or by cutting. However, the first shorting bar which binds each data pad to one and the second shorting bar which binds the gate pad to one may be formed.

As described above, preferred embodiments of the present invention have been described in detail, but the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of the present invention.

As described above, when the shorting bar for inducing static electricity is formed by using silicon doped with impurities, the shorting bar is not corroded even when exposed to the outside.

Claims (11)

A thin film transistor substrate comprising: a gate wiring formed on an insulating substrate and transmitting a scan signal; a data wiring crossing the insulating wiring so as to be insulated from the gate wiring; and a thin film transistor connected to the gate wiring and the data wiring. , And a shorting bar connected to a predetermined area of the gate line and the data line and formed of a conductive semiconductor material.  In claim 1, The gate line includes a gate line, a gate pad, and a gate electrode, and the data line includes a data line, a source electrode, a drain electrode, a data line, and a data pad, and the shorting bar includes the gate pad or the data pad. A thin film transistor substrate connected with the. The method of claim 1 or 2, And the conductive semiconductor material is silicon doped with n-type or p-type impurities. Insulation board, An active layer formed on the substrate and including a source region, a drain region, and a channel region, A gate insulating layer formed on the active layer, A gate wiring including a gate line, a gate pad, and a gate electrode formed in a predetermined region on the gate insulating layer; A first interlayer insulating layer formed on the gate line and including a first contact hole exposing the source region and a second contact hole exposing the drain region; And a data line crossing the gate line and connected to the source region through the first contact hole, a drain electrode connected to the drain region through the second contact hole, and a data pad formed at one end of the data line. Data wiring, A second interlayer insulating layer formed on the data line and including a third contact hole exposing the drain electrode; A pixel electrode formed on the second interlayer insulating layer and connected to the drain electrode through the third contact hole; And a shorting bar formed on the same layer as the source region or the drain region and connected to the gate pad and the data pad. Insulation board, An active layer formed on the substrate and including a source region, a drain region, and a channel region, A gate insulating layer formed on the active layer, A gate wiring including a gate line, a gate electrode, and a gate pad formed in a predetermined region on the gate insulating layer; A data metal piece spaced apart from the gate line by a predetermined distance and separated vertically with the gate line interposed therebetween; A data pad formed in a predetermined region of the data metal piece, An interlayer insulating layer formed on the substrate and including first and second contact holes exposing one end and the other end of the data metal piece and a third contact hole exposing a drain region; A data connection portion formed on the interlayer insulating layer and contacting and connecting two data metal pieces adjacent to each other through the first and second contact holes; A pixel electrode formed on the interlayer insulating layer and connected to the drain region through the third contact hole; And a shorting bar formed on the same layer of the same material as the source region and the drain region and connected to the data pad and the gate pad. Insulation board, A gate wiring formed on the substrate and including a gate line, a gate electrode, and a gate pad; A gate insulating layer formed on the gate wiring; A semiconductor layer formed in a predetermined region on the gate insulating layer, An ohmic contact layer formed in a region other than a predetermined region of the semiconductor layer, A data line including a data line, a data pad, a source electrode, and a drain electrode formed on the ohmic contact layer; An interlayer insulating layer including a contact hole exposing the drain electrode; A pixel electrode connected to the drain electrode through the contact hole; And a shorting bar formed on the same layer using the same material as the ohmic contact layer and connected to the gate pad and the data pad. The method of claim 4 or 5, The gate pad or the data pad is connected to the shorting bar through a contact hole formed in the gate insulating layer or the interlayer insulating layer. In claim 6, And the gate pad is connected to the shorting bar through a contact hole formed in the gate insulating layer. Forming an amorphous silicon layer on the insulating substrate, Crystallizing the amorphous silicon layer and then patterning to form first and second polycrystalline silicon patterns, Forming a gate insulating layer on the first and second polycrystalline silicon patterns and then forming first and second contact holes by a photolithography process; A gate pad formed in a predetermined region on the gate insulating layer, a gate electrode which is a part of the gate line, and a gate pad formed at one end of the gate line and connected to the second polycrystalline silicon pattern through the first contact hole; Forming a gate wiring comprising: Doping n-type or p-type impurities in the first polycrystalline silicon pattern using the gate wiring as a mask to form an active layer including a source region, a drain region, and a channel region in which the impurities are not doped, and simultaneously to the second polycrystalline silicon pattern. Doping impurities to form a shorting bar, Forming a third contact hole exposing the source region, a fourth contact hole exposing the drain region, and a fifth contact hole exposing the second contact hole on the gate wiring; The shorting through the data line connected to the source region through the third contact hole, the drain electrode connected to the drain region through the fourth contact hole, and the second and fifth contact holes on the first interlayer insulating layer. Forming a data line comprising a data pad connected to the bar, Forming a sixth contact hole exposing the drain electrode on the data line; Forming a pixel electrode on the second interlayer insulating layer, the pixel electrode being connected to the drain electrode through the sixth contact hole; Method of manufacturing a thin film transistor substrate comprising a. Forming an amorphous silicon layer on the insulating substrate, Crystallizing the amorphous silicon layer and then patterning to form first and second polycrystalline silicon patterns, Forming a gate insulating layer on the first and second polycrystalline silicon patterns and then forming first and second contact holes by a photolithography process; A gate line on the gate insulating layer, a gate line including a gate pad and a gate electrode connected to the second polysilicon pattern through the first contact hole, and a gate line including a gate electrode and a second contact hole to the second polycrystalline silicon pattern; Forming a data metal piece including a data pad, N-type or p-type impurities are doped into the first polycrystalline silicon pattern and the second polycrystalline silicon pattern by using the gate wiring and the data metal piece as masks, so that the source region, the drain region, and the channel region without impurities are doped. Forming an active layer and a shorting bar comprising: Forming an interlayer insulating layer over said gate wiring and data metal piece, Forming a third contact hole exposing the source region, a fourth contact hole exposing the drain region, and a fifth contact hole exposing the data metal piece in the interlayer insulating layer; Forming a pixel electrode connected to the source region, the drain region, and the data metal piece through the third, fourth, and fifth contact holes on the interlayer insulating layer, Method of manufacturing a thin film transistor substrate comprising a. The method of claim 10, The data metal piece is spaced apart from the gate line by a predetermined distance and formed to be separated up and down with the gate line therebetween. And forming a data connection portion intersecting the gate line.

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